Xavier Series

Xavier Series SoC Technical Reference Manual

XAVIER | TRM | DP-09253-002_v1.1 | SUBJECT TO CHANGE | www.nvidia.com Page of 1 8287

DP-09253-002

ID:

10-Dec-2018 15:50

Date:

1.1

Version:

Technical Reference Manual

Xavier Series SoC

Abstract

The Technical Reference Manual focuses on the logical organization and control of

Xavier Series SoC. It provides information for those modules that interface to external

devices, or those that control fundamental chip operations. The modules detailed in

this document provide an overview, any necessary programming guidelines, and a

hardware acceleration are controlled by NVIDIA provided software and not

documented here.

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Table of Contents
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  10
Introduction  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  11
1 Reading Register Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  13
2 Units  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  15
3 Glossary  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  15
Memory Architecture and Memory Mapped I/O . . . . . . . . . . . . . . . . . . . . .  24
1 Address Map  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  24
1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  24
1.2 AMAP and Aperture  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  25
1.3 System Address Map  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  29
2 Address Space Translation (AST)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  71
2.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  71
2.2 Functional Description  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  73
2.3 AST Software Requirements  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  77
2.4 AST Registers  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  78
3 General Purpose Direct Memory Access (DMA) Engines  . . . . . . . . . . . . . . . . . . . . . . .  105
3.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  105
3.2 Functional Description  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  108
3.3 Programming Guidelines  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  110
3.4 GPC-DMA Registers  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  115
4 System Memory Management Unit (SMMU)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  435
4.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  435
Boot and Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  438

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1 Boot and Power Management Processor (BPMP)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  438
1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  438
CPU Complex (CCPLEX)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  439
1 CCPLEX Overview  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  440
1.1 High-Level Multi-Core Block Diagram  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  440
1.2 Architectural Compliance  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  442
1.3 GICv2  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  442
1.4 High-Level Description of Micro-coded Implementation  . . . . . . . . . . . . . . . . . . . . . . . . . . .  442
1.5 High-Level Description of Power Management  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  442
1.6 Cache Flushes and Multi-processor Coherence  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  443
2 CCPLEX Functional Description  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  443
2.1 Top-Level Functional Diagram  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  443
2.2 Xavier Processor Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  445
3 CCPLEX Programming Guidelines  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  448
3.1 ARMv8 Architecture Concepts  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  448
3.2 Former ThumbEE Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  448
3.3 Jazelle Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  449
3.4 Memory Model  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  449
3.5 Optimizing CPU Workloads  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  449
4 System Control  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  461
4.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  461
5 Memory Management Unit  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  518
5.1 About the MMU and Address Translation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  518
5.2 Address Translation Hierarchy  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  519
5.3 Unsupported Exclusives Fault  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  521
6 L1 Memory System  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  521
6.1 About the L1 Memory System  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  521
6.2 Cache Organization  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  521
6.3 Support for and Behavior of ARMv8 Memory Types  . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  522
6.4 L1 Instruction Memory System  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  522
6.5 L1 Data Memory System  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  524
7 L2 Memory System  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  528

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7.1 Organization  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  528
7.2 Outstanding Request Tracker . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  529
7.3 Inclusion  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  529
7.4 Enabling/Disabling  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  529
7.5 Prefetching  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  530
7.6 Behavior of Different Memory Types  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  530
7.7 Cache Flushing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  531
8 System Coherence Fabric (SCF) and L3  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  531
8.1 Interconnect  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  531
8.2 Probe Filter  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  531
8.3 L3 Cache  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  532
8.4 Performance Monitoring  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  532
8.5 Cache Flush State Machines  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  532
9 Floating Point and Advanced SIMD  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  532
9.1 About Floating-Point and Advanced SIMD  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  532
9.2 Identification of Floating-Point and Advanced SIMD  . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  533
9.3 Floating-Point and Advanced SIMD Control and Status Registers  . . . . . . . . . . . . . . . . . .  535
9.4 Performance Hints  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  535
10 vGIC Interrupt Controller  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  536
10.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  536
10.2 vGIC Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  537
11 Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  542
11.1 Topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  542
11.2 CPU Voltage Sensing Control  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  544
12 Performance Monitoring Unit (PMU)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  545
12.1 Carmel (PMU) Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  545
13 Debug Features  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  558
13.1 About Debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  559
13.2 Debug Register Interfaces  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  559
13.3 AArch64 Debug Register Summary  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  559
13.4 AArch64 Debug Register Descriptions  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  561
13.5 AArch32 Debug Register Summary  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  561
13.6 AArch32 Debug Register Descriptions  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  563
13.7 External Debug Register Summary  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  564

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13.8 External Debug Register Descriptions  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  566
13.9 Debug Events  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  568
14 Cross Trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  568
14.1 About the Cross Trigger  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  568
14.2 Trigger Inputs and Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  570
14.3 Cross Trigger Register Summary  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  571
14.4 External Register Access Permissions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  572
14.5 Cross Trigger Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  572
GPU  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  575
1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  575
1.1 Tensor Cores  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  575
1.2 Enhanced L1 Data Cache and Shared Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  576
1.3 Independent Thread Scheduling  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  576
Multimedia Complex  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  578
1 Host Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  578
1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  578
1.2 Functionality  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  582
1.3 Programming Guidelines  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  596
2 Camera Subsystem  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  617
2.1 MIPI Camera Serial Interface (CSI)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  617
2.2 Video Input (VI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  1108
3 Video Image Compositor (VIC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  1243
3.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  1243
3.2 VIC Programming Guidelines  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  1270
3.3 VIC Registers  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  1322
4 High Definition Audio (HDA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  1329
4.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  1329
4.2 Programming Guidelines  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  1331
4.3 HDA Registers  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  1332
4.4 HDA Registers (Continued)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  1352

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5 Display Controller  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  1365
5.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  1365
5.2 Functional Description   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  1370
5.3 Programming Guidelines  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  1411
5.4 Display Controller Registers  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  1451
6 Display Interface (DisplayIF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  2789
6.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  2789
6.2 Functionality  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  2793
6.3 Programming Guidelines  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  2798
6.4 Display Interface Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  2834
7 Consumer Electronics Control (CEC)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  3086
7.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  3086
7.2 Functional Description  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  3087
7.3 Programming Guidelines  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  3087
7.4 CEC Registers  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  3088
8 Audio Processing Engine (APE)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  3104
8.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  3104
8.2 Functional Descriptions  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  3109
8.3 Programming Guidelines  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  3132
8.4 APE Registers  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  3162
9 Always On Digital Microphone (AODMIC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  5549
9.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  5549
9.2 Functional Description  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  5551
9.3 Programming Guidelines  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  5553
9.4 AODMIC Registers  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  5554
10 Pixel Memory Formats  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  5565
10.1 Pixel Memory Formats Functional Description  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  5565
10.2 Pixel Memory Formats Programming Guidelines  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  5608
System Components  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  5611
1 Clock and Reset Controller (CAR)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  5611
1.1 Reset Controller  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  5611
1.2 Clock Controller  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  5612

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2 Interrupt Controllers  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  5613
2.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  5613
2.2 Functional Description  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  5616
2.3 Interrupt Registers  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  5658
2.4 Legacy Interrupt Controller (LIC) Registers  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  5663
3 Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  5903
3.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  5903
3.2 Functional Description  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  5907
3.3 TKE Module  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  5919
3.4 Programming Guidelines  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  5926
3.5 Timer Registers  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  5931
4 Multi-Purpose I/O Pins and Pin Multiplexing (PinMux)  . . . . . . . . . . . . . . . . . . . . . . . .  6026
4.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  6026
4.2 Functionality  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  6040
4.3 Programming Guidelines  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  6053
4.4 PinMux Registers  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  6061
5 Hardware Synchronization Primitives (HSP)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  6338
5.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  6338
5.2 Functional Description  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  6339
5.3 Programming Model  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  6347
5.4 HSP Programming Guidelines  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  6348
5.5 HSP Registers  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  6350
6 Design for Debugging (DFD)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  6359
6.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  6359
High-Speed I/O  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  6393
1 HSIO Controllers  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  6393
1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  6393
2 USB Complex . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  6398
2.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  6398
2.2 USB Functional Description  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  6400
2.3 USB Programming Guidelines  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  6404
2.4 USB PADCTL and AO Registers  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  6459

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2.5 XHCI Controller Configuration Registers  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  6508
2.6 XUSB DEV Registers  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  6618
2.7 USB 3.0 Device Controller Memory-Mapped I/O Registers  . . . . . . . . . . . . . . . . . . . . . . .  6633
2.8 XHCI Controller Memory-Mapped I/O Registers  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  6680
3 SATA Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  6711
3.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  6711
3.2 SATA Functional Description  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  6713
3.3 SATA Programming Guidelines  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  6724
3.4 SATA Registers  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  6729
3.5 SATA AUX Registers  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  6751
3.6 SATA Miscellaneous Registers  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  6758
3.7 SATA AHCI Registers  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  6855
4 PCI Express (PCIe) Controller  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  6903
4.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  6903
4.2 Programming Guidelines  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  6910
4.3 PCIe Registers  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  6935
Low-Speed I/O  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  7842
1 SDMMC Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  7842
1.1 SDMMC Controller Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  7842
1.2 SDMMC Programming Guidelines  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  7855
1.3 SDMMCA Registers  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  7882
1.4 SDMMC Registers  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  7949
1.5 SDMMCAB Registers  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  8014
2 I2C Controller (I2C)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  8100
2.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  8100
2.2 Functional Description  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  8101
2.3 Software Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  8108
2.4 I2C Programming Guidelines  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  8112
2.5 I2C Registers  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  8151
3 Universal Asynchronous Receiver/Transmitter (UART)  . . . . . . . . . . . . . . . . . . . . . . .  8175
3.1 Functional Description  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  8175
3.2 Programming Guidelines  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  8179
3.3 UART Pad and Pinmux Information  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  8193

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3.4 UART Registers  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  8196
4 Serial Peripheral Interface (SPI)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  8206
4.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  8206
4.2 Functionality  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  8208
4.3 Programming Guidelines  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  8222
4.4 SPI Registers  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  8227
5 Quad Serial Peripheral Interface (QSPI)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  8242
5.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  8242
5.2 Functionality  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  8244
5.3 Programming Guidelines  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  8254
5.4 QSPI Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  8262
6 Pulse Width Modulator (PWM)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  8277
6.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  8277
6.2 Programming Guidelines  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  8279
6.3 PWM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  8280
7 Fan Tachometer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  8281
7.1 Fan Tachometer Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  8282
7.2 Fan Tachometer Programming Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  8286
7.3 Fan Tachometer Registers  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  8286

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1 Revision History

Version Date Description

1.0 November 20, 2018 Initial Release

1.1 December 10, 2018

Added:

CPU Complex (CCPLEX) - vGIC Interrupt Controller

Updated:

General Purpose DMA - Registers

SATA Controller - Registers

CPU Complex (CCPLEX) - System Control (NVGINDEX)

Audio Processing Engine (APE) - Programming Guidelines

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2 Introduction

This Technical Reference Manual (TRM) describes how the NVIDIA Xavier series system-on-chip (SoC)

functions; and is a guide for writing, understanding or modifying code that controls those functions. It contains

functional descriptions of how the Xavier hardware works, and also describes the registers and related

programming interfaces

Not all the units in Xavier are described in detail here; as some, like the GPU, are only intended to be used with

NVIDIA supplied drivers.

This document may describe hardware / software features and functionality not currently supported on

specific Xavier product SKUs, or features not supported by NVIDIA software. Refer to the appropriate

Xavier product data sheet as this is the primary authority for supported features and functionality of a

particular product SKU. Description of a hardware capability in this document does not imply software

support for that function. Refer to the appropriate BSP or software release notes for detailed

information about currently supported software functionality.

Xavier delivers a powerful solution designed to optimize performance and efficiency. Major features include:

Graphics: an NVIDIA Volta architecture GPU. The Volta GPU architecture supports the latest graphics and compute

capabilities with up to 512 CUDA cores. The GPU supports the same feature set as discrete NVIDIA GPUs, including

extensive compute APIs and libraries for CUDA and more.

CPU Complex: eight NVIDIA Carmel CPU cores in a coherent multi-processor configuration. The Carmel cores

support the ARM Architecture version 8.2, executing both 64-bit AArch64 code, and 32-bit AArch32 code. The Carmel

processors are organized as four dual-core clusters, where each cluster has a dedicated 2 MiB Level-2 unified cache.

A high speed coherency fabric connects these processor complexes and allows heterogeneous multi-processing with

all eight cores if required.

Level 3 cache: a 4 MiB Level-3 cache is available to both the CPU and GPU.

Computer Vision Acceleration: multiple dedicated engines including up to two Programmable Vision Accelerators

(PVA), a Stereo Optical Flow Engine (SOFE), and up to two dedicated Deep Learning Accelerators (DLA) are

available to complement the GPU and off-load some tasks from it.

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A set of embedded processors:

Audio Processing Engine (APE): a dedicated ARM Cortex-A9 with NEON, used as a digital signal processor

(DSP) with dedicated RAM. The related audio subsystem enables full hardware support for multi-channel audio

over multiple interfaces, and dedicated audio DMA, routing, mixing, and processing hardware.

Always-On Sensor Processing Engine (AON/SPE): a dedicated ARM Cortex-R5F subsystem. This is a low-

power processor in an Always-On power domain.

Boot and Power Management Processor (BPMP): a dedicated ARM Cortex-R5F subsystem to handle boot and

power management functions and related security enforcement.

Safety Cluster Engine (SCE): a dedicated ARM Cortex-R5F subsystem to handle safety management.

Real-time Camera Engine (RCE): a dedicated ARM Cortex-R5F subsystem to handle real-time camera

management.

Memory Controller: a 256 or 128-bit DRAM interface providing high bandwidth LPDDR4x support.

Video Decoder: a pair of advanced video decoders supporting up to dual 30 fps playback of 8K video, or multiple

streams at lower resolutions, with up to 12-bit pixels. These support H.265, H.264, VP9, VP8, MPEG-2, and MPEG-4

video standards.

Video Encoder: a pair of advanced video encoders supporting up to dual 60 fps capture of 4K video. These support H.

265, H.264 BP/MP/HP/MVC, and VP9 encoding.

Imaging: a high-quality hardware accelerated still-image and video capture path, with advanced ISP.

Display: a unified display controller supporting four heads, and up to six surfaces which can be assigned to any head.

Output is through four multi-mode outputs switchable between eDP/DP 1.4 and HDMI 2.0. Multiple line pixel storage

allows more memory-efficient scaling operations and pixel fetching.

In addition to these elements, Xavier has a broad range of peripheral interfaces to enable communication with

peripherals, audio codecs, power management, and other devices. Dedicated high-performance mass storage

controllers, with their own DMA engines, free the CPU Complex from routine data management tasks.

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Figure 2.1 Xavier Processor Block Diagram

2.1 Reading Register Tables

Every register table has an address line followed by a table containing the bit descriptions for that register. The

address line contains:

Offset: the address of the register within the specific module. Refer to the system memory map for the start address

of the module, and apply the offset at the top of the table to get the register address.

Read/Write: the register access type. When a register table contains the R/W column, individual bits within the

property. Values are RO (read only), R/W (read/write), WO (write only, and RWC (read/write clear).

Parity Protection: per register Parity diagnostic in hardware implemented by safety critical IPs. The Parity Diagnostic

detects random faults in the register fields.

‘Y’ indicates the field is continuously checked by the Parity Diagnostic of the register. Single bit flips in the register,

when not intended, is reported as a fault.

‘N’ indicates the field is not checked by the Parity Diagnostic of the register.

If all fields of the register have Parity Protection Column as 'N', the register does not implement any hardware based

Parity Diagnostic.

Reset: gives the power-on reset value in 32-bit binary. A value of x implies that the register bit has an undefined

value at reset. A hexadecimal value is listed for convenience, where appropriate.

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Default: only displayed if the default setting is different from the Reset value.

Unspecified bits may not appear in tables (see example below). Unspecified bits should be written with their

Reset values, while reads return an unknown value.

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2.2 Units

This TRM follows the IEEE and NIST conventions for multiplying prefixes.

Among other things, this convention uses an 'i' to indicate the binary convention, and its absence to indicate

decimal. So, 1 KiB is 2 or 1,024 bytes, and 1 KB is 10 or 1,000 bytes. Similarly it uses:

10 3

Mi for 2 and M for 10

20 6

Gi for 2 and G for 10

30 9

Ti for 2 and T for 10

40 12

2.3 Glossary

This glossary is intended to cover the acronyms used in this document; along with some others related to the

ARM SoC world. Many other acronyms in this document are in broad engineering use and are not documented

here.

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Term Definition

32K or 32k 32,768 Hz oscillator clock. Any references to 32k, 32 kHz, 32 KHz or 32K in the context of this clock should

always be interpreted as referring to a frequency of 32,768 Hz.

444/422/420 Pixel storage formats, 444 refers to formats where there are equal amounts of information for all three elements,

422 and 420 refer to formats where the color difference information is stored at half-resolution in either one

direction or both.

ADAS Advanced Driving Assistance System

ADSP Audio DSP, referring to the Cortex-A9 processor in the APE.

ADX Audio Demultiplexer Block, part of the Audio Hub used to demultiplex multiple audio streams.

AMBA Advanced Microcontroller Bus Architecture, a set of standard buses defined by ARM.

AMX Audio Multiplexer Block, part of the Audio Hub used to multiplex multiple audio streams together.

AO or AON Always-On power domain. This part of the chip is always powered on, even in the deepest sleep state, except

complete processor shutdown. See also SPE.

AON I/O rails I/Os in VDDIO_SYS, VDDIO_AO, and VDDIO_AO_HV serving the AON cluster logic

AONPG Always-On Non-Power Gated. Used to indicate when an AO partition has no power gating implemented.

AOPG Always-On Power Gated. Used to indicate when an AO partition has power gating implemented.

AOPM Always-On Cluster Power Management Module. PM module implements/manages the Cortex-R5 Power State

transitions. AOPM manages the SPE Cortex-R5 and its subsystem power states transitions.

AOTAG Always-On Thermal Alarm Generator

AOVC Always-On Voltage Controller

AP Applications Processor, refers to the Xavier device. Means the same as SoC.

APB AMBA Peripheral Bus, an ARM defined simple 32-bit single master bus for peripheral devices.

APE Audio Processing Engine

Aperture A named region of address space

APS Auxiliary processor subsystem. Refers to an implementation boundary that is shared across Cortex-R5 clusters

on the chip

ARM ARM is a company provides the CPU architectural specification for Xavier.

ARM is also Architecture Reference Manual, as in (the second ARM of) ARM ARM which defines the CPU

architecture.

AST Address Space Translator. A sub-unit associated with some of the embedded ARM cores that does address

translation from local addresses to system addresses along with appending some AXI attributes.

AXI AMBA Advanced eXtensible Interface, a more advanced bus than AHB defined as part of AMBA 3 by ARM.

AVIC ARM PL192 Vectored Interrupt Controller, used as the Cortex-R5 interrupt controller for all the Cortex-R5

processors (SPE, SCE, and BPMP).

Bayer A type of image sampling pattern invented by Dr. Bryce E. Bayer of Eastman Kodak. The pattern consists of

quads of pixels with two green samples, one red sample, and one blue sample:

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Term Definition

BCT Boot Configuration Table. Stored on external boot device, contains config parameters for boot decisions

BIT Boot information Table. Maintained internally by Boot ROM in RAM for boot path/error tracking and logging

BKV Best Known Value. Configurations determined by system characterization

BOM Bottom of Memory, refers to the lowest address in an address map.

BPMP Boot and Power Management Processor, see the corresponding chapter.

BPMP-FW BPMP Firmware – This refers to the power management firmware that would be executed on BPMP (post-boot).

This is also stored in external boot media

BR Boot ROM (Power-on start boot code. Stored/burnt in chip IROM, executes from BPMP)

Brick I/O interface block with analog and other special functions

CAR Clock and Reset module, which controls clocks and resets to the various parts of Xavier.

Carmel NVIDIA proprietary CPU core that is ARMv8 compatible. This is used in the Xavier CCPLEX.

CBB Control Backbone

CCPLEX CPU complex – i.e., CPU subsystem

CDE Color Decompression Engine

CEC Consumer Electronics Control, a part of the HDMI interface specification used for sending device control

commands, often from a remote control.

CID Client ID

CIL Control and Interface Logic

Cold boot The SoC partition power transitions from OFF to ON with no previous state available. Software must construct all

states from scratch. Boot ROM is executed. DRAM is brought on-line.

CoT Chain-of-trust – a security term used to denote any code that is trusted because it is loaded securely from the root

of trust (Boot ROM)

CP Color Parser

C-PHY A MIPI standard physical layer that can carry CSI data; clocks are transmitted along with data. Data lanes are

three wires.

CPU Unless specified otherwise, CPU generally refers to the main Carmel CPUs

CRC Cyclic Redundancy Check

CSI MIPI Camera Serial Interface, a standard high-speed serial interface for connecting cameras to Xavier.

CUDA Compute Unified Device Architecture

CVC Central Voltage Controller

CV Cluster Computer Vision Cluster. A partition in Xavier which has NVDLA, PVA, and CVNAS.

CVNAS Computer Vision NoC and SRAM

CVNOC A sub-block within CVNAS–the NoC portion of CVNAS.

CVSRAM A sub-block within CVNAS–the memory storage portion of CVNAS.

CZ Controlled-output impedance MPIO pads.

DBC Dead Battery Charging

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Term Definition

DBP Dead Battery Provisions

DBB Data Back-Bone

DCO Dynamic Code Optimization, a technique used by the Carmel CPU cores in Xavier to optimize the performance of

frequently executed ARM instructions. Refer to the CPU Complex chapter for more details.

DDA Digital Differential Analyzer, a technique commonly used in graphics for interpolation of variables over an interval

between start and end point, and also applied to other problems.

DDIC Display Driver IC

DFD Design for Debug

DFS Dynamic Frequency Scaling

DFT Design for Test

dGPU or DGPU Discrete GPU. Refers to an attached GPU which is external to the Xavier SoC, as opposed to the internal GPU.

DLA Deep Learning Accelerator

DLS Delayed Lock-Step

DMIC Digital microphone interface, supporting direct attach of PDM microphones.

DPD Deep Power Down. A mode in which the pad can tolerate VDD_CORE being turned off.

D-PHY A MIPI standard physical layer that can carry CSI data; clocks are transmitted separately from data. Data lanes

are two wires and clock lanes are two wires.

DRCM Debug Recovery Mode (also known as RCM-exit-to-JTAG)

DSI MIPI Display Serial Interface, a standard high-speed serial interface for connecting displays to Xavier.

DVC Dynamic Voltage Controller module

DVFS Dynamic Voltage and Frequency Scaling

EAVB Ethernet audio video bridging, and extension of the Ethernet standard supporting real-time streaming. More

recently referred to as Time-Sensitive Networking.

ECC Error Correction Code

eDP Embedded DisplayPort™

EMC External Memory Controller, a module that interfaces with external DDR/LPDDR devices.

EOF End of Frame. Refers to the last non-cropped long packet in a frame, or to an ISP EOF packet.

EVP Exception Vector Pointer

FA Failure Analysis

FCM Full Custom Macro

FE Frame End. Refers to the NVCSI short packet.

FIQ Fast Interrupt Request

FMEA Failure Mode and Effects Analysis

FMON Frequency Monitoring logic

FS Frame Start. Refers to the NVCSI short packet.

FSM

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Term Definition

Finite State Machine, this is a hardware engineering phrase used to describe a hardware block that controls the

operation of some logic function.

GIC Generic interrupt controller, normally used to describe an ARM supplied interrupt controller used for a specific set

of processors.

GPIO General Purpose Input/Output, an I/O signal uncommitted to a specific role and controlled by software.

HDMI High-Definition Multimedia Interface, a digital connection carrying video and audio at high speed over a single

connector.

HDR High Dynamic Range, usually a reference to cameras or displays using a higher dynamic range for pixel values.

HSIO High-Speed I/O Interfaces. See the corresponding chapter of this TRM for more details.

HSM Hardware Safety Module/Manager

HVC Hardware Vmin Control: The hardware initiated flow to enter/exit the Vmin state on VDD_CPU. Now referred to as

CC3.

iGPU or IGPU Internal GPU, refers to the GPU module within the Xavier SoC, as opposed to a possible external one.

IRAM Internal RAM used by the boot process until DRAM is configured (now deprecated, and replaced by TCMs and

SysRAM)

IROM Internal chip ROM which contains the Boot ROM code and data

IPI Inter-Processor Interrupt

IPT Inverse Perspective Transform

IRQ Interrupt Request

ISP Image Signal Processor, a hardware engine that is part of the camera processing pipeline.

KMD Kernel mode driver

LDC Lens Distortion Correction

LIC "Legacy" interrupt controller, a central interrupt controller in Xavier.

LP1 Low Power 1 state. Devices are power-gated, SoC clock domains are set to the minimum frequency (12 MHz and

38.4 MHz), the flow controller is configured to monitor "LP1 exit wake events," DRAM is put in self-refresh, and

the VDD_CPU rail is powered off. Also known as the Suspend state.

LV Low-voltage MPIO pads

MB1 and MB2 MicroBoot stages 1 and 2, stored on external boot media. Refer to the Boot chapter for more details.

MC Memory Controller module handles requests from internal clients and arbitrates among them to allocate memory

bandwidth. Also referred to as MSS.

MCCIF or MC-CIF Memory Controller Client InterFace, the standard interface block between the memory controller subsystem fabric

and the client device. Note that some modules may have multiple client interfaces.

MDMM Multi-drop multi-merge

MIPI The Mobile Industry Processor Interface, an industry alliance promoting a number of standard interfaces for

mobile devices.

MMIO Memory-Mapped I/O (transactions)

MODS

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Term Definition

Modular Diagnostic Software. It is a powerful software program that allows users to test the NVIDIA hardware.

MODS is used for three primary purposes--chip and board functional validation, chip and board failure analysis

and debug, and architectural verification.

MPCORE Multi-processor CPU core, a generic term for a CPU capable of operating as part of an SMP group.

M-PHY or MPHY MIPI M-PHY, an embedded-clock serial-interface technology with high bandwidth capabilities.

MPIO Multi-purpose I/O

MSI Message Signaled Interrupt

MSS Memory Sub-System. Refer to the corresponding chapter.

MTS An alternate name for the Carmel CPU Microcode generated by Dynamic Code Optimization.

NVDEC NVIDIA Video Decoder engine.

NVENC NVIDIA Video Encoder engine.

NVJPG NVIDIA JPEG engine.

NVM Non-Volatile memory – data retained even after power is turned off. All boot media have non-volatile memory

storage.

OD Open Drain MPIO pads

OGL Open Graphics Library, also known as OpenGL. An API supported on Xavier and accelerated in hardware by

dedicated 3D and 2D engines.

PA Physical Address

Partition A physical sub-region of the Xavier device. Power gating is usually applied at the partition level.

PMIC Power Management Integrated Control (synonymous with PMU)

PCIe Peripheral Component Interconnect Express, a high-speed interface for external devices connected to Xavier.

PMC Power Management Controller module controls the various power management features in the system.

PMIC Power management IC. Off-die module that controls various voltage regulators, provides the 32 kHz (32.768 kHz)

clock source and provides the main system reset to the SoC.

POR Power On Reset

PPC Pixels Per Clock

PPI Private Peripheral Interrupt within an ARM processor core

PWFM Pulse Width Frequency Modulation module generates programmed pulse widths typically used to control

backlight in display panels.

PVA Programmable Vision Accelerator is a custom computer vision DSP, Xavier has two of them.

PVT Process, Voltage, and Temperature

R5 Cortex-R5 is a mid-range ARMv7 CPU cluster used for multiple engines in Xavier.

RAZ Read As Zero

RCE Real-time Camera-control Engine, see the corresponding chapter .

RCM Recovery Mode, used for re-flashing the external boot device image.

RGB

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Term Definition

Name given to pixels with red, green, and blue color components. This is the pixel format typically found in most

display technologies because each color component corresponds to the colors of the filters or phosphors used in

the display device.

RISC Reduced Instruction Set Computer, the CPU architecture used by ARM CPUs.

RMMI Reference M-PHY Module Interface

R/O Read only

R/W Read write

SATA Serial Advanced Technology Attachment (ATA)

SC7 Low power 0 state in which DRAM is put in self-refresh. The system state is saved in the PMC and in DRAM.

VDD_CORE and VDD_CPU rails are powered off, and PMC is configured to monitor "LP0 wake events" that

trigger LP0 exit. Also known as Deep-Sleep state.

SCE Safety Cluster Engine, see the corresponding chapter.

SCF System Coherency Fabric

SCR Security Control Register. Refer to the Control Fabric chapter for details of how these are programmed.

SE Security Engine, used for hardware acceleration of authentication and decryption steps.

SGI Software Generated Interrupt

SDMMC SD and MMC controller. An I/O controller supporting both the SD/SDIO interface standards and the eMMC

standard.

SFIO Special Function I/O

SLCG Second Level Clock Gating, a hardware technique to reduce power.

SLINK Serial Link, a legacy and now obsolete name for the SPI controller.

SMMU System Memory Management Unit, a block within the memory controller used to map from a virtual address

space to physical addresses for device DMA.

SMP Symmetric Multi-Processing

SNIC System Network InterConnect, used to refer to the control fabric in Xavier, and explained in the Control Fabric

chapter of this TRM.

SoC System on a Chip, an integrated circuit containing a CPU, memory controller and the peripheral devices needed

for a computing system.

SOF Start of Frame. Used to refer to the first non-cropped long packet in a frame, or to an ISP SOF packet.

SOR Serial Output Resource. SOR is GPU IP for driving HDMI/DP/LVDS. It converts the output of the display to a

more modern high-speed serial protocol. DSI is not included since it's not GPU IP based.

S/PDIF Sony/Philips Digital Interconnect Format

SPE Sensor Processing Engine, which has other uses, see the Always-On Cluster chapter.

SPI Serial Peripheral Interface Bus, a synchronous serial data link, that operates in full-duplex mode.

SPI A Shared Peripheral Interrupt within an ARM core

ST Standard MPIO pads

Sub-aperture

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Term Definition

An aperture whose address space is a subset of another aperture and whose accessibility is also a subset of

another aperture.

SysRAM Name for the shared on-chip memory

TBSA Trusted Base System Architecture – an ARM specification

TCM Tightly Coupled Memory – this refers to internal local RAM that is associated with some of the ARM CPU Cores.

These are used as local, low-latency scratch pad memory.

Tegra The name formerly used to describe the NVIDIA family of SoCs, and now used only in certain applications.

References to Tegra that still exist in this TRM, such as Tegra Host or Tegra pixel formats, may be considered to

apply to all the NVIDIA family of SoCs, up to and including Xavier.

THI Host Interface

TOS Trusted OS

TSOSC Ring oscillator based thermal sensors

TOM Top of Memory, refers to the highest address in an address map.

TNR Temporal Noise Reduction

TSC Time Stamp Counter

TSEC Security co-processor, an embedded security processor used mainly to manage the HDCP encryption and keys

on the HDMI link.

TrustZone is a secure operating environment of the ARM CPU architecture and the related secure parts of the

SoC backbone and devices.

TZRAM TrustZone secured RAM on the SoC.

UFS Universal Flash Storage

UFSHC UFS Host Controller

Uncore The CPU related logic outside of the CPU processing core itself.

UniPro MIPI Unified Protocol, a link layer communication protocol.

U-PHY or UPHY Universal PHY, and NVIDIA reference to a multi-mode Serializer-Deserializer (SerDes) with analog pads for high-

speed signaling to support various protocols.

VA Virtual address

VDD_CORE SoC power rail

VDD_CPU CPU power rail

VDD_RTC Always-On power rail

vGPIO Virtual General-Purpose Input/Output

VI Video Input block, the acronym used to describe the Xavier block used for camera and related pixel input

functions.

VIC (a) Video Image Compositor, a Xavier block that implements video post-processing functions needed by a video

playback application to produce the final image for the player window.

(b) The ARM name for the PL192 Vectored Interrupt Controller used alongside the Cortex-R5 cores. Also referred

to here as AVIC to avoid a name-space conflict with the previous entry.

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Term Definition

VM Virtual machine

VPR Video Protect Region

Warm boot Exit from SC7 state

WDT Watchdog Timer. These timers can generate interrupts or resets to attempt to break the AP out of undesirable

states.

WFE Wait For Event (an ARM instruction)

WFI Wait For Interrupt (an ARM instruction)

WID Write ID (from the AXI specification)

W1C Write as 1 to Clear

xHCI eXtensible Host Controller Interface for USB

XIP eXecute In Place. Debug-only scheme where the primary IROM code is bypassed, and external code is fetched

instead at reset, to test out Boot ROM code. This code is executed in-place from the external device, i.e.,

executed per instruction without fetching the entire code chunk.

YCbCr An alternative pixel representation that can take advantage of the properties of the human psycho-perceptual

vision system and store the color difference information with lower spatial resolution. It consists of a luminance

channel Y and two color difference signals Cb and Cr. See the definition of 444/422/420.

YUV See YCbCr. U and V are equivalent to Cb and Cr, respectively.

ZSL Zero Shutter Lag

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3 Memory Architecture and Memory Mapped I/O

3.1 Address Map

3.1.1 Overview

This chapter defines the NVIDIA Xavier series system-on-chip (SoC) system Address Map (AMAP).

The term “Address” reflects the “Physical Address” as seen by the main CPU complex, unless specified

otherwise. The Xavier Series SoC has several subsystems such as the BPMP, SPE, Audio, etc. The processors

in these subsystems may have a different view of the System AMAP. The AMAP specifications for these

subsystems are explained in more detail in the corresponding subsystem section of this document.

The term AMAP implies System Address Map or Global Address Map (with the terms System Address Map and

Global Address Map being used interchangeably), unless otherwise specified.

Features

64 KiB Alignment

ARM Architecture recommends aligning all peripheral address ranges along the MMU page sizes. This

enables each device to occupy a single entry in the Page Table and makes it possible to uniquely identify

and describe device access attributes. The page can be uniquely classified under a non-normal memory

type such as nGnRnE (for SO) or nGnRE (for DEV). Refer to the ARMv8 Architecture Reference Manuals

for more information. Page-alignment of peripherals also improves security across virtualized guest

Operating Systems. ARMv8 supports three types of page sizes in its MMU – 4 KiB, 16 KiB, and 64 KiB.

By aligning with 64 KiB, all three implementations are supported and sufficient MMIO for each device is

allocated.

40-bit Address Map

Xavier supports a one Terabyte AMAP (1 TiB or 40 bits of addressing).

PCIe Aperture

Xavier offers two apertures for PCIe: one for a 32-bit address OS and the other for a greater-than 32-bit

address OS. Each PCIe controller is provided with a 32 MiB aperture. The PCIe aperture for greater-than

32-bit address OS handles situations with large AMAP requirements, which cannot be addressed by

drivers running on a 32-bit address OS.

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3.1.2 AMAP and Aperture

Xavier supports a 1-Terabyte AMAP (40 bits). See below for a high-level overview of the AMAP.

AMAP Overview

Name Address Range

Reserved (1023 GiB - 1024 GiB) 0xFF_C000_0000 - 0xFF_FFFF_FFFF

Off-Chip Aperture (128 GiB - 1023 GiB) 0x20_0000_0000 - 0xFF_BFFF_FFFF

PCIe Aperture for > 32-bit OS (72 GiB - 128 GiB)

(1)

0x12_0000_0000 - 0x1F_FFFF_FFFF

Reserved (66 GiB - 72 GiB) 0x10_8000_0000 - 0x11_FFFF_FFFF

DRAM Aperture (2 GiB - 66 GiB) 0x00_8000_0000 - 0x10_7FFF_FFFF

On-Chip Data/Sync Plane (1 GiB - 2 GiB) 0x00_4000_0000 - 0x00_7FFF_FFFF

PCIe Aperture for 32-bit OS (0.75 GiB - 1 GiB) 0x00_3000_0000 - 0x00_3FFF_FFFF

MMIO Aperture (0 GiB - 1 GiB) 0x00_0000_0000 - 0x00_3FFF_FFFF

The control plane extends beyond 4 GiB for PCIe controllers controlled by > 32-bit OS.

Figure 3.1 Xavier AMAP Diagram

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MMIO Aperture

The MMIO aperture begins at the bottom of memory (0x0) and extends to 1 GiB.

Figure 3.2 MMIO Aperture

This region houses the following apertures:

Configuration register apertures of all IPs of the SoC

144 MiB iGPU aperture

PCIe aperture for 32-bit OS in its top 256 MiB. This is used for configuration, MMIO, IOIO space and is accessible by

32-bit OS.

(Note: the APE only decodes apertures below 0.75 GiB to the control backbone, soit cannot access PCIe. Since the

High Definition Audio (HDA) controller sits under the 0.75 GiB range, there is no need for APE to ever access any

PCIe controller.)

Each PCIe controller is provided with a 32 MiB aperture.

PCIe APB configuration space is disjoint from this space and can live anywhere outside this range

On-Chip Data/Sync Plane Aperture

The following figure shows the On-Chip Data/Sync Plane aperture.

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Figure 3.3 On-Chip Data/Sync Plane Aperture

This region houses the following:

The SysRAM region starting at 1 GiB. A 256 MiB region is reserved, although physical SysRAM Size is 416 KiB. 256

MiB allows for a higher steering granularity at the System Coherency Fabric (SCF) in the CCPLEX. All CPUs access

SysRAM at this physical location, without the need of any translation.

The 4 MiB Compute Vision SRAM (CV-SRAM), used by Programmable Vision Accelerators (PVAs) and Deep

Learning Accelerators. A 256 MiB region is reserved for this similarly to SysRAM.

The dGPU Host Controller Sync Point aperture. This is a 4 MiB Sync Point Region that is used to convert the dGPU

semaphores into Host Controller sync points. Note that this region can also be used by any non Host Controller

clients. This region shadows the Syncpoint RAM in Host Controller using a sideband interface between Host

Controller and Memory. Previously the GPU needed a sideband interface into the Host Controller Syncpoint to talk to

any other Host Controller client. With this syncpoint region, the sideband with Host Controller is removed from the

GPU.

Reserved region beyond the dGPU Syncpoint aperture.

DRAM Aperture

The DRAM aperture is used for the Physical Address of the off-chip local DRAM. The AMAP supports up to 64

GiB of DRAM. A 32-bit OS can access the lower 2 GiB Physical DRAM location (AMAP region from 2 GiB to 4

GiB). In order to access DRAM above 4 GiB in the AMAP, a 32-bit OS must use an additional address

translation capability like AST or the SMMU).

PCIe Aperture (32-bit OS)

Xavier has two apertures for PCIe: one for 32-bit OS (a sub-aperture within the MMIO aperture above) and the

other for a 64-bit OS (see figure below).

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Figure 3.4 PCIe Aperture (32-bit OS)

The PCIe aperture for a 64-bit OS handles situations with large AMAP requirements. When a PCIe controller is

connected to a device which has multiple functions, where each function can in turn be a switch, as shown in

below figure, it presents large AMAP requirements. Such large AMAP requirements cannot be met under 4 GiB

and hence cannot be addressed by drivers running on 32 bit CPUs.

Figure 3.5 PCIe Controller Connection Example

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Xavier platforms can present a similar large AMAP requirement. PCIe x8/x4 controllers are used to connect

Xavier devices to dGPUs or NVSwitch. Because there are two PCIe x4 controllers and one PCIe x8 controller

where either of these could be used to connect to NVIDIA SoCs/NVSwitch/dGPUs, each PCIe x4/x8 controller

is allocated 16 GiB AMAP.

There are also three PCIe x1 controllers that present a 1 GiB per controller requirement. An 8 GiB space is

reserved for the PCIe x1 controllers to allow for future expansion.

Off-Chip Aperture

This configurable (BOM/TOM registers in SCF and MCF) aperture allows the AMAP to be adjusted to the

required platform. This region can be used to access

Peer DRAM Dual Xavier platforms.

dGPUs VIDMEM in Xavier with Discrete GPU platforms

Other dGPUs VIDMEMs and other DRAMs in Single/Multiple Xavier with Multiple GPUs platform

3.1.3 System Address Map

The locality column indicates if apertures are only accessible by some masters. For example:

SYSTEM - indicates access is possible from all Initiators unless the paths from a master to slave is not

physically present.

CCPLEX - indicates access is only possible from CCPLEX, the main CPU complex.

SYSTEM_CFG - same as SYSTEM. In addition, when an IP can exist in various modes, this indicates the

exact register bit that is used to decide the mode.

For example, the PCIe controller can exist as a Root Complex or as an End Point. And for each mode, the

header file is different.

Block Name Start Address End Address Address Locality

LOVEC 0x00000000 0x0000ffff CCPLEX

MISC 0x00100000 0x0010ffff SYSTEM

MC8 0x01700000 0x0170ffff SYSTEM

MC9 0x01710000 0x0171ffff SYSTEM

MC10 0x01720000 0x0172ffff SYSTEM

MC11 0x01730000 0x0173ffff SYSTEM

MC12 0x01740000 0x0174ffff SYSTEM

MC13 0x01750000 0x0175ffff SYSTEM

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Block Name Start Address End Address Address Locality

MC14 0x01760000 0x0176ffff SYSTEM

MC15 0x01770000 0x0177ffff SYSTEM

EMC8 0x01780000 0x0178ffff SYSTEM

EMC9 0x01790000 0x0179ffff SYSTEM

EMC10 0x017a0000 0x017affff SYSTEM

EMC11 0x017b0000 0x017bffff SYSTEM

EMC12 0x017c0000 0x017cffff SYSTEM

EMC13 0x017d0000 0x017dffff SYSTEM

EMC14 0x017e0000 0x017effff SYSTEM

EMC15 0x017f0000 0x017fffff SYSTEM

TSA_NODE_0 0x02000000 0x02000fff SYSTEM

TSA_NODE_1 0x02001000 0x02001fff SYSTEM

TSA_NODE_2 0x02002000 0x02002fff SYSTEM

TSA_NODE_3 0x02003000 0x02003fff SYSTEM

TSA_NODE_4 0x02004000 0x02004fff SYSTEM

TSA_NODE_5 0x02005000 0x02005fff SYSTEM

TSA_NODE_6 0x02006000 0x02006fff SYSTEM

TSA_NODE_7 0x02007000 0x02007fff SYSTEM

TSA_NODE_8 0x02008000 0x02008fff SYSTEM

TSA_NODE_9 0x02009000 0x02009fff SYSTEM

TSA_NODE_10 0x0200a000 0x0200afff SYSTEM

TSA_NODE_11 0x0200b000 0x0200bfff SYSTEM

TSA_NODE_12 0x0200c000 0x0200cfff SYSTEM

TSA_NODE_13 0x0200d000 0x0200dfff SYSTEM

TSA_NODE_14 0x0200e000 0x0200efff SYSTEM

TSA_NODE_15 0x0200f000 0x0200ffff SYSTEM

TSA_NODE_16 0x02010000 0x02010fff SYSTEM

TSA_NODE_17 0x02011000 0x02011fff SYSTEM

TSA_NODE_18 0x02012000 0x02012fff SYSTEM

TSA_NODE_19 0x02013000 0x02013fff SYSTEM

TSA_NODE_20 0x02014000 0x02014fff SYSTEM

TSA_NODE_21 0x02015000 0x02015fff SYSTEM

TSA_NODE_22 0x02016000 0x02016fff SYSTEM

TSA_NODE_23 0x02017000 0x02017fff SYSTEM

TSA_NODE_24 0x02018000 0x02018fff SYSTEM

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Block Name Start Address End Address Address Locality

TSA_NODE_25 0x02019000 0x02019fff SYSTEM

TSA_NODE_26 0x0201a000 0x0201afff SYSTEM

TSA_NODE_27 0x0201b000 0x0201bfff SYSTEM

TSA_NODE_28 0x0201c000 0x0201cfff SYSTEM

TSA_NODE_29 0x0201d000 0x0201dfff SYSTEM

TSA_NODE_30 0x0201e000 0x0201efff SYSTEM

TSA_NODE_31 0x0201f000 0x0201ffff SYSTEM

TSA_NODE_32 0x02020000 0x02020fff SYSTEM

TSA_NODE_33 0x02021000 0x02021fff SYSTEM

TSA_NODE_34 0x02022000 0x02022fff SYSTEM

TSA_NODE_35 0x02023000 0x02023fff SYSTEM

TSA_NODE_36 0x02024000 0x02024fff SYSTEM

TSA_NODE_37 0x02025000 0x02025fff SYSTEM

TSA_NODE_38 0x02026000 0x02026fff SYSTEM

TSA_NODE_39 0x02027000 0x02027fff SYSTEM

TSA_NODE_40 0x02028000 0x02028fff SYSTEM

TSA_NODE_41 0x02029000 0x02029fff SYSTEM

TSA_NODE_42 0x0202a000 0x0202afff SYSTEM

TSA_NODE_43 0x0202b000 0x0202bfff SYSTEM

TSA_NODE_44 0x0202c000 0x0202cfff SYSTEM

TSA_NODE_45 0x0202d000 0x0202dfff SYSTEM

TSA_NODE_46 0x0202e000 0x0202efff SYSTEM

TSA_NODE_47 0x0202f000 0x0202ffff SYSTEM

TSA_NODE_48 0x02030000 0x02030fff SYSTEM

TSA_NODE_49 0x02031000 0x02031fff SYSTEM

TSA_NODE_50 0x02032000 0x02032fff SYSTEM

TSA_NODE_51 0x02033000 0x02033fff SYSTEM

TSA_NODE_52 0x02034000 0x02034fff SYSTEM

TSA_NODE_53 0x02035000 0x02035fff SYSTEM

TSA_NODE_54 0x02036000 0x02036fff SYSTEM

TSA_NODE_55 0x02037000 0x02037fff SYSTEM

TSA_NODE_56 0x02038000 0x02038fff SYSTEM

TSA_NODE_57 0x02039000 0x02039fff SYSTEM

TSA_NODE_58 0x0203a000 0x0203afff SYSTEM

TSA_NODE_59 0x0203b000 0x0203bfff SYSTEM

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Block Name Start Address End Address Address Locality

TSA_NODE_60 0x0203c000 0x0203cfff SYSTEM

TSA_NODE_61 0x0203d000 0x0203dfff SYSTEM

TSA_NODE_62 0x0203e000 0x0203efff SYSTEM

TSA_NODE_63 0x0203f000 0x0203ffff SYSTEM

GPIO_CTL_COMMON_GPIO0 0x02200000 0x02200fff SYSTEM

GPIO_CTL_COMMON_GPIO1 0x02201000 0x02201fff SYSTEM

GPIO_CTL_COMMON_GPIO2 0x02202000 0x02202fff SYSTEM

GPIO_CTL_COMMON_GPIO3 0x02203000 0x02203fff SYSTEM

GPIO_CTL_COMMON_GPIO4 0x02204000 0x02204fff SYSTEM

GPIO_CTL_COMMON_GPIO5 0x02205000 0x02205fff SYSTEM

GPIO_CTL0_GPIO0 0x02210000 0x02210fff SYSTEM

GPIO_CTL0_GPIO1 0x02211000 0x02211fff SYSTEM

GPIO_CTL0_GPIO2 0x02212000 0x02212fff SYSTEM

GPIO_CTL0_GPIO3 0x02213000 0x02213fff SYSTEM

GPIO_CTL0_GPIO4 0x02214000 0x02214fff SYSTEM

GPIO_CTL0_GPIO5 0x02215000 0x02215fff SYSTEM

GPIO_CTL1_GPIO0 0x02220000 0x02220fff SYSTEM

GPIO_CTL1_GPIO1 0x02221000 0x02221fff SYSTEM

GPIO_CTL1_GPIO2 0x02222000 0x02222fff SYSTEM

GPIO_CTL1_GPIO3 0x02223000 0x02223fff SYSTEM

GPIO_CTL1_GPIO4 0x02224000 0x02224fff SYSTEM

GPIO_CTL1_GPIO5 0x02225000 0x02225fff SYSTEM

GPIO_CTL2_GPIO0 0x02230000 0x02230fff SYSTEM

GPIO_CTL2_GPIO1 0x02231000 0x02231fff SYSTEM

GPIO_CTL2_GPIO2 0x02232000 0x02232fff SYSTEM

GPIO_CTL2_GPIO3 0x02233000 0x02233fff SYSTEM

GPIO_CTL2_GPIO4 0x02234000 0x02234fff SYSTEM

GPIO_CTL2_GPIO5 0x02235000 0x02235fff SYSTEM

GPIO_CTL3_GPIO0 0x02240000 0x02240fff SYSTEM

GPIO_CTL3_GPIO1 0x02241000 0x02241fff SYSTEM

GPIO_CTL3_GPIO2 0x02242000 0x02242fff SYSTEM

GPIO_CTL3_GPIO3 0x02243000 0x02243fff SYSTEM

GPIO_CTL3_GPIO4 0x02244000 0x02244fff SYSTEM

GPIO_CTL3_GPIO5 0x02245000 0x02245fff SYSTEM

GPIO_CTL4_GPIO0 0x02250000 0x02250fff SYSTEM

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Block Name Start Address End Address Address Locality

GPIO_CTL4_GPIO1 0x02251000 0x02251fff SYSTEM

GPIO_CTL4_GPIO2 0x02252000 0x02252fff SYSTEM

GPIO_CTL4_GPIO3 0x02253000 0x02253fff SYSTEM

GPIO_CTL4_GPIO4 0x02254000 0x02254fff SYSTEM

GPIO_CTL4_GPIO5 0x02255000 0x02255fff SYSTEM

GPIO_CTL5_GPIO0 0x02260000 0x02260fff SYSTEM

GPIO_CTL5_GPIO1 0x02261000 0x02261fff SYSTEM

GPIO_CTL5_GPIO2 0x02262000 0x02262fff SYSTEM

GPIO_CTL5_GPIO3 0x02263000 0x02263fff SYSTEM

GPIO_CTL5_GPIO4 0x02264000 0x02264fff SYSTEM

GPIO_CTL5_GPIO5 0x02265000 0x02265fff SYSTEM

GPIO_CTL6_GPIO0 0x02270000 0x02270fff SYSTEM

GPIO_CTL6_GPIO1 0x02271000 0x02271fff SYSTEM

GPIO_CTL6_GPIO2 0x02272000 0x02272fff SYSTEM

GPIO_CTL6_GPIO3 0x02273000 0x02273fff SYSTEM

GPIO_CTL6_GPIO4 0x02274000 0x02274fff SYSTEM

GPIO_CTL6_GPIO5 0x02275000 0x02275fff SYSTEM

GPIO_CTL7_GPIO0 0x02280000 0x02280fff SYSTEM

GPIO_CTL7_GPIO1 0x02281000 0x02281fff SYSTEM

GPIO_CTL7_GPIO2 0x02282000 0x02282fff SYSTEM

GPIO_CTL7_GPIO3 0x02283000 0x02283fff SYSTEM

GPIO_CTL7_GPIO4 0x02284000 0x02284fff SYSTEM

GPIO_CTL7_GPIO5 0x02285000 0x02285fff SYSTEM

CBB_AXIS_CENTRAL_ERR_OBSERVE

0x02300000 0x0230ffff SYSTEM

CBB_AXIS_CENTRAL_FAULT_PWR 0x02310000 0x0231ffff SYSTEM

CBB_AXIS_CENTRAL_QOS 0x02320000 0x0232ffff SYSTEM

CBB_FIREWALL 0x02340000 0x0234ffff SYSTEM

CBB_AXIS_PCIE_1X5_FAULT_PWR 0x02350000 0x0235ffff SYSTEM

CBB_AXIS_SATELLITE_1X5_FAULT_P

0x02360000 0x0236ffff SYSTEM

CBB_AXIS_AXI2APB_1x2_FAULT_PW

0x02370000 0x0237ffff SYSTEM

CBB_AXIS_AON_1x2_FAULT_PWR 0x02380000 0x0238ffff SYSTEM

AXI2APB_1 0x02390000 0x0239ffff SYSTEM

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Block Name Start Address End Address Address Locality

AXI2APB_2 0x023a0000 0x023affff SYSTEM

AXI2APB_3 0x023b0000 0x023bffff SYSTEM

AXI2APB_4 0x023c0000 0x023cffff SYSTEM

AXI2APB_5 0x023d0000 0x023dffff SYSTEM

AXI2APB_6 0x023e0000 0x023effff SYSTEM

PADCTL_A0 0x02430000 0x02430fff SYSTEM

PADCTL_A1 0x02431000 0x02431fff SYSTEM

PADCTL_A2 0x02432000 0x02432fff SYSTEM

PADCTL_A4 0x02434000 0x02434fff SYSTEM

PADCTL_A5 0x02435000 0x02435fff SYSTEM

PADCTL_A6 0x02436000 0x02436fff SYSTEM

PADCTL_A7 0x02437000 0x02437fff SYSTEM

PADCTL_A8 0x02438000 0x02438fff SYSTEM

PADCTL_A10 0x0243a000 0x0243afff SYSTEM

PADCTL_A11 0x0243b000 0x0243bfff SYSTEM

PADCTL_A13 0x0243d000 0x0243dfff SYSTEM

PADCTL_A16 0x02440000 0x02440fff SYSTEM

PADCTL_A17 0x02441000 0x02441fff SYSTEM

PADCTL_A20 0x02444000 0x02444fff SYSTEM

PADCTL_A21 0x02445000 0x02445fff SYSTEM

PADCTL_A22 0x02446000 0x02446fff SYSTEM

UFSHC_0_MMIO 0x02450000 0x0245ffff SYSTEM

UFSHC_0_UNIPRO_AUX 0x02460000 0x02467fff SYSTEM

UFSHC_0_UNIPRO_FPGA 0x02468000 0x0246ffff SYSTEM

MPHY_L0 0x02470000 0x0247ffff SYSTEM

MPHY_L1 0x02480000 0x0248ffff SYSTEM

ETHER_QOS_0 0x02490000 0x0249ffff SYSTEM

ETHER_QOS_1 0x024a0000 0x024affff SYSTEM

ETHER_QOS_2 0x024b0000 0x024bffff SYSTEM

ETHER_QOS_3 0x024c0000 0x024cffff SYSTEM

ETHER_QOS_4 0x024d0000 0x024dffff SYSTEM

MISC_ERR_COLLATOR 0x024e0000 0x024effff SYSTEM

GPCDMA_COMMON_0 0x02600000 0x0260ffff SYSTEM

GPCDMA_CH0 0x02610000 0x0261ffff SYSTEM

GPCDMA_CH1 0x02620000 0x0262ffff SYSTEM

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Block Name Start Address End Address Address Locality

GPCDMA_CH2 0x02630000 0x0263ffff SYSTEM

GPCDMA_CH3 0x02640000 0x0264ffff SYSTEM

GPCDMA_CH4 0x02650000 0x0265ffff SYSTEM

GPCDMA_CH5 0x02660000 0x0266ffff SYSTEM

GPCDMA_CH6 0x02670000 0x0267ffff SYSTEM

GPCDMA_CH7 0x02680000 0x0268ffff SYSTEM

GPCDMA_CH8 0x02690000 0x0269ffff SYSTEM

GPCDMA_CH9 0x026a0000 0x026affff SYSTEM

GPCDMA_CH10 0x026b0000 0x026bffff SYSTEM

GPCDMA_CH11 0x026c0000 0x026cffff SYSTEM

GPCDMA_CH12 0x026d0000 0x026dffff SYSTEM

GPCDMA_CH13 0x026e0000 0x026effff SYSTEM

GPCDMA_CH14 0x026f0000 0x026fffff SYSTEM

GPCDMA_CH15 0x02700000 0x0270ffff SYSTEM

GPCDMA_CH16 0x02710000 0x0271ffff SYSTEM

GPCDMA_CH17 0x02720000 0x0272ffff SYSTEM

GPCDMA_CH18 0x02730000 0x0273ffff SYSTEM

GPCDMA_CH19 0x02740000 0x0274ffff SYSTEM

GPCDMA_CH20 0x02750000 0x0275ffff SYSTEM

GPCDMA_CH21 0x02760000 0x0276ffff SYSTEM

GPCDMA_CH22 0x02770000 0x0277ffff SYSTEM

GPCDMA_CH23 0x02780000 0x0278ffff SYSTEM

GPCDMA_CH24 0x02790000 0x0279ffff SYSTEM

GPCDMA_CH25 0x027a0000 0x027affff SYSTEM

GPCDMA_CH26 0x027b0000 0x027bffff SYSTEM

GPCDMA_CH27 0x027c0000 0x027cffff SYSTEM

GPCDMA_CH28 0x027d0000 0x027dffff SYSTEM

GPCDMA_CH29 0x027e0000 0x027effff SYSTEM

GPCDMA_CH30 0x027f0000 0x027fffff SYSTEM

GPCDMA_CH31 0x02800000 0x0280ffff SYSTEM

AXBAR 0x02900800 0x02900fff SYSTEM

I2S1 0x02901000 0x029010ff SYSTEM

I2S2 0x02901100 0x029011ff SYSTEM

I2S3 0x02901200 0x029012ff SYSTEM

I2S4 0x02901300 0x029013ff SYSTEM

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Block Name Start Address End Address Address Locality

I2S5 0x02901400 0x029014ff SYSTEM

I2S6 0x02901500 0x029015ff SYSTEM

SFC1 0x02902000 0x029021ff SYSTEM

SFC2 0x02902200 0x029023ff SYSTEM

SFC3 0x02902400 0x029025ff SYSTEM

SFC4 0x02902600 0x029027ff SYSTEM

AMX1 0x02903000 0x029030ff SYSTEM

AMX2 0x02903100 0x029031ff SYSTEM

AMX3 0x02903200 0x029032ff SYSTEM

AMX4 0x02903300 0x029033ff SYSTEM

ADX1 0x02903800 0x029038ff SYSTEM

ADX2 0x02903900 0x029039ff SYSTEM

ADX3 0x02903a00 0x02903aff SYSTEM

ADX4 0x02903b00 0x02903bff SYSTEM

DMIC1 0x02904000 0x029040ff SYSTEM

DMIC2 0x02904100 0x029041ff SYSTEM

DMIC3 0x02904200 0x029042ff SYSTEM

DMIC4 0x02904300 0x029043ff SYSTEM

DSPK1 0x02905000 0x029050ff SYSTEM

DSPK2 0x02905100 0x029051ff SYSTEM

SPDIF1 0x02906000 0x029061ff SYSTEM

AFC1 0x02907000 0x029070ff SYSTEM

AFC2 0x02907100 0x029071ff SYSTEM

AFC3 0x02907200 0x029072ff SYSTEM

AFC4 0x02907300 0x029073ff SYSTEM

AFC5 0x02907400 0x029074ff SYSTEM

AFC6 0x02907500 0x029075ff SYSTEM

OPE1_COMMON 0x02908000 0x029080ff SYSTEM

OPE1_PEQ 0x02908100 0x029081ff SYSTEM

OPE1_MBDRC 0x02908200 0x029083ff SYSTEM

SPKPROT1 0x02908c00 0x02908fff SYSTEM

MVC1 0x0290a000 0x0290a1ff SYSTEM

MVC2 0x0290a200 0x0290a3ff SYSTEM

AHC 0x0290b900 0x0290baff SYSTEM

MIXER1 0x0290bb00 0x0290c2ff SYSTEM

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Block Name Start Address End Address Address Locality

IQC1 0x0290e000 0x0290e1ff SYSTEM

IQC2 0x0290e200 0x0290e3ff SYSTEM

ARAD 0x0290e400 0x0290e7ff SYSTEM

ADMAIF 0x0290f000 0x0290ffff SYSTEM

ASRC 0x02910000 0x02911fff SYSTEM

APE_ADMA_GLOBAL 0x02930000 0x0293ffff SYSTEM

APE_ADMA_PAGE1 0x02940000 0x0294ffff SYSTEM

APE_ADMA_PAGE2 0x02950000 0x0295ffff SYSTEM

APE_ADMA_PAGE3 0x02960000 0x0296ffff SYSTEM

APE_ADMA_PAGE4 0x02970000 0x0297ffff SYSTEM

APE_AMISC_AMISC 0x02990000 0x029907ff SYSTEM

APE_AMISC_ACTMON 0x02990800 0x02990bff SYSTEM

APE_AMC 0x02993000 0x02993fff SYSTEM

APE_ACAST 0x02994000 0x02995fff SYSTEM

APE_ADAST 0x02996000 0x02997fff SYSTEM

APE_HSP_COMMON 0x029a0000 0x029affff SYSTEM

APE_HSP_SM_0_1 0x029b0000 0x029bffff SYSTEM

APE_HSP_SM_2_3 0x029c0000 0x029cffff SYSTEM

APE_HSP_SM_4_5 0x029d0000 0x029dffff SYSTEM

APE_HSP_SM_6_7 0x029e0000 0x029effff SYSTEM

APE_HSP_SS_0 0x029f0000 0x029fffff SYSTEM

APE_HSP_SS_1 0x02a00000 0x02a0ffff SYSTEM

APE_HSP_SS_2 0x02a10000 0x02a1ffff SYSTEM

APE_HSP_SS_3 0x02a20000 0x02a2ffff SYSTEM

APE_AGIC_PAGE0 0x02a40000 0x02a4ffff SYSTEM

APE_AGIC_PAGE1 0x02a50000 0x02a5ffff SYSTEM

APE_AGIC_PAGE2 0x02a60000 0x02a6ffff SYSTEM

APE_AGIC_PAGE3 0x02a70000 0x02a7ffff SYSTEM

APE_TKE_SHARED 0x02a80000 0x02a8ffff SYSTEM

APE_TKE_TMR_0 0x02a90000 0x02a9ffff SYSTEM

APE_TKE_TMR_1 0x02aa0000 0x02aaffff SYSTEM

APE_TKE_TMR_2 0x02ab0000 0x02abffff SYSTEM

APE_TKE_TMR_3 0x02ac0000 0x02acffff SYSTEM

APE_TKE_WDT_0 0x02ad0000 0x02adffff SYSTEM

MC4 0x02b80000 0x02b8ffff SYSTEM

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Block Name Start Address End Address Address Locality

MC5 0x02b90000 0x02b9ffff SYSTEM

MC6 0x02ba0000 0x02baffff SYSTEM

MC7 0x02bb0000 0x02bbffff SYSTEM

MC_SID 0x02c00000 0x02c0ffff SYSTEM

MCB 0x02c10000 0x02c1ffff SYSTEM

MC0 0x02c20000 0x02c2ffff SYSTEM

MC1 0x02c30000 0x02c3ffff SYSTEM

MC2 0x02c40000 0x02c4ffff SYSTEM

MC3 0x02c50000 0x02c5ffff SYSTEM

EMCB 0x02c60000 0x02c6ffff SYSTEM

EMC0 0x02c70000 0x02c7ffff SYSTEM

EMC1 0x02c80000 0x02c8ffff SYSTEM

EMC2 0x02c90000 0x02c9ffff SYSTEM

EMC3 0x02ca0000 0x02caffff SYSTEM

EMC4 0x02cb0000 0x02cbffff SYSTEM

EMC5 0x02cc0000 0x02ccffff SYSTEM

EMC6 0x02cd0000 0x02cdffff SYSTEM

EMC7 0x02ce0000 0x02ceffff SYSTEM

MSS_QUAL 0x02cf0000 0x02cfffff SYSTEM

UPHY_PLL0 0x02d00000 0x02d1ffff SYSTEM

UPHY_LANE0 0x02d20000 0x02d2ffff SYSTEM

UPHY_LANE1 0x02d30000 0x02d3ffff SYSTEM

UPHY_LANE2 0x02d40000 0x02d4ffff SYSTEM

UPHY_LANE3 0x02d50000 0x02d5ffff SYSTEM

UPHY_LANE4 0x02d60000 0x02d6ffff SYSTEM

UPHY_LANE5 0x02d70000 0x02d7ffff SYSTEM

UPHY_PLL1 0x02d80000 0x02d9ffff SYSTEM

UPHY_LANE6 0x02da0000 0x02daffff SYSTEM

UPHY_LANE7 0x02db0000 0x02dbffff SYSTEM

UPHY_PLL2 0x02dc0000 0x02ddffff SYSTEM

UPHY_LANE8 0x02de0000 0x02deffff SYSTEM

UPHY_LANE9 0x02df0000 0x02dfffff SYSTEM

UPHY_PLL3 0x02e00000 0x02e1ffff SYSTEM

UPHY_LANE10 0x02e20000 0x02e2ffff SYSTEM

UPHY_LANE11 0x02e30000 0x02e3ffff SYSTEM

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Block Name Start Address End Address Address Locality

NVHSUPHY_LANE0 0x02f00000 0x02f0ffff SYSTEM

NVHSUPHY_LANE1 0x02f10000 0x02f1ffff SYSTEM

NVHSUPHY_LANE2 0x02f20000 0x02f2ffff SYSTEM

NVHSUPHY_LANE3 0x02f30000 0x02f3ffff SYSTEM

NVHSUPHY_PLL0 0x02f40000 0x02f5ffff SYSTEM

NVHSUPHY_LANE4 0x02f60000 0x02f6ffff SYSTEM

NVHSUPHY_LANE5 0x02f70000 0x02f7ffff SYSTEM

NVHSUPHY_LANE6 0x02f80000 0x02f8ffff SYSTEM

NVHSUPHY_LANE7 0x02f90000 0x02f9ffff SYSTEM

LIC_CH0 0x03000000 0x030007ff SYSTEM

LIC_CH1 0x03000800 0x03000fff SYSTEM

LIC_CH2 0x03001000 0x030017ff SYSTEM

LIC_CH3 0x03001800 0x03001fff SYSTEM

LIC_CH4 0x03002000 0x030027ff SYSTEM

LIC_CH5 0x03002800 0x03002fff SYSTEM

LIC_CH6 0x03003000 0x030037ff SYSTEM

LIC_CH7 0x03003800 0x03003fff SYSTEM

LIC_COMMON 0x0300f800 0x0300ffff SYSTEM

TMR_SHARED 0x03010000 0x0301ffff SYSTEM

TMR0 0x03020000 0x0302ffff SYSTEM

TMR1 0x03030000 0x0303ffff SYSTEM

TMR2 0x03040000 0x0304ffff SYSTEM

TMR3 0x03050000 0x0305ffff SYSTEM

TMR4 0x03060000 0x0306ffff SYSTEM

TMR5 0x03070000 0x0307ffff SYSTEM

TMR6 0x03080000 0x0308ffff SYSTEM

TMR7 0x03090000 0x0309ffff SYSTEM

TMR8 0x030a0000 0x030affff SYSTEM

TMR9 0x030b0000 0x030bffff SYSTEM

WDT0 0x030c0000 0x030cffff SYSTEM

WDT1 0x030d0000 0x030dffff SYSTEM

WDT2 0x030e0000 0x030effff SYSTEM

UARTA 0x03100000 0x0310ffff SYSTEM

UARTB 0x03110000 0x0311ffff SYSTEM

UARTD 0x03130000 0x0313ffff SYSTEM

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Block Name Start Address End Address Address Locality

UARTE 0x03140000 0x0314ffff SYSTEM

UARTF 0x03150000 0x0315ffff SYSTEM

I2C1 0x03160000 0x0316ffff SYSTEM

UARTH 0x03170000 0x0317ffff SYSTEM

I2C3 0x03180000 0x0318ffff SYSTEM

I2C4 0x03190000 0x0319ffff SYSTEM

I2C5 0x031a0000 0x031affff SYSTEM

I2C6 0x031b0000 0x031bffff SYSTEM

I2C7 0x031c0000 0x031cffff SYSTEM

I2C9 0x031e0000 0x031effff SYSTEM

SPI1 0x03210000 0x0321ffff SYSTEM

SPI3 0x03230000 0x0323ffff SYSTEM

QSPI0 0x03270000 0x0327ffff SYSTEM

PWM1 0x03280000 0x0328ffff SYSTEM

PWM2 0x03290000 0x0329ffff SYSTEM

PWM3 0x032a0000 0x032affff SYSTEM

PWM5 0x032c0000 0x032cffff SYSTEM

PWM6 0x032d0000 0x032dffff SYSTEM

PWM7 0x032e0000 0x032effff SYSTEM

PWM8 0x032f0000 0x032fffff SYSTEM

QSPI1 0x03300000 0x0330ffff SYSTEM

SDMMC1_IMPL 0x03400000 0x0340ffff SYSTEM

SDMMC1B 0x03410000 0x0341ffff SYSTEM

SDMMC3_IMPL 0x03440000 0x0344ffff SYSTEM

SDMMC3B 0x03450000 0x0345ffff SYSTEM

SDMMC4_IMPL 0x03460000 0x0346ffff SYSTEM

SDMMC4B 0x03470000 0x0347ffff SYSTEM

SATA_IFPS 0x03500000 0x03500fff SYSTEM

SATA_CFG 0x03501000 0x03506fff SYSTEM

SATA_AHCI 0x03507000 0x0350ffff SYSTEM

HDA 0x03510000 0x0351ffff SYSTEM

XUSB_PADCTL 0x03520000 0x0352ffff SYSTEM

XUSB_AO 0x03540000 0x0354ffff SYSTEM

XUSB_DEV_BAR0 0x03550000 0x03557fff SYSTEM

XUSB_DEV_CFG 0x03558000 0x0355ffff SYSTEM

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Block Name Start Address End Address Address Locality

XUSB_HOST_PF_CFG 0x03600000 0x0360ffff SYSTEM

XUSB_HOST_PF_BAR0_OP 0x03610000 0x0362ffff SYSTEM

XUSB_HOST_PF_BAR0_RT 0x03630000 0x0363ffff SYSTEM

XUSB_HOST_PF_BAR0_DB 0x03640000 0x0364ffff SYSTEM

XUSB_HOST_VF0_CFG 0x03650000 0x0365ffff SYSTEM

XUSB_HOST_VF0_BAR0_OP 0x03660000 0x0367ffff SYSTEM

XUSB_HOST_VF0_BAR0_RT 0x03680000 0x0368ffff SYSTEM

XUSB_HOST_VF0_BAR0_DB 0x03690000 0x0369ffff SYSTEM

XUSB_HOST_VF1_CFG 0x036a0000 0x036affff SYSTEM

XUSB_HOST_VF1_BAR0_OP 0x036b0000 0x036cffff SYSTEM

XUSB_HOST_VF1_BAR0_RT 0x036d0000 0x036dffff SYSTEM

XUSB_HOST_VF1_BAR0_DB 0x036e0000 0x036effff SYSTEM

XUSB_HOST_VF2_CFG 0x036f0000 0x036fffff SYSTEM

XUSB_HOST_VF2_BAR0_OP 0x03700000 0x0371ffff SYSTEM

XUSB_HOST_VF2_BAR0_RT 0x03720000 0x0372ffff SYSTEM

XUSB_HOST_VF2_BAR0_DB 0x03730000 0x0373ffff SYSTEM

XUSB_HOST_VF3_CFG 0x03740000 0x0374ffff SYSTEM

XUSB_HOST_VF3_BAR0_OP 0x03750000 0x0376ffff SYSTEM

XUSB_HOST_VF3_BAR0_RT 0x03770000 0x0377ffff SYSTEM

XUSB_HOST_VF3_BAR0_DB 0x03780000 0x0378ffff SYSTEM

PEXCLK0 0x03790000 0x0379ffff SYSTEM

PEXCLK1 0x037a0000 0x037affff SYSTEM

CCPLEX_GIC 0x03881000 0x03881fff CCPLEX

CCPLEX_GIC_A 0x03882000 0x03883fff CCPLEX

CCPLEX_GIC_B 0x03884000 0x03884fff CCPLEX

CCPLEX_GIC_C 0x03885000 0x03885fff CCPLEX

CCPLEX_GIC_D 0x03886000 0x03887fff CCPLEX

CCPLEX_GIC_A_ALIAS_0 0x03892000 0x03893fff CCPLEX

CCPLEX_GIC_A_ALIAS_1 0x038a2000 0x038a3fff CCPLEX

CEC 0x03960000 0x0396ffff SYSTEM

MIPI_CAL 0x03990000 0x0399ffff SYSTEM

TACH_0 0x039c0000 0x039cffff SYSTEM

IST 0x03a60000 0x03a6ffff SYSTEM

SATA_AUX 0x03a90000 0x03a9ffff SYSTEM

LIC_GTE0 0x03aa0000 0x03aaffff SYSTEM

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Block Name Start Address End Address Address Locality

LIC_GTE1 0x03ab0000 0x03abffff SYSTEM

IST_LINK_CTL 0x03af0000 0x03af0fff SYSTEM

IST_LINK_CTL1 0x03af1000 0x03af1fff SYSTEM

TOP0_HSP_COMMON 0x03c00000 0x03c0ffff SYSTEM

TOP0_HSP_SM_0_1 0x03c10000 0x03c1ffff SYSTEM

TOP0_HSP_SM_2_3 0x03c20000 0x03c2ffff SYSTEM

TOP0_HSP_SM_4_5 0x03c30000 0x03c3ffff SYSTEM

TOP0_HSP_SM_6_7 0x03c40000 0x03c4ffff SYSTEM

TOP0_HSP_SS_0 0x03c50000 0x03c5ffff SYSTEM

TOP0_HSP_SS_1 0x03c60000 0x03c6ffff SYSTEM

TOP0_HSP_AS_0 0x03c70000 0x03c7ffff SYSTEM

TOP0_HSP_AS_1 0x03c80000 0x03c8ffff SYSTEM

TOP0_HSP_DB_0 0x03c90000 0x03c9ffff SYSTEM

TOP1_HSP_COMMON 0x03d00000 0x03d0ffff SYSTEM

TOP1_HSP_SM_0_1 0x03d10000 0x03d1ffff SYSTEM

TOP1_HSP_SM_2_3 0x03d20000 0x03d2ffff SYSTEM

TOP1_HSP_SM_4_5 0x03d30000 0x03d3ffff SYSTEM

TOP1_HSP_SM_6_7 0x03d40000 0x03d4ffff SYSTEM

TOP1_HSP_SS_0 0x03d50000 0x03d5ffff SYSTEM

TOP1_HSP_SS_1 0x03d60000 0x03d6ffff SYSTEM

TOP1_HSP_SS_2 0x03d70000 0x03d7ffff SYSTEM

TOP1_HSP_SS_3 0x03d80000 0x03d8ffff SYSTEM

PIPE2UPHY_XBAR 0x03e00000 0x03e0ffff SYSTEM

PIPE2UPHY_0 0x03e10000 0x03e1ffff SYSTEM

PIPE2UPHY_1 0x03e20000 0x03e2ffff SYSTEM

PIPE2UPHY_2 0x03e30000 0x03e3ffff SYSTEM

PIPE2UPHY_3 0x03e40000 0x03e4ffff SYSTEM

PIPE2UPHY_4 0x03e50000 0x03e5ffff SYSTEM

PIPE2UPHY_5 0x03e60000 0x03e6ffff SYSTEM

PIPE2UPHY_6 0x03e70000 0x03e7ffff SYSTEM

PIPE2UPHY_7 0x03e80000 0x03e8ffff SYSTEM

PIPE2UPHY_8 0x03e90000 0x03e9ffff SYSTEM

PIPE2UPHY_9 0x03ea0000 0x03eaffff SYSTEM

PIPE2UPHY_10 0x03eb0000 0x03ebffff SYSTEM

PIPE2UPHY_11 0x03ec0000 0x03ecffff SYSTEM

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Block Name Start Address End Address Address Locality

PIPE2UPHY_12 0x03ed0000 0x03edffff SYSTEM

PIPE2UPHY_13 0x03ee0000 0x03eeffff SYSTEM

PIPE2UPHY_14 0x03ef0000 0x03efffff SYSTEM

PIPE2UPHY_15 0x03f00000 0x03f0ffff SYSTEM

PIPE2UPHY_16 0x03f10000 0x03f1ffff SYSTEM

PIPE2UPHY_17 0x03f20000 0x03f2ffff SYSTEM

PIPE2UPHY_18 0x03f30000 0x03f3ffff SYSTEM

PIPE2UPHY_19 0x03f40000 0x03f4ffff SYSTEM

SCE_ATCM_CFG_EVP 0x0b000000 0x0b00ffff SYSTEM

SCE_VIC_0 0x0b020000 0x0b02ffff SYSTEM

SCE_VIC_1 0x0b030000 0x0b03ffff SYSTEM

SCE_AST_0 0x0b040000 0x0b04ffff SYSTEM

SCE_AST_1 0x0b050000 0x0b05ffff SYSTEM

SCE_DMA_COMMON 0x0b060000 0x0b06ffff SYSTEM

SCE_DMA_CH_0 0x0b070000 0x0b07ffff SYSTEM

SCE_DMA_CH_1 0x0b080000 0x0b08ffff SYSTEM

SCE_DMA_CH_2 0x0b090000 0x0b09ffff SYSTEM

SCE_DMA_CH_3 0x0b0a0000 0x0b0affff SYSTEM

SCE_DMA_CH_4 0x0b0b0000 0x0b0bffff SYSTEM

SCE_DMA_CH_5 0x0b0c0000 0x0b0cffff SYSTEM

SCE_DMA_CH_6 0x0b0d0000 0x0b0dffff SYSTEM

SCE_DMA_CH_7 0x0b0e0000 0x0b0effff SYSTEM

SCE_TKE_SHARED 0x0b0f0000 0x0b0fffff SYSTEM

SCE_TKE_TMR_0 0x0b100000 0x0b10ffff SYSTEM

SCE_TKE_TMR_1 0x0b110000 0x0b11ffff SYSTEM

SCE_TKE_TMR_2 0x0b120000 0x0b12ffff SYSTEM

SCE_TKE_TMR_3 0x0b130000 0x0b13ffff SYSTEM

SCE_TKE_WDT_0 0x0b140000 0x0b14ffff SYSTEM

SCE_HSP_COMMON 0x0b150000 0x0b15ffff SYSTEM

SCE_HSP_SM_0_1 0x0b160000 0x0b16ffff SYSTEM

SCE_HSP_SM_2_3 0x0b170000 0x0b17ffff SYSTEM

SCE_HSP_SM_4_5 0x0b180000 0x0b18ffff SYSTEM

SCE_HSP_SM_6_7 0x0b190000 0x0b19ffff SYSTEM

SCE_HSP_SS_0 0x0b1a0000 0x0b1affff SYSTEM

SCE_HSP_SS_1 0x0b1b0000 0x0b1bffff SYSTEM

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Block Name Start Address End Address Address Locality

SCE_HSP_SS_2 0x0b1c0000 0x0b1cffff SYSTEM

SCE_HSP_SS_3 0x0b1d0000 0x0b1dffff SYSTEM

SCE_GTE 0x0b1e0000 0x0b1effff SYSTEM

SCE_PM_IMPL 0x0b1f0000 0x0b1fffff SYSTEM

SCE_ACTMON 0x0b200000 0x0b20ffff SYSTEM

SCE_CFG 0x0b230000 0x0b23ffff SYSTEM

HSM 0x0b240000 0x0b24ffff SYSTEM

SCE_FPGA_UART 0x0b3d0000 0x0b3dffff SYSTEM

SCE_FPGA_MISC 0x0b3e0000 0x0b3effff SYSTEM

SCE_ATCM_EVP_EXT 0x0b400000 0x0b40ffff SYSTEM

SCE_BTCM 0x0b480000 0x0b4dffff SYSTEM

SCE_ICACHE_ACCESS_PORT 0x0b500000 0x0b57ffff SYSTEM

SCE_DCACHE_ACCESS_PORT 0x0b580000 0x0b5fffff SYSTEM

SCE_ERR_OBSERVER 0x0b600000 0x0b60ffff SYSTEM

SCE_FAULT_PWR 0x0b610000 0x0b61ffff SYSTEM

SCE_FIREWALL 0x0b640000 0x0b64ffff SYSTEM

SCE_ERR_COLLATOR 0x0b650000 0x0b65ffff SYSTEM

SCE_MISC 0x0b660000 0x0b66ffff SYSTEM

RCE_ATCM_CFG_EVP 0x0b800000 0x0b80ffff SYSTEM

RCE_VIC_0 0x0b820000 0x0b82ffff SYSTEM

RCE_VIC_1 0x0b830000 0x0b83ffff SYSTEM

RCE_AST_0 0x0b840000 0x0b84ffff SYSTEM

RCE_AST_1 0x0b850000 0x0b85ffff SYSTEM

RCE_DMA_COMMON 0x0b860000 0x0b86ffff SYSTEM

RCE_DMA_CH_0 0x0b870000 0x0b87ffff SYSTEM

RCE_DMA_CH_1 0x0b880000 0x0b88ffff SYSTEM

RCE_DMA_CH_2 0x0b890000 0x0b89ffff SYSTEM

RCE_DMA_CH_3 0x0b8a0000 0x0b8affff SYSTEM

RCE_DMA_CH_4 0x0b8b0000 0x0b8bffff SYSTEM

RCE_DMA_CH_5 0x0b8c0000 0x0b8cffff SYSTEM

RCE_DMA_CH_6 0x0b8d0000 0x0b8dffff SYSTEM

RCE_DMA_CH_7 0x0b8e0000 0x0b8effff SYSTEM

RCE_TKE_SHARED 0x0b8f0000 0x0b8fffff SYSTEM

RCE_TKE_TMR_0 0x0b900000 0x0b90ffff SYSTEM

RCE_TKE_TMR_1 0x0b910000 0x0b91ffff SYSTEM

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Block Name Start Address End Address Address Locality

RCE_TKE_TMR_2 0x0b920000 0x0b92ffff SYSTEM

RCE_TKE_TMR_3 0x0b930000 0x0b93ffff SYSTEM

RCE_TKE_WDT_0 0x0b940000 0x0b94ffff SYSTEM

RCE_HSP_COMMON 0x0b950000 0x0b95ffff SYSTEM

RCE_HSP_SM_0_1 0x0b960000 0x0b96ffff SYSTEM

RCE_HSP_SM_2_3 0x0b970000 0x0b97ffff SYSTEM

RCE_HSP_SM_4_5 0x0b980000 0x0b98ffff SYSTEM

RCE_HSP_SM_6_7 0x0b990000 0x0b99ffff SYSTEM

RCE_HSP_SS_0 0x0b9a0000 0x0b9affff SYSTEM

RCE_HSP_SS_1 0x0b9b0000 0x0b9bffff SYSTEM

RCE_HSP_SS_2 0x0b9c0000 0x0b9cffff SYSTEM

RCE_HSP_SS_3 0x0b9d0000 0x0b9dffff SYSTEM

RCE_GTE 0x0b9e0000 0x0b9effff SYSTEM

RCE_PM_IMPL 0x0b9f0000 0x0b9fffff SYSTEM

RCE_ACTMON 0x0ba00000 0x0ba0ffff SYSTEM

RCE_CFG 0x0ba30000 0x0ba3ffff SYSTEM

RCE_HSM 0x0ba40000 0x0ba4ffff SYSTEM

RCE_FPGA_UART 0x0bbd0000 0x0bbdffff SYSTEM

RCE_FPGA_MISC 0x0bbe0000 0x0bbeffff SYSTEM

RCE_ATCM_EVP_EXT 0x0bc00000 0x0bc0ffff SYSTEM

RCE_BTCM 0x0bc80000 0x0bcdffff SYSTEM

RCE_ICACHE_ACCESS_PORT 0x0bd00000 0x0bd7ffff SYSTEM

RCE_DCACHE_ACCESS_PORT 0x0bd80000 0x0bdfffff SYSTEM

RCE_ERR_OBSERVER 0x0be00000 0x0be0ffff SYSTEM

RCE_FAULT_PWR 0x0be10000 0x0be1ffff SYSTEM

RCE_FIREWALL 0x0be40000 0x0be4ffff SYSTEM

RCE_ERR_COLLATOR 0x0be50000 0x0be5ffff SYSTEM

RCE_MISC 0x0be60000 0x0be6ffff SYSTEM

AON_ATCM_CFG_EVP 0x0c000000 0x0c00ffff SYSTEM

AON_VIC_0 0x0c020000 0x0c02ffff SYSTEM

AON_VIC_1 0x0c030000 0x0c03ffff SYSTEM

AON_AST_0 0x0c040000 0x0c04ffff SYSTEM

AON_AST_1 0x0c050000 0x0c05ffff SYSTEM

AON_DMA_COMMON 0x0c060000 0x0c06ffff SYSTEM

AON_DMA_CH_0 0x0c070000 0x0c07ffff SYSTEM

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Block Name Start Address End Address Address Locality

AON_DMA_CH_1 0x0c080000 0x0c08ffff SYSTEM

AON_DMA_CH_2 0x0c090000 0x0c09ffff SYSTEM

AON_DMA_CH_3 0x0c0a0000 0x0c0affff SYSTEM

AON_DMA_CH_4 0x0c0b0000 0x0c0bffff SYSTEM

AON_DMA_CH_5 0x0c0c0000 0x0c0cffff SYSTEM

AON_DMA_CH_6 0x0c0d0000 0x0c0dffff SYSTEM

AON_DMA_CH_7 0x0c0e0000 0x0c0effff SYSTEM

AON_TKE_SHARED 0x0c0f0000 0x0c0fffff SYSTEM

AON_TKE_TMR_0 0x0c100000 0x0c10ffff SYSTEM

AON_TKE_TMR_1 0x0c110000 0x0c11ffff SYSTEM

AON_TKE_TMR_2 0x0c120000 0x0c12ffff SYSTEM

AON_TKE_TMR_3 0x0c130000 0x0c13ffff SYSTEM

AON_TKE_WDT_0 0x0c140000 0x0c14ffff SYSTEM

AON_HSP_COMMON 0x0c150000 0x0c15ffff SYSTEM

AON_HSP_SM_0_1 0x0c160000 0x0c16ffff SYSTEM

AON_HSP_SM_2_3 0x0c170000 0x0c17ffff SYSTEM

AON_HSP_SM_4_5 0x0c180000 0x0c18ffff SYSTEM

AON_HSP_SM_6_7 0x0c190000 0x0c19ffff SYSTEM

AON_HSP_SS_0 0x0c1a0000 0x0c1affff SYSTEM

AON_HSP_SS_1 0x0c1b0000 0x0c1bffff SYSTEM

AON_HSP_SS_2 0x0c1c0000 0x0c1cffff SYSTEM

AON_HSP_SS_3 0x0c1d0000 0x0c1dffff SYSTEM

AON_GTE 0x0c1e0000 0x0c1effff SYSTEM

AON_PM_IMPL 0x0c1f0000 0x0c1fffff SYSTEM

AON_ACTMON 0x0c200000 0x0c20ffff SYSTEM

AON_CAN_RAM_CTL 0x0c210000 0x0c21ffff SYSTEM

I2C10 0x0c230000 0x0c23ffff SYSTEM

I2C2 0x0c240000 0x0c24ffff SYSTEM

I2C8 0x0c250000 0x0c25ffff SYSTEM

SPI2 0x0c260000 0x0c26ffff SYSTEM

UARTC 0x0c280000 0x0c28ffff SYSTEM

UARTG 0x0c290000 0x0c29ffff SYSTEM

RTC 0x0c2a0000 0x0c2affff SYSTEM

SYSCTR0 0x0c2b0000 0x0c2bffff SYSTEM

SYSCTR1 0x0c2c0000 0x0c2cffff SYSTEM

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Block Name Start Address End Address Address Locality

TSC_IMPL 0x0c2d0000 0x0c2dffff SYSTEM

TSCUS 0x0c2e0000 0x0c2effff SYSTEM

AON_GPIO_0 0x0c2f0000 0x0c2fffff SYSTEM

PADCTL_A12 0x0c301000 0x0c301fff SYSTEM

PADCTL_A14 0x0c302000 0x0c302fff SYSTEM

PADCTL_A15 0x0c303000 0x0c303fff SYSTEM

CAN1 0x0c310000 0x0c31ffff SYSTEM

CAN2 0x0c320000 0x0c32ffff SYSTEM

DMIC5 0x0c330000 0x0c33ffff SYSTEM

PWM4 0x0c340000 0x0c34ffff SYSTEM

AON_MSS 0x0c350000 0x0c35ffff SYSTEM

PMC_IMPL 0x0c360000 0x0c36ffff SYSTEM

WAKE 0x0c370000 0x0c37ffff SYSTEM

AOTAG 0x0c380000 0x0c38ffff SYSTEM

SCRATCH 0x0c390000 0x0c39ffff SYSTEM

PMC_MISC 0x0c3a0000 0x0c3affff SYSTEM

AOVC 0x0c3b0000 0x0c3bffff SYSTEM

AON_FPGA_MISC 0x0c3e0000 0x0c3effff SYSTEM

AON_ATCM_EVP_EXT 0x0c400000 0x0c40ffff SYSTEM

AON_BTCM 0x0c480000 0x0c4bffff SYSTEM

AON_ICACHE_ACCESS_PORT 0x0c500000 0x0c57ffff SYSTEM

AON_DCACHE_ACCESS_PORT 0x0c580000 0x0c5fffff SYSTEM

AON_ERR_OBSERVER 0x0c600000 0x0c60ffff SYSTEM

AON_FAULT_PWR 0x0c610000 0x0c61ffff SYSTEM

AON_FIREWALL 0x0c640000 0x0c64ffff SYSTEM

AON_ERR_COLLATOR 0x0c650000 0x0c65ffff SYSTEM

AON_MISC 0x0c660000 0x0c66ffff SYSTEM

ACTMON 0x0d230000 0x0d23ffff SYSTEM

SIMON0 0x0d240000 0x0d24ffff SYSTEM

SIMON1 0x0d250000 0x0d25ffff SYSTEM

SIMON2 0x0d260000 0x0d26ffff SYSTEM

SIMON3 0x0d270000 0x0d27ffff SYSTEM

SOC_THERM 0x0d280000 0x0d28ffff SYSTEM

CENTRAL_VTG_CTLR 0x0d290000 0x0d29ffff SYSTEM

CENTRAL_PWR_MGR 0x0d2a0000 0x0d2affff SYSTEM

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Block Name Start Address End Address Address Locality

SIMON4 0x0d2b0000 0x0d2bffff SYSTEM

CCPLEX_MMCRAB_ARM 0x0e000000 0x0e3fffff CCPLEX

AXIS_NIC_0 0x0f000000 0x0f0fffff SYSTEM

SMMU2_64KB_PAGESIZE_GR0 0x10000000 0x1000ffff SYSTEM_CFG.SMMU2_64KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.1

SMMU2_4KB_PAGESIZE_GR0 0x10000000 0x10000fff SYSTEM_CFG.SMMU2_4KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.0

SMMU2_4KB_PAGESIZE_GR1 0x10001000 0x10001fff SYSTEM_CFG.SMMU2_4KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.0

SMMU2_4KB_PAGESIZE_GID 0x10002000 0x10002fff SYSTEM_CFG.SMMU2_4KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.0

SMMU2_4KB_PAGESIZE_PM 0x10003000 0x10003fff SYSTEM_CFG.SMMU2_4KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.0

SMMU2_64KB_PAGESIZE_GR1 0x10010000 0x1001ffff SYSTEM_CFG.SMMU2_64KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.1

SMMU2_64KB_PAGESIZE_GID 0x10020000 0x1002ffff SYSTEM_CFG.SMMU2_64KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.1

SMMU2_64KB_PAGESIZE_PM 0x10030000 0x1003ffff SYSTEM_CFG.SMMU2_64KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.1

SMMU2_4KB_PAGESIZE_CB0 0x10040000 0x10040fff SYSTEM_CFG.SMMU2_4KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.0

SMMU2_4KB_PAGESIZE_CB1 0x10041000 0x10041fff SYSTEM_CFG.SMMU2_4KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.0

SMMU2_4KB_PAGESIZE_CB2 0x10042000 0x10042fff SYSTEM_CFG.SMMU2_4KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.0

SMMU2_4KB_PAGESIZE_CB3 0x10043000 0x10043fff SYSTEM_CFG.SMMU2_4KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.0

SMMU2_4KB_PAGESIZE_CB4 0x10044000 0x10044fff SYSTEM_CFG.SMMU2_4KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.0

SMMU2_4KB_PAGESIZE_CB5 0x10045000 0x10045fff SYSTEM_CFG.SMMU2_4KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.0

SMMU2_4KB_PAGESIZE_CB6 0x10046000 0x10046fff SYSTEM_CFG.SMMU2_4KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.0

SMMU2_4KB_PAGESIZE_CB7 0x10047000 0x10047fff SYSTEM_CFG.SMMU2_4KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.0

SMMU2_4KB_PAGESIZE_CB8 0x10048000 0x10048fff SYSTEM_CFG.SMMU2_4KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.0

SMMU2_4KB_PAGESIZE_CB9 0x10049000 0x10049fff SYSTEM_CFG.SMMU2_4KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.0

SMMU2_4KB_PAGESIZE_CB10

0x1004a000

0x1004afff

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Block Name Start Address End Address Address Locality

SYSTEM_CFG.SMMU2_4KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.0

SMMU2_4KB_PAGESIZE_CB11 0x1004b000 0x1004bfff SYSTEM_CFG.SMMU2_4KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.0

SMMU2_4KB_PAGESIZE_CB12 0x1004c000 0x1004cfff SYSTEM_CFG.SMMU2_4KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.0

SMMU2_4KB_PAGESIZE_CB13 0x1004d000 0x1004dfff SYSTEM_CFG.SMMU2_4KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.0

SMMU2_4KB_PAGESIZE_CB14 0x1004e000 0x1004efff SYSTEM_CFG.SMMU2_4KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.0

SMMU2_4KB_PAGESIZE_CB15 0x1004f000 0x1004ffff SYSTEM_CFG.SMMU2_4KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.0

SMMU2_4KB_PAGESIZE_CB16 0x10050000 0x10050fff SYSTEM_CFG.SMMU2_4KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.0

SMMU2_4KB_PAGESIZE_CB17 0x10051000 0x10051fff SYSTEM_CFG.SMMU2_4KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.0

SMMU2_4KB_PAGESIZE_CB18 0x10052000 0x10052fff SYSTEM_CFG.SMMU2_4KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.0

SMMU2_4KB_PAGESIZE_CB19 0x10053000 0x10053fff SYSTEM_CFG.SMMU2_4KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.0

SMMU2_4KB_PAGESIZE_CB20 0x10054000 0x10054fff SYSTEM_CFG.SMMU2_4KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.0

SMMU2_4KB_PAGESIZE_CB21 0x10055000 0x10055fff SYSTEM_CFG.SMMU2_4KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.0

SMMU2_4KB_PAGESIZE_CB22 0x10056000 0x10056fff SYSTEM_CFG.SMMU2_4KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.0

SMMU2_4KB_PAGESIZE_CB23 0x10057000 0x10057fff SYSTEM_CFG.SMMU2_4KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.0

SMMU2_4KB_PAGESIZE_CB24 0x10058000 0x10058fff SYSTEM_CFG.SMMU2_4KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.0

SMMU2_4KB_PAGESIZE_CB25 0x10059000 0x10059fff SYSTEM_CFG.SMMU2_4KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.0

SMMU2_4KB_PAGESIZE_CB26 0x1005a000 0x1005afff SYSTEM_CFG.SMMU2_4KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.0

SMMU2_4KB_PAGESIZE_CB27 0x1005b000 0x1005bfff SYSTEM_CFG.SMMU2_4KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.0

SMMU2_4KB_PAGESIZE_CB28 0x1005c000 0x1005cfff SYSTEM_CFG.SMMU2_4KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.0

SMMU2_4KB_PAGESIZE_CB29 0x1005d000 0x1005dfff SYSTEM_CFG.SMMU2_4KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.0

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Block Name Start Address End Address Address Locality

SMMU2_4KB_PAGESIZE_CB30 0x1005e000 0x1005efff SYSTEM_CFG.SMMU2_4KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.0

SMMU2_4KB_PAGESIZE_CB31 0x1005f000 0x1005ffff SYSTEM_CFG.SMMU2_4KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.0

SMMU2_4KB_PAGESIZE_CB32 0x10060000 0x10060fff SYSTEM_CFG.SMMU2_4KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.0

SMMU2_4KB_PAGESIZE_CB33 0x10061000 0x10061fff SYSTEM_CFG.SMMU2_4KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.0

SMMU2_4KB_PAGESIZE_CB34 0x10062000 0x10062fff SYSTEM_CFG.SMMU2_4KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.0

SMMU2_4KB_PAGESIZE_CB35 0x10063000 0x10063fff SYSTEM_CFG.SMMU2_4KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.0

SMMU2_4KB_PAGESIZE_CB36 0x10064000 0x10064fff SYSTEM_CFG.SMMU2_4KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.0

SMMU2_4KB_PAGESIZE_CB37 0x10065000 0x10065fff SYSTEM_CFG.SMMU2_4KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.0

SMMU2_4KB_PAGESIZE_CB38 0x10066000 0x10066fff SYSTEM_CFG.SMMU2_4KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.0

SMMU2_4KB_PAGESIZE_CB39 0x10067000 0x10067fff SYSTEM_CFG.SMMU2_4KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.0

SMMU2_4KB_PAGESIZE_CB40 0x10068000 0x10068fff SYSTEM_CFG.SMMU2_4KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.0

SMMU2_4KB_PAGESIZE_CB41 0x10069000 0x10069fff SYSTEM_CFG.SMMU2_4KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.0

SMMU2_4KB_PAGESIZE_CB42 0x1006a000 0x1006afff SYSTEM_CFG.SMMU2_4KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.0

SMMU2_4KB_PAGESIZE_CB43 0x1006b000 0x1006bfff SYSTEM_CFG.SMMU2_4KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.0

SMMU2_4KB_PAGESIZE_CB44 0x1006c000 0x1006cfff SYSTEM_CFG.SMMU2_4KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.0

SMMU2_4KB_PAGESIZE_CB45 0x1006d000 0x1006dfff SYSTEM_CFG.SMMU2_4KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.0

SMMU2_4KB_PAGESIZE_CB46 0x1006e000 0x1006efff SYSTEM_CFG.SMMU2_4KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.0

SMMU2_4KB_PAGESIZE_CB47 0x1006f000 0x1006ffff SYSTEM_CFG.SMMU2_4KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.0

SMMU2_4KB_PAGESIZE_CB48 0x10070000 0x10070fff SYSTEM_CFG.SMMU2_4KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.0

SMMU2_4KB_PAGESIZE_CB49 0x10071000 0x10071fff SYSTEM_CFG.SMMU2_4KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.0

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Block Name Start Address End Address Address Locality

SMMU2_4KB_PAGESIZE_CB50 0x10072000 0x10072fff SYSTEM_CFG.SMMU2_4KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.0

SMMU2_4KB_PAGESIZE_CB51 0x10073000 0x10073fff SYSTEM_CFG.SMMU2_4KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.0

SMMU2_4KB_PAGESIZE_CB52 0x10074000 0x10074fff SYSTEM_CFG.SMMU2_4KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.0

SMMU2_4KB_PAGESIZE_CB53 0x10075000 0x10075fff SYSTEM_CFG.SMMU2_4KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.0

SMMU2_4KB_PAGESIZE_CB54 0x10076000 0x10076fff SYSTEM_CFG.SMMU2_4KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.0

SMMU2_4KB_PAGESIZE_CB55 0x10077000 0x10077fff SYSTEM_CFG.SMMU2_4KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.0

SMMU2_4KB_PAGESIZE_CB56 0x10078000 0x10078fff SYSTEM_CFG.SMMU2_4KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.0

SMMU2_4KB_PAGESIZE_CB57 0x10079000 0x10079fff SYSTEM_CFG.SMMU2_4KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.0

SMMU2_4KB_PAGESIZE_CB58 0x1007a000 0x1007afff SYSTEM_CFG.SMMU2_4KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.0

SMMU2_4KB_PAGESIZE_CB59 0x1007b000 0x1007bfff SYSTEM_CFG.SMMU2_4KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.0

SMMU2_4KB_PAGESIZE_CB60 0x1007c000 0x1007cfff SYSTEM_CFG.SMMU2_4KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.0

SMMU2_4KB_PAGESIZE_CB61 0x1007d000 0x1007dfff SYSTEM_CFG.SMMU2_4KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.0

SMMU2_4KB_PAGESIZE_CB62 0x1007e000 0x1007efff SYSTEM_CFG.SMMU2_4KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.0

SMMU2_4KB_PAGESIZE_CB63 0x1007f000 0x1007ffff SYSTEM_CFG.SMMU2_4KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.0

SMMU2_64KB_PAGESIZE_CB0 0x10400000 0x1040ffff SYSTEM_CFG.SMMU2_64KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.1

SMMU2_64KB_PAGESIZE_CB1 0x10410000 0x1041ffff SYSTEM_CFG.SMMU2_64KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.1

SMMU2_64KB_PAGESIZE_CB2 0x10420000 0x1042ffff SYSTEM_CFG.SMMU2_64KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.1

SMMU2_64KB_PAGESIZE_CB3 0x10430000 0x1043ffff SYSTEM_CFG.SMMU2_64KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.1

SMMU2_64KB_PAGESIZE_CB4 0x10440000 0x1044ffff SYSTEM_CFG.SMMU2_64KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.1

SMMU2_64KB_PAGESIZE_CB5 0x10450000 0x1045ffff SYSTEM_CFG.SMMU2_64KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.1

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Block Name Start Address End Address Address Locality

SMMU2_64KB_PAGESIZE_CB6 0x10460000 0x1046ffff SYSTEM_CFG.SMMU2_64KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.1

SMMU2_64KB_PAGESIZE_CB7 0x10470000 0x1047ffff SYSTEM_CFG.SMMU2_64KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.1

SMMU2_64KB_PAGESIZE_CB8 0x10480000 0x1048ffff SYSTEM_CFG.SMMU2_64KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.1

SMMU2_64KB_PAGESIZE_CB9 0x10490000 0x1049ffff SYSTEM_CFG.SMMU2_64KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.1

SMMU2_64KB_PAGESIZE_CB10 0x104a0000 0x104affff SYSTEM_CFG.SMMU2_64KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.1

SMMU2_64KB_PAGESIZE_CB11 0x104b0000 0x104bffff SYSTEM_CFG.SMMU2_64KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.1

SMMU2_64KB_PAGESIZE_CB12 0x104c0000 0x104cffff SYSTEM_CFG.SMMU2_64KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.1

SMMU2_64KB_PAGESIZE_CB13 0x104d0000 0x104dffff SYSTEM_CFG.SMMU2_64KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.1

SMMU2_64KB_PAGESIZE_CB14 0x104e0000 0x104effff SYSTEM_CFG.SMMU2_64KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.1

SMMU2_64KB_PAGESIZE_CB15 0x104f0000 0x104fffff SYSTEM_CFG.SMMU2_64KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.1

SMMU2_64KB_PAGESIZE_CB16 0x10500000 0x1050ffff SYSTEM_CFG.SMMU2_64KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.1

SMMU2_64KB_PAGESIZE_CB17 0x10510000 0x1051ffff SYSTEM_CFG.SMMU2_64KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.1

SMMU2_64KB_PAGESIZE_CB18 0x10520000 0x1052ffff SYSTEM_CFG.SMMU2_64KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.1

SMMU2_64KB_PAGESIZE_CB19 0x10530000 0x1053ffff SYSTEM_CFG.SMMU2_64KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.1

SMMU2_64KB_PAGESIZE_CB20 0x10540000 0x1054ffff SYSTEM_CFG.SMMU2_64KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.1

SMMU2_64KB_PAGESIZE_CB21 0x10550000 0x1055ffff SYSTEM_CFG.SMMU2_64KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.1

SMMU2_64KB_PAGESIZE_CB22 0x10560000 0x1056ffff SYSTEM_CFG.SMMU2_64KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.1

SMMU2_64KB_PAGESIZE_CB23 0x10570000 0x1057ffff SYSTEM_CFG.SMMU2_64KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.1

SMMU2_64KB_PAGESIZE_CB24 0x10580000 0x1058ffff SYSTEM_CFG.SMMU2_64KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.1

SMMU2_64KB_PAGESIZE_CB25 0x10590000 0x1059ffff SYSTEM_CFG.SMMU2_64KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.1

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Block Name Start Address End Address Address Locality

SMMU2_64KB_PAGESIZE_CB26 0x105a0000 0x105affff SYSTEM_CFG.SMMU2_64KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.1

SMMU2_64KB_PAGESIZE_CB27 0x105b0000 0x105bffff SYSTEM_CFG.SMMU2_64KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.1

SMMU2_64KB_PAGESIZE_CB28 0x105c0000 0x105cffff SYSTEM_CFG.SMMU2_64KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.1

SMMU2_64KB_PAGESIZE_CB29 0x105d0000 0x105dffff SYSTEM_CFG.SMMU2_64KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.1

SMMU2_64KB_PAGESIZE_CB30 0x105e0000 0x105effff SYSTEM_CFG.SMMU2_64KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.1

SMMU2_64KB_PAGESIZE_CB31 0x105f0000 0x105fffff SYSTEM_CFG.SMMU2_64KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.1

SMMU2_64KB_PAGESIZE_CB32 0x10600000 0x1060ffff SYSTEM_CFG.SMMU2_64KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.1

SMMU2_64KB_PAGESIZE_CB33 0x10610000 0x1061ffff SYSTEM_CFG.SMMU2_64KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.1

SMMU2_64KB_PAGESIZE_CB34 0x10620000 0x1062ffff SYSTEM_CFG.SMMU2_64KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.1

SMMU2_64KB_PAGESIZE_CB35 0x10630000 0x1063ffff SYSTEM_CFG.SMMU2_64KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.1

SMMU2_64KB_PAGESIZE_CB36 0x10640000 0x1064ffff SYSTEM_CFG.SMMU2_64KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.1

SMMU2_64KB_PAGESIZE_CB37 0x10650000 0x1065ffff SYSTEM_CFG.SMMU2_64KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.1

SMMU2_64KB_PAGESIZE_CB38 0x10660000 0x1066ffff SYSTEM_CFG.SMMU2_64KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.1

SMMU2_64KB_PAGESIZE_CB39 0x10670000 0x1067ffff SYSTEM_CFG.SMMU2_64KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.1

SMMU2_64KB_PAGESIZE_CB40 0x10680000 0x1068ffff SYSTEM_CFG.SMMU2_64KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.1

SMMU2_64KB_PAGESIZE_CB41 0x10690000 0x1069ffff SYSTEM_CFG.SMMU2_64KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.1

SMMU2_64KB_PAGESIZE_CB42 0x106a0000 0x106affff SYSTEM_CFG.SMMU2_64KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.1

SMMU2_64KB_PAGESIZE_CB43 0x106b0000 0x106bffff SYSTEM_CFG.SMMU2_64KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.1

SMMU2_64KB_PAGESIZE_CB44 0x106c0000 0x106cffff SYSTEM_CFG.SMMU2_64KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.1

SMMU2_64KB_PAGESIZE_CB45 0x106d0000 0x106dffff SYSTEM_CFG.SMMU2_64KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.1

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Block Name Start Address End Address Address Locality

SMMU2_64KB_PAGESIZE_CB46 0x106e0000 0x106effff SYSTEM_CFG.SMMU2_64KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.1

SMMU2_64KB_PAGESIZE_CB47 0x106f0000 0x106fffff SYSTEM_CFG.SMMU2_64KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.1

SMMU2_64KB_PAGESIZE_CB48 0x10700000 0x1070ffff SYSTEM_CFG.SMMU2_64KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.1

SMMU2_64KB_PAGESIZE_CB49 0x10710000 0x1071ffff SYSTEM_CFG.SMMU2_64KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.1

SMMU2_64KB_PAGESIZE_CB50 0x10720000 0x1072ffff SYSTEM_CFG.SMMU2_64KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.1

SMMU2_64KB_PAGESIZE_CB51 0x10730000 0x1073ffff SYSTEM_CFG.SMMU2_64KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.1

SMMU2_64KB_PAGESIZE_CB52 0x10740000 0x1074ffff SYSTEM_CFG.SMMU2_64KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.1

SMMU2_64KB_PAGESIZE_CB53 0x10750000 0x1075ffff SYSTEM_CFG.SMMU2_64KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.1

SMMU2_64KB_PAGESIZE_CB54 0x10760000 0x1076ffff SYSTEM_CFG.SMMU2_64KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.1

SMMU2_64KB_PAGESIZE_CB55 0x10770000 0x1077ffff SYSTEM_CFG.SMMU2_64KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.1

SMMU2_64KB_PAGESIZE_CB56 0x10780000 0x1078ffff SYSTEM_CFG.SMMU2_64KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.1

SMMU2_64KB_PAGESIZE_CB57 0x10790000 0x1079ffff SYSTEM_CFG.SMMU2_64KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.1

SMMU2_64KB_PAGESIZE_CB58 0x107a0000 0x107affff SYSTEM_CFG.SMMU2_64KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.1

SMMU2_64KB_PAGESIZE_CB59 0x107b0000 0x107bffff SYSTEM_CFG.SMMU2_64KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.1

SMMU2_64KB_PAGESIZE_CB60 0x107c0000 0x107cffff SYSTEM_CFG.SMMU2_64KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.1

SMMU2_64KB_PAGESIZE_CB61 0x107d0000 0x107dffff SYSTEM_CFG.SMMU2_64KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.1

SMMU2_64KB_PAGESIZE_CB62 0x107e0000 0x107effff SYSTEM_CFG.SMMU2_64KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.1

SMMU2_64KB_PAGESIZE_CB63 0x107f0000 0x107fffff SYSTEM_CFG.SMMU2_64KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.1

SMMU1_64KB_PAGESIZE_GR0 0x11000000 0x1100ffff SYSTEM_CFG.SMMU1_64KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.1

SMMU1_4KB_PAGESIZE_GR0 0x11000000 0x11000fff SYSTEM_CFG.SMMU1_4KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.0

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Block Name Start Address End Address Address Locality

SMMU1_4KB_PAGESIZE_GR1 0x11001000 0x11001fff SYSTEM_CFG.SMMU1_4KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.0

SMMU1_4KB_PAGESIZE_GID 0x11002000 0x11002fff SYSTEM_CFG.SMMU1_4KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.0

SMMU1_4KB_PAGESIZE_PM 0x11003000 0x11003fff SYSTEM_CFG.SMMU1_4KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.0

SMMU1_64KB_PAGESIZE_GR1 0x11010000 0x1101ffff SYSTEM_CFG.SMMU1_64KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.1

SMMU1_64KB_PAGESIZE_GID 0x11020000 0x1102ffff SYSTEM_CFG.SMMU1_64KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.1

SMMU1_64KB_PAGESIZE_PM 0x11030000 0x1103ffff SYSTEM_CFG.SMMU1_64KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.1

SMMU1_4KB_PAGESIZE_CB0 0x11040000 0x11040fff SYSTEM_CFG.SMMU1_4KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.0

SMMU1_4KB_PAGESIZE_CB1 0x11041000 0x11041fff SYSTEM_CFG.SMMU1_4KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.0

SMMU1_4KB_PAGESIZE_CB2 0x11042000 0x11042fff SYSTEM_CFG.SMMU1_4KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.0

SMMU1_4KB_PAGESIZE_CB3 0x11043000 0x11043fff SYSTEM_CFG.SMMU1_4KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.0

SMMU1_4KB_PAGESIZE_CB4 0x11044000 0x11044fff SYSTEM_CFG.SMMU1_4KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.0

SMMU1_4KB_PAGESIZE_CB5 0x11045000 0x11045fff SYSTEM_CFG.SMMU1_4KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.0

SMMU1_4KB_PAGESIZE_CB6 0x11046000 0x11046fff SYSTEM_CFG.SMMU1_4KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.0

SMMU1_4KB_PAGESIZE_CB7 0x11047000 0x11047fff SYSTEM_CFG.SMMU1_4KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.0

SMMU1_4KB_PAGESIZE_CB8 0x11048000 0x11048fff SYSTEM_CFG.SMMU1_4KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.0

SMMU1_4KB_PAGESIZE_CB9 0x11049000 0x11049fff SYSTEM_CFG.SMMU1_4KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.0

SMMU1_4KB_PAGESIZE_CB10 0x1104a000 0x1104afff SYSTEM_CFG.SMMU1_4KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.0

SMMU1_4KB_PAGESIZE_CB11 0x1104b000 0x1104bfff SYSTEM_CFG.SMMU1_4KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.0

SMMU1_4KB_PAGESIZE_CB12 0x1104c000 0x1104cfff SYSTEM_CFG.SMMU1_4KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.0

SMMU1_4KB_PAGESIZE_CB13 0x1104d000 0x1104dfff SYSTEM_CFG.SMMU1_4KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.0

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Block Name Start Address End Address Address Locality

SMMU1_4KB_PAGESIZE_CB14 0x1104e000 0x1104efff SYSTEM_CFG.SMMU1_4KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.0

SMMU1_4KB_PAGESIZE_CB15 0x1104f000 0x1104ffff SYSTEM_CFG.SMMU1_4KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.0

SMMU1_4KB_PAGESIZE_CB16 0x11050000 0x11050fff SYSTEM_CFG.SMMU1_4KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.0

SMMU1_4KB_PAGESIZE_CB17 0x11051000 0x11051fff SYSTEM_CFG.SMMU1_4KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.0

SMMU1_4KB_PAGESIZE_CB18 0x11052000 0x11052fff SYSTEM_CFG.SMMU1_4KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.0

SMMU1_4KB_PAGESIZE_CB19 0x11053000 0x11053fff SYSTEM_CFG.SMMU1_4KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.0

SMMU1_4KB_PAGESIZE_CB20 0x11054000 0x11054fff SYSTEM_CFG.SMMU1_4KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.0

SMMU1_4KB_PAGESIZE_CB21 0x11055000 0x11055fff SYSTEM_CFG.SMMU1_4KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.0

SMMU1_4KB_PAGESIZE_CB22 0x11056000 0x11056fff SYSTEM_CFG.SMMU1_4KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.0

SMMU1_4KB_PAGESIZE_CB23 0x11057000 0x11057fff SYSTEM_CFG.SMMU1_4KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.0

SMMU1_4KB_PAGESIZE_CB24 0x11058000 0x11058fff SYSTEM_CFG.SMMU1_4KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.0

SMMU1_4KB_PAGESIZE_CB25 0x11059000 0x11059fff SYSTEM_CFG.SMMU1_4KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.0

SMMU1_4KB_PAGESIZE_CB26 0x1105a000 0x1105afff SYSTEM_CFG.SMMU1_4KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.0

SMMU1_4KB_PAGESIZE_CB27 0x1105b000 0x1105bfff SYSTEM_CFG.SMMU1_4KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.0

SMMU1_4KB_PAGESIZE_CB28 0x1105c000 0x1105cfff SYSTEM_CFG.SMMU1_4KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.0

SMMU1_4KB_PAGESIZE_CB29 0x1105d000 0x1105dfff SYSTEM_CFG.SMMU1_4KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.0

SMMU1_4KB_PAGESIZE_CB30 0x1105e000 0x1105efff SYSTEM_CFG.SMMU1_4KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.0

SMMU1_4KB_PAGESIZE_CB31 0x1105f000 0x1105ffff SYSTEM_CFG.SMMU1_4KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.0

SMMU1_4KB_PAGESIZE_CB32 0x11060000 0x11060fff SYSTEM_CFG.SMMU1_4KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.0

SMMU1_4KB_PAGESIZE_CB33 0x11061000 0x11061fff SYSTEM_CFG.SMMU1_4KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.0

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Block Name Start Address End Address Address Locality

SMMU1_4KB_PAGESIZE_CB34 0x11062000 0x11062fff SYSTEM_CFG.SMMU1_4KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.0

SMMU1_4KB_PAGESIZE_CB35 0x11063000 0x11063fff SYSTEM_CFG.SMMU1_4KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.0

SMMU1_4KB_PAGESIZE_CB36 0x11064000 0x11064fff SYSTEM_CFG.SMMU1_4KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.0

SMMU1_4KB_PAGESIZE_CB37 0x11065000 0x11065fff SYSTEM_CFG.SMMU1_4KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.0

SMMU1_4KB_PAGESIZE_CB38 0x11066000 0x11066fff SYSTEM_CFG.SMMU1_4KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.0

SMMU1_4KB_PAGESIZE_CB39 0x11067000 0x11067fff SYSTEM_CFG.SMMU1_4KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.0

SMMU1_4KB_PAGESIZE_CB40 0x11068000 0x11068fff SYSTEM_CFG.SMMU1_4KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.0

SMMU1_4KB_PAGESIZE_CB41 0x11069000 0x11069fff SYSTEM_CFG.SMMU1_4KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.0

SMMU1_4KB_PAGESIZE_CB42 0x1106a000 0x1106afff SYSTEM_CFG.SMMU1_4KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.0

SMMU1_4KB_PAGESIZE_CB43 0x1106b000 0x1106bfff SYSTEM_CFG.SMMU1_4KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.0

SMMU1_4KB_PAGESIZE_CB44 0x1106c000 0x1106cfff SYSTEM_CFG.SMMU1_4KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.0

SMMU1_4KB_PAGESIZE_CB45 0x1106d000 0x1106dfff SYSTEM_CFG.SMMU1_4KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.0

SMMU1_4KB_PAGESIZE_CB46 0x1106e000 0x1106efff SYSTEM_CFG.SMMU1_4KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.0

SMMU1_4KB_PAGESIZE_CB47 0x1106f000 0x1106ffff SYSTEM_CFG.SMMU1_4KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.0

SMMU1_4KB_PAGESIZE_CB48 0x11070000 0x11070fff SYSTEM_CFG.SMMU1_4KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.0

SMMU1_4KB_PAGESIZE_CB49 0x11071000 0x11071fff SYSTEM_CFG.SMMU1_4KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.0

SMMU1_4KB_PAGESIZE_CB50 0x11072000 0x11072fff SYSTEM_CFG.SMMU1_4KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.0

SMMU1_4KB_PAGESIZE_CB51 0x11073000 0x11073fff SYSTEM_CFG.SMMU1_4KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.0

SMMU1_4KB_PAGESIZE_CB52 0x11074000 0x11074fff SYSTEM_CFG.SMMU1_4KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.0

SMMU1_4KB_PAGESIZE_CB53 0x11075000 0x11075fff SYSTEM_CFG.SMMU1_4KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.0

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Block Name Start Address End Address Address Locality

SMMU1_4KB_PAGESIZE_CB54 0x11076000 0x11076fff SYSTEM_CFG.SMMU1_4KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.0

SMMU1_4KB_PAGESIZE_CB55 0x11077000 0x11077fff SYSTEM_CFG.SMMU1_4KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.0

SMMU1_4KB_PAGESIZE_CB56 0x11078000 0x11078fff SYSTEM_CFG.SMMU1_4KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.0

SMMU1_4KB_PAGESIZE_CB57 0x11079000 0x11079fff SYSTEM_CFG.SMMU1_4KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.0

SMMU1_4KB_PAGESIZE_CB58 0x1107a000 0x1107afff SYSTEM_CFG.SMMU1_4KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.0

SMMU1_4KB_PAGESIZE_CB59 0x1107b000 0x1107bfff SYSTEM_CFG.SMMU1_4KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.0

SMMU1_4KB_PAGESIZE_CB60 0x1107c000 0x1107cfff SYSTEM_CFG.SMMU1_4KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.0

SMMU1_4KB_PAGESIZE_CB61 0x1107d000 0x1107dfff SYSTEM_CFG.SMMU1_4KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.0

SMMU1_4KB_PAGESIZE_CB62 0x1107e000 0x1107efff SYSTEM_CFG.SMMU1_4KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.0

SMMU1_4KB_PAGESIZE_CB63 0x1107f000 0x1107ffff SYSTEM_CFG.SMMU1_4KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.0

SMMU1_64KB_PAGESIZE_CB0 0x11400000 0x1140ffff SYSTEM_CFG.SMMU1_64KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.1

SMMU1_64KB_PAGESIZE_CB1 0x11410000 0x1141ffff SYSTEM_CFG.SMMU1_64KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.1

SMMU1_64KB_PAGESIZE_CB2 0x11420000 0x1142ffff SYSTEM_CFG.SMMU1_64KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.1

SMMU1_64KB_PAGESIZE_CB3 0x11430000 0x1143ffff SYSTEM_CFG.SMMU1_64KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.1

SMMU1_64KB_PAGESIZE_CB4 0x11440000 0x1144ffff SYSTEM_CFG.SMMU1_64KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.1

SMMU1_64KB_PAGESIZE_CB5 0x11450000 0x1145ffff SYSTEM_CFG.SMMU1_64KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.1

SMMU1_64KB_PAGESIZE_CB6 0x11460000 0x1146ffff SYSTEM_CFG.SMMU1_64KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.1

SMMU1_64KB_PAGESIZE_CB7 0x11470000 0x1147ffff SYSTEM_CFG.SMMU1_64KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.1

SMMU1_64KB_PAGESIZE_CB8 0x11480000 0x1148ffff SYSTEM_CFG.SMMU1_64KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.1

SMMU1_64KB_PAGESIZE_CB9 0x11490000 0x1149ffff SYSTEM_CFG.SMMU1_64KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.1

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Block Name Start Address End Address Address Locality

SMMU1_64KB_PAGESIZE_CB10 0x114a0000 0x114affff SYSTEM_CFG.SMMU1_64KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.1

SMMU1_64KB_PAGESIZE_CB11 0x114b0000 0x114bffff SYSTEM_CFG.SMMU1_64KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.1

SMMU1_64KB_PAGESIZE_CB12 0x114c0000 0x114cffff SYSTEM_CFG.SMMU1_64KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.1

SMMU1_64KB_PAGESIZE_CB13 0x114d0000 0x114dffff SYSTEM_CFG.SMMU1_64KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.1

SMMU1_64KB_PAGESIZE_CB14 0x114e0000 0x114effff SYSTEM_CFG.SMMU1_64KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.1

SMMU1_64KB_PAGESIZE_CB15 0x114f0000 0x114fffff SYSTEM_CFG.SMMU1_64KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.1

SMMU1_64KB_PAGESIZE_CB16 0x11500000 0x1150ffff SYSTEM_CFG.SMMU1_64KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.1

SMMU1_64KB_PAGESIZE_CB17 0x11510000 0x1151ffff SYSTEM_CFG.SMMU1_64KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.1

SMMU1_64KB_PAGESIZE_CB18 0x11520000 0x1152ffff SYSTEM_CFG.SMMU1_64KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.1

SMMU1_64KB_PAGESIZE_CB19 0x11530000 0x1153ffff SYSTEM_CFG.SMMU1_64KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.1

SMMU1_64KB_PAGESIZE_CB20 0x11540000 0x1154ffff SYSTEM_CFG.SMMU1_64KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.1

SMMU1_64KB_PAGESIZE_CB21 0x11550000 0x1155ffff SYSTEM_CFG.SMMU1_64KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.1

SMMU1_64KB_PAGESIZE_CB22 0x11560000 0x1156ffff SYSTEM_CFG.SMMU1_64KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.1

SMMU1_64KB_PAGESIZE_CB23 0x11570000 0x1157ffff SYSTEM_CFG.SMMU1_64KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.1

SMMU1_64KB_PAGESIZE_CB24 0x11580000 0x1158ffff SYSTEM_CFG.SMMU1_64KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.1

SMMU1_64KB_PAGESIZE_CB25 0x11590000 0x1159ffff SYSTEM_CFG.SMMU1_64KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.1

SMMU1_64KB_PAGESIZE_CB26 0x115a0000 0x115affff SYSTEM_CFG.SMMU1_64KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.1

SMMU1_64KB_PAGESIZE_CB27 0x115b0000 0x115bffff SYSTEM_CFG.SMMU1_64KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.1

SMMU1_64KB_PAGESIZE_CB28 0x115c0000 0x115cffff SYSTEM_CFG.SMMU1_64KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.1

SMMU1_64KB_PAGESIZE_CB29 0x115d0000 0x115dffff SYSTEM_CFG.SMMU1_64KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.1

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Block Name Start Address End Address Address Locality

SMMU1_64KB_PAGESIZE_CB30 0x115e0000 0x115effff SYSTEM_CFG.SMMU1_64KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.1

SMMU1_64KB_PAGESIZE_CB31 0x115f0000 0x115fffff SYSTEM_CFG.SMMU1_64KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.1

SMMU1_64KB_PAGESIZE_CB32 0x11600000 0x1160ffff SYSTEM_CFG.SMMU1_64KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.1

SMMU1_64KB_PAGESIZE_CB33 0x11610000 0x1161ffff SYSTEM_CFG.SMMU1_64KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.1

SMMU1_64KB_PAGESIZE_CB34 0x11620000 0x1162ffff SYSTEM_CFG.SMMU1_64KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.1

SMMU1_64KB_PAGESIZE_CB35 0x11630000 0x1163ffff SYSTEM_CFG.SMMU1_64KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.1

SMMU1_64KB_PAGESIZE_CB36 0x11640000 0x1164ffff SYSTEM_CFG.SMMU1_64KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.1

SMMU1_64KB_PAGESIZE_CB37 0x11650000 0x1165ffff SYSTEM_CFG.SMMU1_64KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.1

SMMU1_64KB_PAGESIZE_CB38 0x11660000 0x1166ffff SYSTEM_CFG.SMMU1_64KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.1

SMMU1_64KB_PAGESIZE_CB39 0x11670000 0x1167ffff SYSTEM_CFG.SMMU1_64KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.1

SMMU1_64KB_PAGESIZE_CB40 0x11680000 0x1168ffff SYSTEM_CFG.SMMU1_64KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.1

SMMU1_64KB_PAGESIZE_CB41 0x11690000 0x1169ffff SYSTEM_CFG.SMMU1_64KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.1

SMMU1_64KB_PAGESIZE_CB42 0x116a0000 0x116affff SYSTEM_CFG.SMMU1_64KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.1

SMMU1_64KB_PAGESIZE_CB43 0x116b0000 0x116bffff SYSTEM_CFG.SMMU1_64KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.1

SMMU1_64KB_PAGESIZE_CB44 0x116c0000 0x116cffff SYSTEM_CFG.SMMU1_64KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.1

SMMU1_64KB_PAGESIZE_CB45 0x116d0000 0x116dffff SYSTEM_CFG.SMMU1_64KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.1

SMMU1_64KB_PAGESIZE_CB46 0x116e0000 0x116effff SYSTEM_CFG.SMMU1_64KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.1

SMMU1_64KB_PAGESIZE_CB47 0x116f0000 0x116fffff SYSTEM_CFG.SMMU1_64KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.1

SMMU1_64KB_PAGESIZE_CB48 0x11700000 0x1170ffff SYSTEM_CFG.SMMU1_64KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.1

SMMU1_64KB_PAGESIZE_CB49 0x11710000 0x1171ffff SYSTEM_CFG.SMMU1_64KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.1

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Block Name Start Address End Address Address Locality

SMMU1_64KB_PAGESIZE_CB50 0x11720000 0x1172ffff SYSTEM_CFG.SMMU1_64KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.1

SMMU1_64KB_PAGESIZE_CB51 0x11730000 0x1173ffff SYSTEM_CFG.SMMU1_64KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.1

SMMU1_64KB_PAGESIZE_CB52 0x11740000 0x1174ffff SYSTEM_CFG.SMMU1_64KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.1

SMMU1_64KB_PAGESIZE_CB53 0x11750000 0x1175ffff SYSTEM_CFG.SMMU1_64KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.1

SMMU1_64KB_PAGESIZE_CB54 0x11760000 0x1176ffff SYSTEM_CFG.SMMU1_64KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.1

SMMU1_64KB_PAGESIZE_CB55 0x11770000 0x1177ffff SYSTEM_CFG.SMMU1_64KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.1

SMMU1_64KB_PAGESIZE_CB56 0x11780000 0x1178ffff SYSTEM_CFG.SMMU1_64KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.1

SMMU1_64KB_PAGESIZE_CB57 0x11790000 0x1179ffff SYSTEM_CFG.SMMU1_64KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.1

SMMU1_64KB_PAGESIZE_CB58 0x117a0000 0x117affff SYSTEM_CFG.SMMU1_64KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.1

SMMU1_64KB_PAGESIZE_CB59 0x117b0000 0x117bffff SYSTEM_CFG.SMMU1_64KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.1

SMMU1_64KB_PAGESIZE_CB60 0x117c0000 0x117cffff SYSTEM_CFG.SMMU1_64KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.1

SMMU1_64KB_PAGESIZE_CB61 0x117d0000 0x117dffff SYSTEM_CFG.SMMU1_64KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.1

SMMU1_64KB_PAGESIZE_CB62 0x117e0000 0x117effff SYSTEM_CFG.SMMU1_64KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.1

SMMU1_64KB_PAGESIZE_CB63 0x117f0000 0x117fffff SYSTEM_CFG.SMMU1_64KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.1

SMMU0_64KB_PAGESIZE_GR0 0x12000000 0x1200ffff SYSTEM_CFG.SMMU0_64KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.1

SMMU0_4KB_PAGESIZE_GR0 0x12000000 0x12000fff SYSTEM_CFG.SMMU0_4KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.0

SMMU0_4KB_PAGESIZE_GR1 0x12001000 0x12001fff SYSTEM_CFG.SMMU0_4KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.0

SMMU0_4KB_PAGESIZE_GID 0x12002000 0x12002fff SYSTEM_CFG.SMMU0_4KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.0

SMMU0_4KB_PAGESIZE_PM 0x12003000 0x12003fff SYSTEM_CFG.SMMU0_4KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.0

SMMU0_64KB_PAGESIZE_GR1 0x12010000 0x1201ffff SYSTEM_CFG.SMMU0_64KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.1

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Block Name Start Address End Address Address Locality

SMMU0_64KB_PAGESIZE_GID 0x12020000 0x1202ffff SYSTEM_CFG.SMMU0_64KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.1

SMMU0_64KB_PAGESIZE_PM 0x12030000 0x1203ffff SYSTEM_CFG.SMMU0_64KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.1

SMMU0_4KB_PAGESIZE_CB0 0x12040000 0x12040fff SYSTEM_CFG.SMMU0_4KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.0

SMMU0_4KB_PAGESIZE_CB1 0x12041000 0x12041fff SYSTEM_CFG.SMMU0_4KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.0

SMMU0_4KB_PAGESIZE_CB2 0x12042000 0x12042fff SYSTEM_CFG.SMMU0_4KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.0

SMMU0_4KB_PAGESIZE_CB3 0x12043000 0x12043fff SYSTEM_CFG.SMMU0_4KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.0

SMMU0_4KB_PAGESIZE_CB4 0x12044000 0x12044fff SYSTEM_CFG.SMMU0_4KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.0

SMMU0_4KB_PAGESIZE_CB5 0x12045000 0x12045fff SYSTEM_CFG.SMMU0_4KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.0

SMMU0_4KB_PAGESIZE_CB6 0x12046000 0x12046fff SYSTEM_CFG.SMMU0_4KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.0

SMMU0_4KB_PAGESIZE_CB7 0x12047000 0x12047fff SYSTEM_CFG.SMMU0_4KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.0

SMMU0_4KB_PAGESIZE_CB8 0x12048000 0x12048fff SYSTEM_CFG.SMMU0_4KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.0

SMMU0_4KB_PAGESIZE_CB9 0x12049000 0x12049fff SYSTEM_CFG.SMMU0_4KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.0

SMMU0_4KB_PAGESIZE_CB10 0x1204a000 0x1204afff SYSTEM_CFG.SMMU0_4KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.0

SMMU0_4KB_PAGESIZE_CB11 0x1204b000 0x1204bfff SYSTEM_CFG.SMMU0_4KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.0

SMMU0_4KB_PAGESIZE_CB12 0x1204c000 0x1204cfff SYSTEM_CFG.SMMU0_4KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.0

SMMU0_4KB_PAGESIZE_CB13 0x1204d000 0x1204dfff SYSTEM_CFG.SMMU0_4KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.0

SMMU0_4KB_PAGESIZE_CB14 0x1204e000 0x1204efff SYSTEM_CFG.SMMU0_4KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.0

SMMU0_4KB_PAGESIZE_CB15 0x1204f000 0x1204ffff SYSTEM_CFG.SMMU0_4KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.0

SMMU0_4KB_PAGESIZE_CB16 0x12050000 0x12050fff SYSTEM_CFG.SMMU0_4KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.0

SMMU0_4KB_PAGESIZE_CB17 0x12051000 0x12051fff SYSTEM_CFG.SMMU0_4KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.0

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Block Name Start Address End Address Address Locality

SMMU0_4KB_PAGESIZE_CB18 0x12052000 0x12052fff SYSTEM_CFG.SMMU0_4KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.0

SMMU0_4KB_PAGESIZE_CB19 0x12053000 0x12053fff SYSTEM_CFG.SMMU0_4KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.0

SMMU0_4KB_PAGESIZE_CB20 0x12054000 0x12054fff SYSTEM_CFG.SMMU0_4KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.0

SMMU0_4KB_PAGESIZE_CB21 0x12055000 0x12055fff SYSTEM_CFG.SMMU0_4KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.0

SMMU0_4KB_PAGESIZE_CB22 0x12056000 0x12056fff SYSTEM_CFG.SMMU0_4KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.0

SMMU0_4KB_PAGESIZE_CB23 0x12057000 0x12057fff SYSTEM_CFG.SMMU0_4KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.0

SMMU0_4KB_PAGESIZE_CB24 0x12058000 0x12058fff SYSTEM_CFG.SMMU0_4KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.0

SMMU0_4KB_PAGESIZE_CB25 0x12059000 0x12059fff SYSTEM_CFG.SMMU0_4KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.0

SMMU0_4KB_PAGESIZE_CB26 0x1205a000 0x1205afff SYSTEM_CFG.SMMU0_4KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.0

SMMU0_4KB_PAGESIZE_CB27 0x1205b000 0x1205bfff SYSTEM_CFG.SMMU0_4KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.0

SMMU0_4KB_PAGESIZE_CB28 0x1205c000 0x1205cfff SYSTEM_CFG.SMMU0_4KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.0

SMMU0_4KB_PAGESIZE_CB29 0x1205d000 0x1205dfff SYSTEM_CFG.SMMU0_4KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.0

SMMU0_4KB_PAGESIZE_CB30 0x1205e000 0x1205efff SYSTEM_CFG.SMMU0_4KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.0

SMMU0_4KB_PAGESIZE_CB31 0x1205f000 0x1205ffff SYSTEM_CFG.SMMU0_4KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.0

SMMU0_4KB_PAGESIZE_CB32 0x12060000 0x12060fff SYSTEM_CFG.SMMU0_4KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.0

SMMU0_4KB_PAGESIZE_CB33 0x12061000 0x12061fff SYSTEM_CFG.SMMU0_4KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.0

SMMU0_4KB_PAGESIZE_CB34 0x12062000 0x12062fff SYSTEM_CFG.SMMU0_4KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.0

SMMU0_4KB_PAGESIZE_CB35 0x12063000 0x12063fff SYSTEM_CFG.SMMU0_4KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.0

SMMU0_4KB_PAGESIZE_CB36 0x12064000 0x12064fff SYSTEM_CFG.SMMU0_4KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.0

SMMU0_4KB_PAGESIZE_CB37 0x12065000 0x12065fff SYSTEM_CFG.SMMU0_4KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.0

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Block Name Start Address End Address Address Locality

SMMU0_4KB_PAGESIZE_CB38 0x12066000 0x12066fff SYSTEM_CFG.SMMU0_4KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.0

SMMU0_4KB_PAGESIZE_CB39 0x12067000 0x12067fff SYSTEM_CFG.SMMU0_4KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.0

SMMU0_4KB_PAGESIZE_CB40 0x12068000 0x12068fff SYSTEM_CFG.SMMU0_4KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.0

SMMU0_4KB_PAGESIZE_CB41 0x12069000 0x12069fff SYSTEM_CFG.SMMU0_4KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.0

SMMU0_4KB_PAGESIZE_CB42 0x1206a000 0x1206afff SYSTEM_CFG.SMMU0_4KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.0

SMMU0_4KB_PAGESIZE_CB43 0x1206b000 0x1206bfff SYSTEM_CFG.SMMU0_4KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.0

SMMU0_4KB_PAGESIZE_CB44 0x1206c000 0x1206cfff SYSTEM_CFG.SMMU0_4KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.0

SMMU0_4KB_PAGESIZE_CB45 0x1206d000 0x1206dfff SYSTEM_CFG.SMMU0_4KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.0

SMMU0_4KB_PAGESIZE_CB46 0x1206e000 0x1206efff SYSTEM_CFG.SMMU0_4KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.0

SMMU0_4KB_PAGESIZE_CB47 0x1206f000 0x1206ffff SYSTEM_CFG.SMMU0_4KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.0

SMMU0_4KB_PAGESIZE_CB48 0x12070000 0x12070fff SYSTEM_CFG.SMMU0_4KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.0

SMMU0_4KB_PAGESIZE_CB49 0x12071000 0x12071fff SYSTEM_CFG.SMMU0_4KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.0

SMMU0_4KB_PAGESIZE_CB50 0x12072000 0x12072fff SYSTEM_CFG.SMMU0_4KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.0

SMMU0_4KB_PAGESIZE_CB51 0x12073000 0x12073fff SYSTEM_CFG.SMMU0_4KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.0

SMMU0_4KB_PAGESIZE_CB52 0x12074000 0x12074fff SYSTEM_CFG.SMMU0_4KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.0

SMMU0_4KB_PAGESIZE_CB53 0x12075000 0x12075fff SYSTEM_CFG.SMMU0_4KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.0

SMMU0_4KB_PAGESIZE_CB54 0x12076000 0x12076fff SYSTEM_CFG.SMMU0_4KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.0

SMMU0_4KB_PAGESIZE_CB55 0x12077000 0x12077fff SYSTEM_CFG.SMMU0_4KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.0

SMMU0_4KB_PAGESIZE_CB56 0x12078000 0x12078fff SYSTEM_CFG.SMMU0_4KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.0

SMMU0_4KB_PAGESIZE_CB57 0x12079000 0x12079fff SYSTEM_CFG.SMMU0_4KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.0

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Block Name Start Address End Address Address Locality

SMMU0_4KB_PAGESIZE_CB58 0x1207a000 0x1207afff SYSTEM_CFG.SMMU0_4KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.0

SMMU0_4KB_PAGESIZE_CB59 0x1207b000 0x1207bfff SYSTEM_CFG.SMMU0_4KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.0

SMMU0_4KB_PAGESIZE_CB60 0x1207c000 0x1207cfff SYSTEM_CFG.SMMU0_4KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.0

SMMU0_4KB_PAGESIZE_CB61 0x1207d000 0x1207dfff SYSTEM_CFG.SMMU0_4KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.0

SMMU0_4KB_PAGESIZE_CB62 0x1207e000 0x1207efff SYSTEM_CFG.SMMU0_4KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.0

SMMU0_4KB_PAGESIZE_CB63 0x1207f000 0x1207ffff SYSTEM_CFG.SMMU0_4KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.0

SMMU0_64KB_PAGESIZE_CB0 0x12400000 0x1240ffff SYSTEM_CFG.SMMU0_64KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.1

SMMU0_64KB_PAGESIZE_CB1 0x12410000 0x1241ffff SYSTEM_CFG.SMMU0_64KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.1

SMMU0_64KB_PAGESIZE_CB2 0x12420000 0x1242ffff SYSTEM_CFG.SMMU0_64KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.1

SMMU0_64KB_PAGESIZE_CB3 0x12430000 0x1243ffff SYSTEM_CFG.SMMU0_64KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.1

SMMU0_64KB_PAGESIZE_CB4 0x12440000 0x1244ffff SYSTEM_CFG.SMMU0_64KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.1

SMMU0_64KB_PAGESIZE_CB5 0x12450000 0x1245ffff SYSTEM_CFG.SMMU0_64KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.1

SMMU0_64KB_PAGESIZE_CB6 0x12460000 0x1246ffff SYSTEM_CFG.SMMU0_64KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.1

SMMU0_64KB_PAGESIZE_CB7 0x12470000 0x1247ffff SYSTEM_CFG.SMMU0_64KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.1

SMMU0_64KB_PAGESIZE_CB8 0x12480000 0x1248ffff SYSTEM_CFG.SMMU0_64KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.1

SMMU0_64KB_PAGESIZE_CB9 0x12490000 0x1249ffff SYSTEM_CFG.SMMU0_64KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.1

SMMU0_64KB_PAGESIZE_CB10 0x124a0000 0x124affff SYSTEM_CFG.SMMU0_64KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.1

SMMU0_64KB_PAGESIZE_CB11 0x124b0000 0x124bffff SYSTEM_CFG.SMMU0_64KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.1

SMMU0_64KB_PAGESIZE_CB12 0x124c0000 0x124cffff SYSTEM_CFG.SMMU0_64KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.1

SMMU0_64KB_PAGESIZE_CB13 0x124d0000 0x124dffff SYSTEM_CFG.SMMU0_64KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.1

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Block Name Start Address End Address Address Locality

SMMU0_64KB_PAGESIZE_CB14 0x124e0000 0x124effff SYSTEM_CFG.SMMU0_64KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.1

SMMU0_64KB_PAGESIZE_CB15 0x124f0000 0x124fffff SYSTEM_CFG.SMMU0_64KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.1

SMMU0_64KB_PAGESIZE_CB16 0x12500000 0x1250ffff SYSTEM_CFG.SMMU0_64KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.1

SMMU0_64KB_PAGESIZE_CB17 0x12510000 0x1251ffff SYSTEM_CFG.SMMU0_64KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.1

SMMU0_64KB_PAGESIZE_CB18 0x12520000 0x1252ffff SYSTEM_CFG.SMMU0_64KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.1

SMMU0_64KB_PAGESIZE_CB19 0x12530000 0x1253ffff SYSTEM_CFG.SMMU0_64KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.1

SMMU0_64KB_PAGESIZE_CB20 0x12540000 0x1254ffff SYSTEM_CFG.SMMU0_64KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.1

SMMU0_64KB_PAGESIZE_CB21 0x12550000 0x1255ffff SYSTEM_CFG.SMMU0_64KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.1

SMMU0_64KB_PAGESIZE_CB22 0x12560000 0x1256ffff SYSTEM_CFG.SMMU0_64KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.1

SMMU0_64KB_PAGESIZE_CB23 0x12570000 0x1257ffff SYSTEM_CFG.SMMU0_64KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.1

SMMU0_64KB_PAGESIZE_CB24 0x12580000 0x1258ffff SYSTEM_CFG.SMMU0_64KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.1

SMMU0_64KB_PAGESIZE_CB25 0x12590000 0x1259ffff SYSTEM_CFG.SMMU0_64KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.1

SMMU0_64KB_PAGESIZE_CB26 0x125a0000 0x125affff SYSTEM_CFG.SMMU0_64KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.1

SMMU0_64KB_PAGESIZE_CB27 0x125b0000 0x125bffff SYSTEM_CFG.SMMU0_64KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.1

SMMU0_64KB_PAGESIZE_CB28 0x125c0000 0x125cffff SYSTEM_CFG.SMMU0_64KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.1

SMMU0_64KB_PAGESIZE_CB29 0x125d0000 0x125dffff SYSTEM_CFG.SMMU0_64KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.1

SMMU0_64KB_PAGESIZE_CB30 0x125e0000 0x125effff SYSTEM_CFG.SMMU0_64KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.1

SMMU0_64KB_PAGESIZE_CB31 0x125f0000 0x125fffff SYSTEM_CFG.SMMU0_64KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.1

SMMU0_64KB_PAGESIZE_CB32 0x12600000 0x1260ffff SYSTEM_CFG.SMMU0_64KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.1

SMMU0_64KB_PAGESIZE_CB33 0x12610000 0x1261ffff SYSTEM_CFG.SMMU0_64KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.1

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Block Name Start Address End Address Address Locality

SMMU0_64KB_PAGESIZE_CB34 0x12620000 0x1262ffff SYSTEM_CFG.SMMU0_64KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.1

SMMU0_64KB_PAGESIZE_CB35 0x12630000 0x1263ffff SYSTEM_CFG.SMMU0_64KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.1

SMMU0_64KB_PAGESIZE_CB36 0x12640000 0x1264ffff SYSTEM_CFG.SMMU0_64KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.1

SMMU0_64KB_PAGESIZE_CB37 0x12650000 0x1265ffff SYSTEM_CFG.SMMU0_64KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.1

SMMU0_64KB_PAGESIZE_CB38 0x12660000 0x1266ffff SYSTEM_CFG.SMMU0_64KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.1

SMMU0_64KB_PAGESIZE_CB39 0x12670000 0x1267ffff SYSTEM_CFG.SMMU0_64KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.1

SMMU0_64KB_PAGESIZE_CB40 0x12680000 0x1268ffff SYSTEM_CFG.SMMU0_64KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.1

SMMU0_64KB_PAGESIZE_CB41 0x12690000 0x1269ffff SYSTEM_CFG.SMMU0_64KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.1

SMMU0_64KB_PAGESIZE_CB42 0x126a0000 0x126affff SYSTEM_CFG.SMMU0_64KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.1

SMMU0_64KB_PAGESIZE_CB43 0x126b0000 0x126bffff SYSTEM_CFG.SMMU0_64KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.1

SMMU0_64KB_PAGESIZE_CB44 0x126c0000 0x126cffff SYSTEM_CFG.SMMU0_64KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.1

SMMU0_64KB_PAGESIZE_CB45 0x126d0000 0x126dffff SYSTEM_CFG.SMMU0_64KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.1

SMMU0_64KB_PAGESIZE_CB46 0x126e0000 0x126effff SYSTEM_CFG.SMMU0_64KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.1

SMMU0_64KB_PAGESIZE_CB47 0x126f0000 0x126fffff SYSTEM_CFG.SMMU0_64KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.1

SMMU0_64KB_PAGESIZE_CB48 0x12700000 0x1270ffff SYSTEM_CFG.SMMU0_64KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.1

SMMU0_64KB_PAGESIZE_CB49 0x12710000 0x1271ffff SYSTEM_CFG.SMMU0_64KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.1

SMMU0_64KB_PAGESIZE_CB50 0x12720000 0x1272ffff SYSTEM_CFG.SMMU0_64KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.1

SMMU0_64KB_PAGESIZE_CB51 0x12730000 0x1273ffff SYSTEM_CFG.SMMU0_64KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.1

SMMU0_64KB_PAGESIZE_CB52 0x12740000 0x1274ffff SYSTEM_CFG.SMMU0_64KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.1

SMMU0_64KB_PAGESIZE_CB53 0x12750000 0x1275ffff SYSTEM_CFG.SMMU0_64KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.1

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Block Name Start Address End Address Address Locality

SMMU0_64KB_PAGESIZE_CB54 0x12760000 0x1276ffff SYSTEM_CFG.SMMU0_64KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.1

SMMU0_64KB_PAGESIZE_CB55 0x12770000 0x1277ffff SYSTEM_CFG.SMMU0_64KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.1

SMMU0_64KB_PAGESIZE_CB56 0x12780000 0x1278ffff SYSTEM_CFG.SMMU0_64KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.1

SMMU0_64KB_PAGESIZE_CB57 0x12790000 0x1279ffff SYSTEM_CFG.SMMU0_64KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.1

SMMU0_64KB_PAGESIZE_CB58 0x127a0000 0x127affff SYSTEM_CFG.SMMU0_64KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.1

SMMU0_64KB_PAGESIZE_CB59 0x127b0000 0x127bffff SYSTEM_CFG.SMMU0_64KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.1

SMMU0_64KB_PAGESIZE_CB60 0x127c0000 0x127cffff SYSTEM_CFG.SMMU0_64KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.1

SMMU0_64KB_PAGESIZE_CB61 0x127d0000 0x127dffff SYSTEM_CFG.SMMU0_64KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.1

SMMU0_64KB_PAGESIZE_CB62 0x127e0000 0x127effff SYSTEM_CFG.SMMU0_64KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.1

SMMU0_64KB_PAGESIZE_CB63 0x127f0000 0x127fffff SYSTEM_CFG.SMMU0_64KB_PAGESIZE_GR0.

ARM_SMMU_GSR0_SACR_0.PAGESIZE.1

CBB_ERR_COLLATOR_0 0x13000000 0x1300ffff SYSTEM

CBB_ERR_COLLATOR_1 0x13010000 0x1301ffff SYSTEM

CBB_ERR_COLLATOR_2 0x13020000 0x1302ffff SYSTEM

CBB_ERR_COLLATOR_3 0x13030000 0x1303ffff SYSTEM

CBB_ERR_COLLATOR_4 0x13040000 0x1304ffff SYSTEM

CBB_ERR_COLLATOR_5 0x13050000 0x1305ffff SYSTEM

CBB_ERR_COLLATOR_6 0x13060000 0x1306ffff SYSTEM

CBB_ERR_COLLATOR_7 0x13070000 0x1307ffff SYSTEM

CBB_ERR_COLLATOR_8 0x13080000 0x1308ffff SYSTEM

CBB_ERR_COLLATOR_9 0x13090000 0x1309ffff SYSTEM

CBB_ERR_COLLATOR_10 0x130a0000 0x130affff SYSTEM

CBB_ERR_COLLATOR_11 0x130b0000 0x130bffff SYSTEM

CBB_ERR_COLLATOR_12 0x130c0000 0x130cffff SYSTEM

CBB_ERR_COLLATOR_13 0x130d0000 0x130dffff SYSTEM

CBB_ERR_COLLATOR_14 0x130e0000 0x130effff SYSTEM

CBB_ERR_COLLATOR_15 0x130f0000 0x130fffff SYSTEM

CBB_ERR_COLLATOR_16 0x13100000 0x1310ffff SYSTEM

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Block Name Start Address End Address Address Locality

CBB_ERR_COLLATOR_17 0x13110000 0x1311ffff SYSTEM

CBB_ERR_COLLATOR_18 0x13120000 0x1312ffff SYSTEM

CBB_ERR_COLLATOR_19 0x13130000 0x1313ffff SYSTEM

HOST1X_COMMON 0x13e00000 0x13e0ffff SYSTEM

HOST1X_0 0x13e10000 0x13e1ffff SYSTEM

HOST1X_1 0x13e20000 0x13e2ffff SYSTEM

HOST1X_2 0x13e30000 0x13e3ffff SYSTEM

HOST1X_3 0x13e40000 0x13e4ffff SYSTEM

HOST1X_4 0x13e50000 0x13e5ffff SYSTEM

HOST1X_5 0x13e60000 0x13e6ffff SYSTEM

HOST1X_6 0x13e70000 0x13e7ffff SYSTEM

HOST1X_7 0x13e80000 0x13e8ffff SYSTEM

HOST1X_ACTMON0 0x13ec0000 0x13ecffff SYSTEM

HOST1X_ACTMON1 0x13ed0000 0x13edffff SYSTEM

HOST1X_ACTMON2 0x13ee0000 0x13eeffff SYSTEM

HOST1X_ACTMON3 0x13ef0000 0x13efffff SYSTEM

HOST1X_ACTMON4 0x13f00000 0x13f0ffff SYSTEM

HOST1X_ACTMON5 0x13f10000 0x13f1ffff SYSTEM

PCIE_C1_CTL 0x14100000 0x1411ffff SYSTEM

PCIE_C2_CTL 0x14120000 0x1413ffff SYSTEM

PCIE_C3_CTL 0x14140000 0x1415ffff SYSTEM

PCIE_C4_CTL 0x14160000 0x1417ffff SYSTEM

PCIE_C0_CTL 0x14180000 0x1419ffff SYSTEM

PCIE_C5_CTL 0x141a0000 0x141bffff SYSTEM

DISPLAY 0x15200000 0x1520ffff SYSTEM

DISPLAYB 0x15210000 0x1521ffff SYSTEM

DISPLAYC 0x15220000 0x1522ffff SYSTEM

DISPLAYD 0x15230000 0x1523ffff SYSTEM

VIC 0x15340000 0x1537ffff SYSTEM

DPAUX 0x155c0000 0x155cffff SYSTEM

DPAUX1 0x155d0000 0x155dffff SYSTEM

DPAUX2 0x155e0000 0x155effff SYSTEM

DPAUX3 0x155f0000 0x155fffff SYSTEM

NVCSI 0x15a00000 0x15a4ffff SYSTEM

SLVSEC 0x15ac0000 0x15afffff SYSTEM

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Block Name Start Address End Address Address Locality

SOR 0x15b00000 0x15b3ffff SYSTEM

SOR1 0x15b40000 0x15b7ffff SYSTEM

SOR2 0x15b80000 0x15bbffff SYSTEM

SOR3 0x15bc0000 0x15bfffff SYSTEM

VI 0x15c00000 0x15efffff SYSTEM

VI_THI 0x15f00000 0x15ffffff SYSTEM

STM 0x22000000 0x22ffffff SYSTEM

PCIE_C1_32BIT_RP 0x30000000 0x30001fff SYSTEM

PCIE_C1_32BIT_DMA 0x30040000 0x3007ffff SYSTEM

PCIE_C2_32BIT_RP 0x32000000 0x32001fff SYSTEM

PCIE_C2_32BIT_DMA 0x32040000 0x3207ffff SYSTEM

PCIE_C3_32BIT_RP 0x34000000 0x34001fff SYSTEM

PCIE_C3_32BIT_DMA 0x34040000 0x3407ffff SYSTEM

PCIE_C4_32BIT_EP 0x36000000 0x36001fff SYSTEM_CFG.PCIE_C4_CTL.

PCIE_RP_APPL_DM_TYPE_0.DEVICE_TYPE.

END_POINT

PCIE_C4_32BIT_RP 0x36000000 0x36001fff SYSTEM_CFG.PCIE_C4_CTL.

PCIE_RP_APPL_DM_TYPE_0.DEVICE_TYPE.

ROOT_PORT

PCIE_C4_32BIT_DMA 0x36040000 0x3607ffff SYSTEM

PCIE_C0_32BIT_EP 0x38000000 0x38001fff SYSTEM_CFG.PCIE_C0_CTL.

PCIE_RP_APPL_DM_TYPE_0.DEVICE_TYPE.

END_POINT

PCIE_C0_32BIT_RP 0x38000000 0x38001fff SYSTEM_CFG.PCIE_C0_CTL.

PCIE_RP_APPL_DM_TYPE_0.DEVICE_TYPE.

ROOT_PORT

PCIE_C0_32BIT_DMA 0x38040000 0x3807ffff SYSTEM

PCIE_C5_32BIT_EP 0x3a000000 0x3a001fff SYSTEM_CFG.PCIE_C5_CTL.

PCIE_RP_APPL_DM_TYPE_0.DEVICE_TYPE.

END_POINT

PCIE_C5_32BIT_RP 0x3a000000 0x3a001fff SYSTEM_CFG.PCIE_C5_CTL.

PCIE_RP_APPL_DM_TYPE_0.DEVICE_TYPE.

ROOT_PORT

PCIE_C5_32BIT_DMA 0x3a040000 0x3a07ffff SYSTEM

SYSRAM_0_IMPL 0x40000000 0x40067fff SYSTEM

SYNCPOINT_0 0x60000000 0x603fffff SYSTEM

EMEM_32BIT 0x80000000 0xffffffff SYSTEM

PCIE_C1_64BIT 0x1200000000 0x123fffffff SYSTEM

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Block Name Start Address End Address Address Locality

PCIE_C2_64BIT 0x1240000000 0x127fffffff SYSTEM

PCIE_C3_64BIT 0x1280000000 0x12bfffffff SYSTEM

PCIE_C4_64BIT 0x1400000000 0x17ffffffff SYSTEM

PCIE_C0_64BIT 0x1800000000 0x1bffffffff SYSTEM

PCIE_C5_64BIT 0x1c00000000 0x1fffffffff SYSTEM

3.2 Address Space Translation (AST)

3.2.1 Overview

The function of the Address Space Translation (AST) is to convert the local AXI physical addresses of the

Xavier embedded Cortex-R5 and Cortex-A9 processor cores to either virtual or physical Memory Controller

(MC) addresses. The AST also adds MC specific attributes to each address range.

One reason a processor may need to use both virtual and physical addresses is that it has a dedicated portion

of system DRAM that is not visible to the Operating System (OS), and is protected from access by other blocks

in the SoC. Accesses to the dedicated region of DRAM must be sent to the MC as physical addresses, and

must bypass the System Memory Management Unit (SMMU). If that same processor uses virtual addresses

provided by a driver to DMA data, them the processor must support sending both physical and virtual addresses

to the MC.

The figure below shows a simple address map illustrating address space conflicts that the AST is designed to

help resolve. In this example, the OS uses a shared page table for the CPU MMU and SMMU. The Virtual

address used for the shared buffer would collide with the BPMP TMRs addresses. The BPMP uses the AST to

relocate the buffer in its local address space, but still generates the correct virtual address to the SMMU.

This document describes an implementation where the mapping of protected physical regions is handled by

boot code during initialization and is completely transparent to the OS.

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Figure 3.6 Example Address Space Conflict

Features

The AST block provides the following function:

A set of regions that provide a mapping from the local AXI address space to the MC address space. Each region

consists of:

The base address and size of the local region

The base address of the MC region

Snoop attribute (if routed to SCF)

Address space ID (StreamID)

AXI Master and Slave Interfaces

APB Configuration Register block

Per region access controls

Per region lock controls

Global Translation attribute lock

Error Detection

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Configurable behavior for requests that do not match a region or do not have the right protection attributes

(TrustZone or security group):

either pass-through unchanged with a default set of attributes,

or return a DECERR response.

3.2.2 Functional Description

During normal operation the AST block functions as an AXI pipeline with internal address translation. Each

pipeline stage captures information from the previous stage using the AXI read/valid protocol.

Address Generation Blocks

The address generation blocks are responsible for address translation and attribute insertion. The address

generation block compares the incoming address and protection bits with each region. If only one region

matches, the address generation block replaces the incoming address with the corresponding translated

address and pushes the request into the request FIFO, if the FIFO is not full. If no region matches and

AST_CONTROL[MatchErrCtl] is clear, the address generation block pushes the request if the FIFO is not full

without modifying the address and the default attributes. If more than one region matches, or no region matches

and CONTROL[MatchErrCtl] is set, the address generation block forwards the request to the Error response

control block.

Read Error Response

When a match error is detected, the read error control block generates a DECERR response for each required

data beat. Read error responses can only be pushed into the FIFO when the master read response interface is

idle. The read error control block also generates DECERR responses when the block signal is asserted.

Write Error Response

When a match error is detected, the write error control block generates a DECERR response. The write error

control block also matches the AWID of the discarded transaction to discard the corresponding data on the

WDATA channel. The write error control block also generates DECERR responses when the block signal is

asserted.

Since Cortex-R5 processors can send write data before the write address, the write data channel is stalled by

the write error control block until the write address check occurs if data arrives before the address.

The AST implements two forms of register protections, per request permission checks and lock bits. Write

protected registers are treated as read-only if the requirements to write the register are not satisfied.

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Per Request Permission Checks

All registers in the AST have a per request permission check. Registers in the AST are grouped together and

assigned to a security control group. The basic security control groups are Global, Region[N], and Hypervisor.

Each security control group has a dedicated security control register.

Lock Bits

The AST implements a number of lock bits to prevent writes to specific registers or fields. All AST lock bits are

write-once and cannot be cleared except by a system reset. Any registers or fields that are write locked by a

lock bit are treated as read-only when the lock bit is set.

StreamID

The StreamID field sent to the MC is used to identify the SMMU context for a given request. The Hypervisor

assigns a unique StreamID to each VM that it runs. Because the AST is architected to provide address

translations from a local processor, the AST must support switching StreamIDs based on the VM that the local

processor is executing code for. In order to restrict the StreamIDs to the set of VMs that the local processor is

configured to do work for, a StreamID mapping table is defined. The local processor programs the index VM

index to select the StreamID that is output to the MC.

Physical StreamID

The MC subsystem defines a special StreamID that indicates to the SMMU that a request does not require

translation. The physical StreamID can be selected by setting the Physical bit in the region control register.

Decode Error Generation

The AST is responsible for generating a decode error response in the following cases:

A request matches multiple regions

A request does not match a region and AST_CONTROL[MatchErrCtl] is set.

The VMIndx for the request points to an AST_STREAMID_CTL register where the enable bit is not set.

The ast_block input is asserted.

When a decode error is generated, the AST logs the address of the request in the error log registers.

AST Reset

Because the AST module has security specific settings that cannot be modified once the settings are locked by

boot code, the reset to the AST module has two resets. One reset is used to reset the AXI pipeline. The second

reset is used to reset all registers and can only be triggered on a system reset.

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Software Requirements

Requirements for Changing an AST Region Mapping

If the region is cacheable in a local cache, any cache lines with an address in the region must be flushed before

changing the address map.

Prior to changing the mapping of an AST region all pending transactions to that region must be completed.

Hypervisor Requirements

StreamID assignments are handled by the hypervisor.

The hypervisor traps and emulates access to Stream ID registers for OSs that expect to assign stream IDs.

Requirements for Boot Code

Secure Boot Code must program and lock any regions that use the physical StreamID or Carve-out controls.

The StreamID registers are restricted to CCPlex access only using the AST_HYP_SEC_CONTROL register to

prevent a local CPU from being able to program any StreamID.

Cold and Warm Boot AST Initialization Sequence

This initialization sequence must be performed on cold boot by either Boot ROM or MB1 for each AST in AON,

BPMP, SCE, and APE. This sequence must be performed on warm boot by either Boot ROM or SC7 resume

code for each AST in BPMP, SCE, and APE.

If one or more GSCs is assigned to the cluster perform the following steps for each GSC

Select a region to map the GSC and program the region slave base, region master base, and region mask

registers to map the GSC into the Cortex-R5 address space.

Program the AST_REGION_CONTROL register to

Physical = 1

CarveOutID = GSC

Snoop = 0 or 1 (Depends on the GSC usage model)

Lock = 1

Program AST_REGION_SLAVE_BASE_LO[Enable] to 1 for the selected region.

If SysRAM access is required and SysRAM accesses must be physical

Select a region to map SysRAM and program the region slave base, region master base and region mask

registers to map SysRAM into the Cortex-R5 address space.

Program the AST_REGION_CONTROL register to

Physical = 1

CarveOutID = 0

Snoop = 0 or 1 (Depends on the SysRAM usage model)

Lock = 1

Program AST_REGION_SLAVE_BASE_LO[Enable] to 1 for the selected region.

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Program AST_CONTROL [CarveOutLock] to 1

Program AST_CONTROL [DefPhysical] to 0

Program AST_CONTROL [DefVMIndx] to 0

Program AST_STREAMID_CTL0 [Enable] to 1

Program AST_CONTROL [Lock] to 1

If Virtualization is required program AST_HYP_SEC_CONTROL so only the CPU can access the AST security control

registers.

Programming Examples

To remap a region of local memory space using the AST the Region Save Base, Region Mask, and Region

master base register must be programmed correctly.

One 32-bit Input and Output Addresses

The following shows an example of how to program the AST region 0 to map the 64 KB local address region

between 0x8000_0000 and 0x8000_FFFF to the system address region between 0x4FFF_0000 and

0x4FFF_FFFF.

AST_REGION_SLAVE_BASE_LO = 0x8000_0001

AST_REGION_SLAVE_BASE_HI = 0x0000_0000

AST_REGION_MASTER_BASE_LO = 0x4FFF_0000

AST_REGION_MASTER_BASE_HI = 0x0000_0000

AST_REGION_MASK_LO = 0x0000_F000

Setting bits 15-12 of the mask

Defines the region as 64K

Defines a region match as address bits 31-16 equal to 0x8000.

Define the output address as 0x4FFF_XXXX where XXXX is the value of the input address.

AST_REGION_MASK_HI = 0x0000_0000

In this example an input address of 0x8000_1000 would generate an output address of 0x4FFF_1000.

One 32-bit Input Address and 40-bit Output Address

The following shows an example of how to program the AST region 0 to map the 1 MB local address region

between 0x4000_0000 and 0x400F_FFFF to the system address region between 0x03_C000_0000 and

0x03_C00F_FFFF.

AST_REGION_SLAVE_BASE_LO = 0x4000_0001

AST_REGION_SLAVE_BASE_HI = 0x0000_0000

AST_REGION_MASTER_BASE_LO = 0xC000_0000

AST_REGION_MASTER_BASE_HI = 0x0000_0003

AST_REGION_MASK_LO = 0x000F_F000

Setting bits 19-12 of the mask

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Defines the region as 1 MB

Defines a region match as address bits 31-20 equal to 0x400.

Define the output address as 0x03_C00X_XXXX where X_XXXX is the value of the input address.

AST_REGION_MASK_HI = 0x0000_0000

In this example an input address of 0x4006_1000 would generate an output address of 0x03_C006_1000.

Programming Guidelines

The following programming guidelines must be followed to ensure proper operation of the AST.

The region mask must be programed to specify a power of two aligned regions.

The region slave and master addresses must be aligned to the region size.

Software must ensure that AST_REGION_SLAVE_BASE_LO[Enable] is 0 before programming any of the region

registers.

3.2.3 AST Software Requirements

Requirements for Changing an AST Region Mapping

If the region is cacheable in a local cache, any cache lines with an address in the region must be flushed before

changing the address map.

Prior to changing the mapping of an AST region all pending transactions to that region must be completed.

Programming Examples

To remap a region of local memory space using the AST the Region Save Base, Region Mask, and Region

master base register must be programmed correctly.

One 32-bit Input and Output Addresses

The following shows an example of how to program the AST region 0 to map the 64 KB local address region

between 0x8000_0000 and 0x8000_FFFF to the system address region between 0x4FFF_0000 and

0x4FFF_FFFF.

AST_REGION_SLAVE_BASE_LO = 0x8000_0001

AST_REGION_SLAVE_BASE_HI = 0x0000_0000

AST_REGION_MASTER_BASE_LO = 0x4FFF_0000

AST_REGION_MASTER_BASE_HI = 0x0000_0000

AST_REGION_MASK_LO = 0x0000_F000

Setting bits 15-12 of the mask

Defines the region as 64K

Defines a region match as address bits 31-16 equal to 0x8000.

Define the output address as 0x4FFF_XXXX where XXXX is the value of the input address.

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AST_REGION_MASK_HI = 0x0000_0000

In this example an input address of 0x8000_1000 would generate an output address of 0x4FFF_1000.

One 32-bit Input Address and 40-bit Output Address

The following shows an example of how to program the AST region 0 to map the 1 MB local address region

between 0x4000_0000 and 0x400F_FFFF to the system address region between 0x03_C000_0000 and

0x03_C00F_FFFF.

AST_REGION_SLAVE_BASE_LO = 0x4000_0001

AST_REGION_SLAVE_BASE_HI = 0x0000_0000

AST_REGION_MASTER_BASE_LO = 0xC000_0000

AST_REGION_MASTER_BASE_HI = 0x0000_0003

AST_REGION_MASK_LO = 0x000F_F000

Setting bits 15-12 of the mask

Defines the region as 1 MB

Defines a region match as address bits 31-20 equal to 0x400.

Define the output address as 0x03_C00X_XXXX where X_XXXX is the value of the input address.

AST_REGION_MASK_HI = 0x0000_0000

In this example an input address of 0x4006_1000 would generate an output address of 0x03_C006_1000.

3.2.4 AST Registers

Refer to "Reading Register Tables" in the Introduction chapter for the register table protocol as well as

recommendations for accessing registers.

There are 10 instances of the AST registers, two for each of the following five modules as shown in

the table below. The register descriptions in this section provide the offset of each register with base

addresses listed in the table.

Module Instance Name Base Address

Always ON Cluster (AON) and SPE AON_AST_0 0x0c040000

AON_AST_1 0x0c050000

Audio Processing Engine (APE) APE_ACAST 0x02994000

APE_ADAST 0x02996000

Boot and Power Management Processor (BPMP) BPMP_AST_0 0x0d040000

BPMP_AST_1 0x0d050000

Real-time CameraEngine (RCE)

RCE_AST_0

0x0b840000

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Module Instance Name Base Address

RCE_AST_1 0x0b850000

Safety Cluster Engine (SCE) SCE_AST_0 0x0b040000

SCE_AST_1 0x0b050000

R/W

Attribute

Definition

RO Read-only

RW Read-write

RW1 Read-write one only: Once set this bit can only be cleared by a system reset

RWCL Read-write-Carveout-Lock:

Read-only (and can only be reset by a system reset) if (AST_CONTROL[CarveOutLock] == 1)

Read-write if (AST_CONTROL[CarveOutLock] == 0)

RWGL Read-write-Global-Lock:

Read-only (and can only be reset by a system reset) if (AST_CONTROL[Lock] == 1 ||

AST_REGION_*_CONTROL[Lock] == 1)

Read-write if (AST_CONTROL[Lock] == 0 && AST_REGION_*_[Lock] == 0)

Note: AST_REGION_*_CONTROL[Lock] Only applies to the REGION_* Registers

RWRL Read-write-Region-Lock:

Read-only (and can only be reset by a system reset) if (AST_REGION_CONTROL[RegionNum][Lock]

== 1)

Read-write if (AST_REGION_CONTROL[RegionNum][Lock] == 0)

APS_AST_CONTROL_0

Offset: 0x0

Read/Write: See table below

Parity Protection: N

SCR Protection: AST_GBL_SEC_CONTROL_0

Reset: 0x1fc80000 (0b0001,1111,11x0,1000,0xxx,xx00,000x,x000)

Bit R/W Reset Description

31 RW 0x0

ApbOvrOn:

APB Clock Override:

Set to 1 to force APB clock always on in AST.

= APB SLCG is disabled1

0x0

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Bit R/W Reset Description

NicOvrOn:

NIC Clock Override:

Set to 1 to force NIC clock always on in AST.

= NIC SLCG is disabled1

29:22 RWGL 0x7f

PhysStreamID:

Physical StreamID.

This field specifies the StreamID output when the physical stream Id is enabled for a region.

20 RW1 0x0

CarveOutLock:

Carveout Lock.

This bit prevents writes to all Carve Out controls when set to 1.

= FALSE0

= TRUE1

19 RWGL 0x1

DefPhysical:

Default Physical Select.

Specifies the default how the StreamID is selected for default accesses.

= DefVMIndx is used to select the StreamID.0

= PhysStreamID is used1

18:15 RWGL 0x0

DefVMIndex:

Default VM Index.

Specifies the default VM Index used to select the Stream ID when (DefPhysical == 0).

9:5 RWCL 0x0

DefCarveOutID:

Default MC Carveout ID.

Specifies the carveout ID for default accesses.

This field specifies the state output on ast_master_a[w,r]user[15,11] for requests that do not

match a region.

2 RWGL 0x0

DefSnoop:

Snoop.

Specifies if default accesses snoop the Main CPU caches.

This bit controls the state output on ast_master_a[w,r]user[8] for requests that do not match a

region.

0 = Do not snoop request.

1 = Snoop request.

= DISABLE0

= ENABLE1

1 RW 0x0

MatchErrCtl:

Match Error Control: Specifies how transactions that do not match a region are handled.

0 = Transactions that do not match a region are forwarded untranslated with the default

attributes.

1 = Transactions that do not match a region return a decode error on the AXI slave interface.

= NO_DECERR0

= DECERR1

RW1

0x0

Lock:

security lock.

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Bit R/W Reset Description

This bit prevents writing to all RWGL fields.

= FALSE0

= TRUE1

APS_AST_ERROR_STATUS_0

OverFlow : This bit is set to 1 by Hardware when (Valid == 1) and a decode error response is generated by the

AST

VMIndxErr : This bit is set to 1 by Hardware when (Valid == 0) and a decode error response is generated by

the AST because a disabled VMIndx was used

Valid : This bit is set to 1 by Hardware when (Valid == 0) and a decode error response is generated by the AST

SW can write this bit to 0 to clear the logged errors (Clears valid,overflow,error-address bits)

Offset: 0x4

Read/Write: See table below

Parity Protection: N

SCR Protection: AST_GBL_SEC_CONTROL_0

Reset: 0x00000000 (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,x000)

Bit R/W Reset Description

2 RO 0x0

Overflow:

Error Overflow.

This bit is set to 1 by Hardware when (AST_ERROR_STATUS[Valid] == 1) (as result of a

previous error) and a new DEC_ERR occurs.

1 RO 0x0

VMIndxErr:

VM Index Error.

This bit is set to 1 by Hardware when (AST_ERROR_STATUS[Valid] == 0) and when a

DEC_ERR response is returned because a disabled VMIndx was programmed.

0 RW 0x0

Valid:

Error valid.

This bit is set to 1 by Hardware when a DEC_ERR response is returned.

= Error Valid. SW can write this bit to 0 to clear the logged errors (Clears valid,overflow,error-1

address bits).

APS_AST_ERROR_ADDR_LO_0

ErrAddrLo : Logs lower 32 bits of the request that caused a decode error. This field is not updated if

(AST_ERROR_STATUS[Valid] == 1).

Offset: 0x8

Read/Write: RO

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Parity Protection: N

SCR Protection: AST_GBL_SEC_CONTROL_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

ErrAddrLo:

Error Address Low.

When a DEC_ERR response is returned and (AST_ERROR_STATUS[Valid] == 0), then the lower 32 bits of

the error address are latched into this register.

This field is not updated if (AST_ERROR_STATUS[Valid] == 1).

APS_AST_ERROR_ADDR_HI_0

ErrAddrhi : Logs upper 32 bits of the request that caused a decode error. This field is not updated if

(AST_ERROR_STATUS[Valid] == 1).

Offset: 0xc

Read/Write: RO

Parity Protection: N

SCR Protection: AST_GBL_SEC_CONTROL_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

ErrAddrHi:

Error Address high.

When a DEC_ERR response is returned and (AST_ERROR_STATUS[Valid] == 0), the upper 32 bits of the

error address are latched into this register.

This field is not updated if (AST_ERROR_STATUS[Valid] == 1).

APS_AST_STREAMID_CTL_0

This is an array of 16 identical register entries; the register fields below apply to each entry.

Full register list is: APS_AST_STREAMID_CTL_[i], among which [i] belongs to [0..15].

Offset: 0x20,..,0x5c

Read/Write: RW

Parity Protection: N

SCR Protection: AST_HYP_SEC_CONTROL_0

Reset: 0x00000000 (0bxxxx,xxxx,xxxx,xxxx,0000,0000,xxxx,xxx0)

Bit Reset Description

15:8 0x0

StreamID:

This specifies the StreamID output when the VMIndx field is programmed to N in a region control register.

N is the STREAMID_CTL register number.

0x0

Enable:

VM Index Enable.

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Bit Reset Description

When this bit is set StreamID[N] can be selected by the VMIndx N.

0 = VM Index disabled.

1 = VM Index enabled.

= DISABLE0

= ENABLE1

APS_AST_REGION_0_SLAVE_BASE_LO_0

Offset: 0x100

Read/Write: RWRL

Parity Protection: N

SCR Protection: AST_REG_0_SEC_CONTROL_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,xxxx,xxxx,xxx0)

Bit Reset Description

31:12 0x0

SlvBase:

Region Slave Base Address.

This field specifies bits 31:12 of the Base address for the region on the AXI slave interface.

This address is compared with the incoming slave address to determine if a region match occurs.

0 0x0

Enable:

Region Enable.

This enables the translation region.

0 = Translation region disabled.

1 = Translation region enabled,

= FALSE0

= TRUE1

APS_AST_REGION_0_SLAVE_BASE_HI_0

Offset: 0x104

Read/Write: RWRL

Parity Protection: N

SCR Protection: AST_REG_0_SEC_CONTROL_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

SlvBase:

Region Slave Base Address.

This field specifies bits 63:32 of the Base address for the region on the AXI slave interface.

This address is compared with the incoming slave address to determine if a region match occurs.

APS_AST_REGION_0_MASK_LO_0

Offset: 0x108

Read/Write: RWRL

Parity Protection: N

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SCR Protection: AST_REG_0_SEC_CONTROL_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,xxxx,xxxx,xxxx)

Bit Reset Description

31:12 0x0

Mask:

Region Mask Address[31:12].

This field is used to mask incoming address bits when performing the region compare.

This field is also used to mask untranslated address bits when generating the output address.

APS_AST_REGION_0_MASK_HI_0

Offset: 0x10c

Read/Write: RWRL

Parity Protection: N

SCR Protection: AST_REG_0_SEC_CONTROL_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

Mask:

Region Mask Address[63:32].

This field is used to mask incoming address bits when performing the region compare.

This field is also used to mask untranslated address bits when generating the output address.

APS_AST_REGION_0_MASTER_BASE_LO_0

Offset: 0x110

Read/Write: RWRL

Parity Protection: N

SCR Protection: AST_REG_0_SEC_CONTROL_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,xxxx,xxxx,xxxx)

Bit Reset Description

31:12 0x0

MastBase:

Region Master Base Address.

This field specifies bits 31:12 of the Base address for the region on the AXI Master interface.

The Output address is generated using the following equation.

OutputAddress[63:12] = (InputAddress[63:12] & Mask[N]) | (MastBase[N] & !Mask[N]).

APS_AST_REGION_0_MASTER_BASE_HI_0

Offset: 0x114

Read/Write: RWRL

Parity Protection: N

SCR Protection: AST_REG_0_SEC_CONTROL_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

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Bit Reset Description

31:0 0x0

MastBase:

Region Master Base Address.

This field specifies bits 63:32 of the Base address for the region on the AXI Master interface.

The Output address is generated using the following equation.

OutputAddress[63:12] = (InputAddress[63:12] & Mask[N]) | (MastBase[N] & !Mask[N]).

APS_AST_REGION_0_CONTROL_0

Offset: 0x118

Read/Write: See table below

Parity Protection: N

SCR Protection: AST_REG_0_SEC_CONTROL_0

Reset: 0x00000000 (0bxxxx,xxxx,xxxx,0000,0xxx,xx00,000x,x0x0)

Bit R/W Reset Description

19 RWGL 0x0

Physical:

Specifies how the StreamID is selected for a region match.

= VMIndx is used to select the StreamID0

= PhysStreamID is used1

18:15 RWRL 0x0

VMIndex:

Specifies the VM Index used to select the Stream ID when (Physical == 0).

9:5 RWCL 0x0

CarveOutID:

Specifies the carveout ID for the region.

his field specifies the state output on ast_master_a[w,r]user[15,11] for requests that matches the

region.

2 RWRL 0x0

Snoop:

Specifies if region accesses snoop the Main CPU caches.

This bit controls the state output on ast_master_a[w,r]user[8] for requests that matches the

region.

0 = Do not snoop request.

1 = Snoop request.

= DISABLE0

= ENABLE1

0 RW1 0x0

Lock:

This bit prevents writes to this region registers.

= FALSE0

= TRUE1

APS_AST_REGION_1_SLAVE_BASE_LO_0

Offset: 0x120

Read/Write: RWRL

Parity Protection: N

SCR Protection: AST_REG_1_SEC_CONTROL_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,xxxx,xxxx,xxx0)

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Bit Reset Description

31:12 0x0

SlvBase:

Region Slave Base Address.

This field specifies bits 31:12 of the Base address for the region on the AXI slave interface.

This address is compared with the incoming slave address to determine if a region match occurs.

0 0x0

Enable:

Region Enable.

This enables the translation region.

0 = Translation region disabled.

1 = Translation region enabled.

= FALSE0

= TRUE1

APS_AST_REGION_1_SLAVE_BASE_HI_0

Offset: 0x124

Read/Write: RWRL

Parity Protection: N

SCR Protection: AST_REG_1_SEC_CONTROL_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

SlvBase:

Region Slave Base Address.

This field specifies bits 63:32 of the Base address for the region on the AXI slave interface.

This address is compared with the incoming slave address to determine if a region match occurs.

APS_AST_REGION_1_MASK_LO_0

Offset: 0x128

Read/Write: RWRL

Parity Protection: N

SCR Protection: AST_REG_1_SEC_CONTROL_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,xxxx,xxxx,xxxx)

Bit Reset Description

31:12 0x0

Mask:

Region Mask Address[31:12].

This field is used to mask incoming address bits when performing the region compare.

This field is also used to mask untranslated address bits when generating the output address.

APS_AST_REGION_1_MASK_HI_0

Offset: 0x12c

Read/Write: RWRL

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Parity Protection: N

SCR Protection: AST_REG_1_SEC_CONTROL_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

Mask:

Region Mask Address[63:32].

This field is used to mask incoming address bits when performing the region compare.

This field is also used to mask untranslated address bits when generating the output address.

APS_AST_REGION_1_MASTER_BASE_LO_0

Offset: 0x130

Read/Write: RWRL

Parity Protection: N

SCR Protection: AST_REG_1_SEC_CONTROL_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,xxxx,xxxx,xxxx)

Bit Reset Description

31:12 0x0

MastBase:

Region Master Base Address.

This field specifies bits 31:12 of the Base address for the region on the AXI Master interface.

The Output address is generated using the following equation.

OutputAddress[63:12] = (InputAddress[63:12] & Mask[N]) | (MastBase[N] & !Mask[N]).

APS_AST_REGION_1_MASTER_BASE_HI_0

Offset: 0x134

Read/Write: RWRL

Parity Protection: N

SCR Protection: AST_REG_1_SEC_CONTROL_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

MastBase:

Region Master Base Address.

This field specifies bits 63:32 of the Base address for the region on the AXI Master interface.

The Output address is generated using the following equation.

OutputAddress[63:12] = (InputAddress[63:12] & Mask[N]) | (MastBase[N] & !Mask[N]).

APS_AST_REGION_1_CONTROL_0

Offset: 0x138

Read/Write: See table below

Parity Protection: N

SCR Protection: AST_REG_1_SEC_CONTROL_0

Reset: 0x00000000 (0bxxxx,xxxx,xxxx,0000,0xxx,xx00,000x,x0x0)

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Bit R/W Reset Description

19 RWGL 0x0

Physical:

Specifies how the StreamID is selected for a region match.

= VMIndx is used to select the StreamID0

= PhysStreamID is used1

18:15 RWRL 0x0

VMIndex:

Specifies the VM Index used to select the Stream ID when (Physical == 0).

9:5 RWCL 0x0

CarveOutID:

Specifies the carveout ID for the region.

This field specifies the state output on ast_master_a[w,r]user[15,11] for requests that matches

the region.

2 RWRL 0x0

Snoop:

Specifies if region accesses snoop the Main CPU caches.

This bit controls the state output on ast_master_a[w,r]user[8] for requests that matches the

region.

0 = Do not snoop request.

1 = Snoop request.

= DISABLE0

= ENABLE1

0 RW1 0x0

Lock:

This bit prevents writes to this region registers.

= FALSE0

= TRUE1

APS_AST_REGION_2_SLAVE_BASE_LO_0

Offset: 0x140

Read/Write: RWRL

Parity Protection: N

SCR Protection: AST_REG_2_SEC_CONTROL_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,xxxx,xxxx,xxx0)

Bit Reset Description

31:12 0x0

SlvBase:

Region Slave Base Address.

This field specifies bits 31:12 of the Base address for the region on the AXI slave interface.

This address is compared with the incoming slave address to determine if a region match occurs.

0 0x0

Enable:

Region Enable.

This enables the translation region.

0 = Translation region disabled.

1 = Translation region enabled.

= FALSE0

= TRUE1

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APS_AST_REGION_2_SLAVE_BASE_HI_0

Offset: 0x144

Read/Write: RWRL

Parity Protection: N

SCR Protection: AST_REG_2_SEC_CONTROL_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

SlvBase:

Region Slave Base Address.

This field specifies bits 63:32 of the Base address for the region on the AXI slave interface.

This address is compared with the incoming slave address to determine if a region match occurs.

APS_AST_REGION_2_MASK_LO_0

Offset: 0x148

Read/Write: RWRL

Parity Protection: N

SCR Protection: AST_REG_2_SEC_CONTROL_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,xxxx,xxxx,xxxx)

Bit Reset Description

31:12 0x0

Mask:

Region Mask Address[31:12].

This field is used to mask incoming address bits when performing the region compare.

This field is also used to mask untranslated address bits when generating the output address.

APS_AST_REGION_2_MASK_HI_0

Offset: 0x14c

Read/Write: RWRL

Parity Protection: N

SCR Protection: AST_REG_2_SEC_CONTROL_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

Mask:

Region Mask Address[63:32].

This field is used to mask incoming address bits when performing the region compare.

This field is also used to mask untranslated address bits when generating the output address.

APS_AST_REGION_2_MASTER_BASE_LO_0

Offset: 0x150

Read/Write: RWRL

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Parity Protection: N

SCR Protection: AST_REG_2_SEC_CONTROL_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,xxxx,xxxx,xxxx)

Bit Reset Description

31:12 0x0

MastBase:

Region Master Base Address.

This field specifies bits 31:12 of the Base address for the region on the AXI Master interface.

The Output address is generated using the following equation.

OutputAddress[63:12] = (InputAddress[63:12] & Mask[N]) | (MastBase[N] & !Mask[N]).

APS_AST_REGION_2_MASTER_BASE_HI_0

Offset: 0x154

Read/Write: RWRL

Parity Protection: N

SCR Protection: AST_REG_2_SEC_CONTROL_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

MastBase:

Region Master Base Address.

This field specifies bits 63:32 of the Base address for the region on the AXI Master interface.

The Output address is generated using the following equation.

OutputAddress[63:12] = (InputAddress[63:12] & Mask[N]) | (MastBase[N] & !Mask[N]).

APS_AST_REGION_2_CONTROL_0

Offset: 0x158

Read/Write: See table below

Parity Protection: N

SCR Protection: AST_REG_2_SEC_CONTROL_0

Reset: 0x00000000 (0bxxxx,xxxx,xxxx,0000,0xxx,xx00,000x,x0x0)

Bit R/W Reset Description

19 RWGL 0x0

Physical:

Specifies how the StreamID is selected for a region match.

= VMIndx is used to select the StreamID0

= PhysStreamID is used1

18:15 RWRL 0x0

VMIndex:

Specifies the VM Index used to select the Stream ID when (Physical == 0).

9:5 RWCL 0x0

CarveOutID:

Specifies the carveout ID for the region.

This field specifies the state output on ast_master_a[w,r]user[15,11] for requests that matches

the region

RWRL

0x0

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Bit R/W Reset Description

Snoop:

Specifies if region accesses snoop the Main CPU caches.

This bit controls the state output on ast_master_a[w,r]user[8] for requests that matches the

region.

0 = Do not snoop request.

1 = Snoop request.

= DISABLE0

= ENABLE1

0 RW1 0x0

Lock:

This bit prevents writes to this region registers.

= FALSE0

= TRUE1

APS_AST_REGION_3_SLAVE_BASE_LO_0

Offset: 0x160

Read/Write: RWRL

Parity Protection: N

SCR Protection: AST_REG_3_SEC_CONTROL_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,xxxx,xxxx,xxx0)

Bit Reset Description

31:12 0x0

SlvBase:

Region Slave Base Address.

This field specifies bits 31:12 of the Base address for the region on the AXI slave interface.

This address is compared with the incoming slave address to determine if a region match occurs.

0 0x0

Enable:

Region Enable: This enables the translation region.

0 = Translation region disabled.

1 = Translation region enabled.

= FALSE0

= TRUE1

APS_AST_REGION_3_SLAVE_BASE_HI_0

Offset: 0x164

Read/Write: RWRL

Parity Protection: N

SCR Protection: AST_REG_3_SEC_CONTROL_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

SlvBase:

Region Slave Base Address.

This field specifies bits 63:32 of the Base address for the region on the AXI slave interface.

This address is compared with the incoming slave address to determine if a region match occurs.

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APS_AST_REGION_3_MASK_LO_0

Offset: 0x168

Read/Write: RWRL

Parity Protection: N

SCR Protection: AST_REG_3_SEC_CONTROL_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,xxxx,xxxx,xxxx)

Bit Reset Description

31:12 0x0

Mask:

Region Mask Address[31:12].

This field is used to mask incoming address bits when performing the region compare.

This field is also used to mask untranslated address bits when generating the output address.

APS_AST_REGION_3_MASK_HI_0

Offset: 0x16c

Read/Write: RWRL

Parity Protection: N

SCR Protection: AST_REG_3_SEC_CONTROL_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

Mask:

Region Mask Address[63:32].

This field is used to mask incoming address bits when performing the region compare.

This field is also used to mask untranslated address bits when generating the output address.

APS_AST_REGION_3_MASTER_BASE_LO_0

Offset: 0x170

Read/Write: RWRL

Parity Protection: N

SCR Protection: AST_REG_3_SEC_CONTROL_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,xxxx,xxxx,xxxx)

Bit Reset Description

31:12 0x0

MastBase:

Region Master Base Address.

This field specifies bits 31:12 of the Base address for the region on the AXI Master interface.

The Output address is generated using the following equation.

OutputAddress[63:12] = (InputAddress[63:12] & Mask[N]) | (MastBase[N] & !Mask[N]).

APS_AST_REGION_3_MASTER_BASE_HI_0

Offset: 0x174

Read/Write: RWRL

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Parity Protection: N

SCR Protection: AST_REG_3_SEC_CONTROL_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

MastBase:

Region Master Base Address:

This field specifies bits 63:32 of the Base address for the region on the AXI Master interface.

The Output address is generated using the following equation.

OutputAddress[63:12] = (InputAddress[63:12] & Mask[N]) | (MastBase[N] & !Mask[N]).

APS_AST_REGION_3_CONTROL_0

Offset: 0x178

Read/Write: See table below

Parity Protection: N

SCR Protection: AST_REG_3_SEC_CONTROL_0

Reset: 0x00000000 (0bxxxx,xxxx,xxxx,0000,0xxx,xx00,000x,x0x0)

Bit R/W Reset Description

19 RWGL 0x0

Physical:

Specifies how the StreamID is selected for a region match.

= VMIndx is used to select the StreamID0

= PhysStreamID is used1

18:15 RWRL 0x0

VMIndex:

Specifies the VM Index used to select the Stream ID when (Physical == 0).

9:5 RWCL 0x0

CarveOutID:

Specifies the carveout ID for the region.

This field specifies the state output on ast_master_a[w,r]user[15,11] for requests that matches

the region.

2 RWRL 0x0

Snoop:

Specifies if region accesses snoop the Main CPU caches.

This bit controls the state output on ast_master_a[w,r]user[8] for requests that matches the

region.

0 = Do not snoop request.

1 = Snoop request.

= DISABLE0

= ENABLE1

0 RW1 0x0

Lock:

This bit prevents writes to this region registers.

= FALSE0

= TRUE1

APS_AST_REGION_4_SLAVE_BASE_LO_0

Offset: 0x180

Read/Write: RWRL

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Parity Protection: N

SCR Protection: AST_REG_4_SEC_CONTROL_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,xxxx,xxxx,xxx0)

Bit Reset Description

31:12 0x0

SlvBase:

Region Slave Base Address.

This field specifies bits 31:12 of the Base address for the region on the AXI slave interface.

This address is compared with the incoming slave address to determine if a region match occurs.

0 0x0

Enable:

Region Enable.

This enables the translation region.

0=Translation region disabled.

1=Translation region enabled.

= FALSE0

= TRUE1

APS_AST_REGION_4_SLAVE_BASE_HI_0

Offset: 0x184

Read/Write: RWRL

Parity Protection: N

SCR Protection: AST_REG_4_SEC_CONTROL_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

SlvBase:

Region Slave Base Address.

This field specifies bits 63:32 of the Base address for the region on the AXI slave interface.

This address is compared with the incoming slave address to determine if a region match occurs.

APS_AST_REGION_4_MASK_LO_0

Offset: 0x188

Read/Write: RWRL

Parity Protection: N

SCR Protection: AST_REG_4_SEC_CONTROL_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,xxxx,xxxx,xxxx)

Bit Reset Description

31:12 0x0

Mask:

Region Mask Address[31:12].

This field is used to mask incoming address bits when performing the region compare.

This field is also used to mask untranslated address bits when generating the output address.

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APS_AST_REGION_4_MASK_HI_0

Offset: 0x18c

Read/Write: RWRL

Parity Protection: N

SCR Protection: AST_REG_4_SEC_CONTROL_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

Mask:

Region Mask Address[63:32].

This field is used to mask incoming address bits when performing the region compare.

This field is also used to mask untranslated address bits when generating the output address.

APS_AST_REGION_4_MASTER_BASE_LO_0

Offset: 0x190

Read/Write: RWRL

Parity Protection: N

SCR Protection: AST_REG_4_SEC_CONTROL_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,xxxx,xxxx,xxxx)

Bit Reset Description

31:12 0x0

MastBase:

Region Master Base Address.

This field specifies bits 31:12 of the Base address for the region on the AXI Master interface.

The Output address is generated using the following equation.

OutputAddress[63:12] = (InputAddress[63:12] & Mask[N]) | (MastBase[N] & !Mask[N]).

APS_AST_REGION_4_MASTER_BASE_HI_0

Offset: 0x194

Read/Write: RWRL

Parity Protection: N

SCR Protection: AST_REG_4_SEC_CONTROL_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

MastBase:

Region Master Base Address.

This field specifies bits 63:32 of the Base address for the region on the AXI Master interface.

The Output address is generated using the following equation.

OutputAddress[63:12] = (InputAddress[63:12] & Mask[N]) | (MastBase[N] & !Mask[N]).

APS_AST_REGION_4_CONTROL_0

Offset: 0x198

Read/Write: See table below

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Parity Protection: N

SCR Protection: AST_REG_4_SEC_CONTROL_0

Reset: 0x00000000 (0bxxxx,xxxx,xxxx,0000,0xxx,xx00,000x,x0x0)

Bit R/W Reset Description

19 RWGL 0x0

Physical:

Specifies how the StreamID is selected for a region match.

= VMIndx is used to select the StreamID0

= PhysStreamID is used1

18:15 RWRL 0x0

VMIndex:

Specifies the VM Index used to select the Stream ID when Physical=0.

9:5 RWCL 0x0

CarveOutID:

Specifies the carveout ID for the region.

This field specifies the state output on ast_master_a[w,r]user[15,11] for requests that matches

the region.

2 RWRL 0x0

Snoop:

Specifies if region accesses snoop the Main CPU caches.

This bit controls the state output on ast_master_a[w,r]user[8] for requests that matches the

region.

0 = Do not snoop request.

1 = Snoop request.

= DISABLE0

= ENABLE1

0 RW1 0x0

Lock:

This bit prevents writes to this region registers.

= FALSE0

= TRUE1

APS_AST_REGION_5_SLAVE_BASE_LO_0

Offset: 0x1a0

Read/Write: RWRL

Parity Protection: N

SCR Protection: AST_REG_5_SEC_CONTROL_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,xxxx,xxxx,xxx0)

Bit Reset Description

31:12 0x0

SlvBase:

Region Slave Base Address.

This field specifies bits 31:12 of the Base address for the region on the AXI slave interface.

This address is compared with the incoming slave address to determine if a region match occurs.

0x0

Enable:

Region Enable: This enables the translation region.

0 = Translation region disabled.

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Bit Reset Description

1 = Translation region enabled.

= FALSE0

= TRUE1

APS_AST_REGION_5_SLAVE_BASE_HI_0

Offset: 0x1a4

Read/Write: RWRL

Parity Protection: N

SCR Protection: AST_REG_5_SEC_CONTROL_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

SlvBase:

Region Slave Base Address.

This field specifies bits 63:32 of the Base address for the region on the AXI slave interface.

This address is compared with the incoming slave address to determine if a region match occurs.

APS_AST_REGION_5_MASK_LO_0

Offset: 0x1a8

Read/Write: RWRL

Parity Protection: N

SCR Protection: AST_REG_5_SEC_CONTROL_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,xxxx,xxxx,xxxx)

Bit Reset Description

31:12 0x0

Mask:

Region Mask Address[31:12].

This field is used to mask incoming address bits when performing the region compare.

This field is also used to mask untranslated address bits when generating the output address.

APS_AST_REGION_5_MASK_HI_0

Offset: 0x1ac

Read/Write: RWRL

Parity Protection: N

SCR Protection: AST_REG_5_SEC_CONTROL_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

Mask:

Region Mask Address[63:32].

This field is used to mask incoming address bits when performing the region compare.

This field is also used to mask untranslated address bits when generating the output address.

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APS_AST_REGION_5_MASTER_BASE_LO_0

Offset: 0x1b0

Read/Write: RWRL

Parity Protection: N

SCR Protection: AST_REG_5_SEC_CONTROL_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,xxxx,xxxx,xxxx)

Bit Reset Description

31:12 0x0

MastBase:

Region Master Base Address.

This field specifies bits 31:12 of the Base address for the region on the AXI Master interface.

The Output address is generated using the following equation.

OutputAddress[63:12] = (InputAddress[63:12] & Mask[N]) | (MastBase[N] & !Mask[N]).

APS_AST_REGION_5_MASTER_BASE_HI_0

Offset: 0x1b4

Read/Write: RWRL

Parity Protection: N

SCR Protection: AST_REG_5_SEC_CONTROL_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

MastBase:

Region Master Base Address.

This field specifies bits 63:32 of the Base address for the region on the AXI Master interface.

The Output address is generated using the following equation.

OutputAddress[63:12] = (InputAddress[63:12] & Mask[N]) | (MastBase[N] & !Mask[N]).

APS_AST_REGION_5_CONTROL_0

Offset: 0x1b8

Read/Write: See table below

Parity Protection: N

SCR Protection: AST_REG_5_SEC_CONTROL_0

Reset: 0x00000000 (0bxxxx,xxxx,xxxx,0000,0xxx,xx00,000x,x0x0)

Bit R/W Reset Description

19 RWGL 0x0

Physical:

Specifies how the StreamID is selected for a region match.

= VMIndx is used to select the StreamID0

= PhysStreamID is used1

18:15 RWRL 0x0

VMIndex:

Specifies the VM Index used to select the Stream ID when Physical=0

9:5

RWCL

0x0

CarveOutID:

Specifies the carveout ID for the region.

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Bit R/W Reset Description

This field specifies the state output on ast_master_a[w,r]user[15,11] for requests that matches

the region.

2 RWRL 0x0

Snoop:

Specifies if region accesses snoop the Main CPU caches.

This bit controls the state output on ast_master_a[w,r]user[8] for requests that matches the

region.

0 = Do not snoop request.

1 = Snoop request.

= DISABLE0

= ENABLE1

0 RW1 0x0

Lock:

This bit prevents writes to this region registers.

= FALSE0

= TRUE1

APS_AST_REGION_6_SLAVE_BASE_LO_0

Offset: 0x1c0

Read/Write: RWRL

Parity Protection: N

SCR Protection: AST_REG_6_SEC_CONTROL_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,xxxx,xxxx,xxx0)

Bit Reset Description

31:12 0x0

SlvBase:

Region Slave Base Address.

This field specifies bits 31:12 of the Base address for the region on the AXI slave interface.

This address is compared with the incoming slave address to determine if a region match occurs.

0 0x0

Enable:

Region Enable.

This enables the translation region.

0 = Translation region disabled.

1 = Translation region enabled.

= FALSE0

= TRUE1

APS_AST_REGION_6_SLAVE_BASE_HI_0

Offset: 0x1c4

Read/Write: RWRL

Parity Protection: N

SCR Protection: AST_REG_6_SEC_CONTROL_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

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Bit Reset Description

31:0 0x0

SlvBase:

Region Slave Base Address.

This field specifies bits 63:32 of the Base address for the region on the AXI slave interface.

This address is compared with the incoming slave address to determine if a region match occurs.

APS_AST_REGION_6_MASK_LO_0

Offset: 0x1c8

Read/Write: RWRL

Parity Protection: N

SCR Protection: AST_REG_6_SEC_CONTROL_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,xxxx,xxxx,xxxx)

Bit Reset Description

31:12 0x0

Mask:

Region Mask Address[31:12].

This field is used to mask incoming address bits when performing the region compare.

This field is also used to mask untranslated address bits when generating the output address.

APS_AST_REGION_6_MASK_HI_0

Offset: 0x1cc

Read/Write: RWRL

Parity Protection: N

SCR Protection: AST_REG_6_SEC_CONTROL_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

Mask:

Region Mask Address[63:32].

This field is used to mask incoming address bits when performing the region compare.

This field is also used to mask untranslated address bits when generating the output address.

APS_AST_REGION_6_MASTER_BASE_LO_0

Offset: 0x1d0

Read/Write: RWRL

Parity Protection: N

SCR Protection: AST_REG_6_SEC_CONTROL_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,xxxx,xxxx,xxxx)

Bit Reset Description

31:12

0x0

MastBase:

Region Master Base Address.

This field specifies bits 31:12 of the Base address for the region on the AXI Master interface.

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Bit Reset Description

The Output address is generated using the following equation.

OutputAddress[63:12] = (InputAddress[63:12] & Mask[N]) | (MastBase[N] & !Mask[N]).

APS_AST_REGION_6_MASTER_BASE_HI_0

Offset: 0x1d4

Read/Write: RWRL

Parity Protection: N

SCR Protection: AST_REG_6_SEC_CONTROL_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

MastBase:

Region Master Base Address.

This field specifies bits 63:32 of the Base address for the region on the AXI Master interface.

The Output address is generated using the following equation.

OutputAddress[63:12] = (InputAddress[63:12] & Mask[N]) | (MastBase[N] & !Mask[N]).

APS_AST_REGION_6_CONTROL_0

Offset: 0x1d8

Read/Write: See table below

Parity Protection: N

SCR Protection: AST_REG_6_SEC_CONTROL_0

Reset: 0x00000000 (0bxxxx,xxxx,xxxx,0000,0xxx,xx00,000x,x0x0)

Bit R/W Reset Description

19 RWGL 0x0

Physical:

Specifies how the StreamID is selected for a region match.

= VMIndx is used to select the StreamID0

= PhysStreamID is used1

18:15 RWRL 0x0

VMIndex:

Specifies the VM Index used to select the Stream ID when (Physical = 0).

9:5 RWCL 0x0

CarveOutID:

Specifies the carveout ID for the region.

This field specifies the state output on ast_master_a[w,r]user[15,11] for requests that matches

the region.

2 RWRL 0x0

Snoop:

Specifies if region accesses snoop the Main CPU caches.

This bit controls the state output on ast_master_a[w,r]user[8] for requests that matches the

region.

0 = Do not snoop request.

1 = Snoop request.

= DISABLE0

= ENABLE1

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Bit R/W Reset Description

0 RW1 0x0

Lock:

This bit prevents writes to this region registers.

= FALSE0

= TRUE1

APS_AST_REGION_7_SLAVE_BASE_LO_0

Offset: 0x1e0

Read/Write: RWRL

Parity Protection: N

SCR Protection: AST_REG_7_SEC_CONTROL_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,xxxx,xxxx,xxx0)

Bit Reset Description

31:12 0x0

SlvBase:

Region Slave Base Address.

This field specifies bits 31:12 of the Base address for the region on the AXI slave interface.

This address is compared with the incoming slave address to determine if a region match occurs.

0 0x0

Enable:

Region Enable.

This enables the translation region.

0 = Translation region disabled.

1 = Translation region enabled.

= FALSE0

= TRUE1

APS_AST_REGION_7_SLAVE_BASE_HI_0

Offset: 0x1e4

Read/Write: RWRL

Parity Protection: N

SCR Protection: AST_REG_7_SEC_CONTROL_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

SlvBase:

Region Slave Base Address.

This field specifies bits 63:32 of the Base address for the region on the AXI slave interface.

This address is compared with the incoming slave address to determine if a region match occurs.

APS_AST_REGION_7_MASK_LO_0

Offset: 0x1e8

Read/Write: RWRL

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Parity Protection: N

SCR Protection: AST_REG_7_SEC_CONTROL_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,xxxx,xxxx,xxxx)

Bit Reset Description

31:12 0x0

Mask:

Region Mask Address[31:12].

This field is used to mask incoming address bits when performing the region compare.

This field is also used to mask untranslated address bits when generating the output address.

APS_AST_REGION_7_MASK_HI_0

Offset: 0x1ec

Read/Write: RWRL

Parity Protection: N

SCR Protection: AST_REG_7_SEC_CONTROL_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

Mask:

Region Mask Address[63:32].

This field is used to mask incoming address bits when performing the region compare.

This field is also used to mask untranslated address bits when generating the output address.

APS_AST_REGION_7_MASTER_BASE_LO_0

Offset: 0x1f0

Read/Write: RWRL

Parity Protection: N

SCR Protection: AST_REG_7_SEC_CONTROL_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,xxxx,xxxx,xxxx)

Bit Reset Description

31:12 0x0

MastBase:

Region Master Base Address.

This field specifies bits 31:12 of the Base address for the region on the AXI Master interface.

The Output address is generated using the following equation.

OutputAddress[63:12] = (InputAddress[63:12] & Mask[N]) | (MastBase[N] & !Mask[N]).

APS_AST_REGION_7_MASTER_BASE_HI_0

Offset: 0x1f4

Read/Write: RWRL

Parity Protection: N

SCR Protection: AST_REG_7_SEC_CONTROL_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

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Bit Reset Description

31:0 0x0

MastBase:

Region Master Base Address:

This field specifies bits 63:32 of the Base address for the region on the AXI Master interface.

The Output address is generated using the following equation.

OutputAddress[63:12] = (InputAddress[63:12] & Mask[N]) | (MastBase[N] & !Mask[N]).

APS_AST_REGION_7_CONTROL_0

Offset: 0x1f8

Read/Write: See table below

Parity Protection: N

SCR Protection: AST_REG_7_SEC_CONTROL_0

Reset: 0x00000000 (0bxxxx,xxxx,xxxx,0000,0xxx,xx00,000x,x0x0)

Bit R/W Reset Description

19 RWGL 0x0

Physical:

Specifies how the StreamID is selected for a region match.

= VMIndx is used to select the StreamID0

= PhysStreamID is used1

18:15 RWRL 0x0

VMIndex:

Specifies the VM Index used to select the Stream ID when Physical=0

9:5 RWCL 0x0

CarveOutID:

Specifies the carveout ID for the region.

This field specifies the state output on ast_master_a[w,r]user[15,11] for requests that matches

the region.

2 RWRL 0x0

Snoop:

Specifies if region accesses snoop the Main CPU caches.

This bit controls the state output on ast_master_a[w,r]user[8] for requests that matches the

region.

0 = Do not snoop request.

1 = Snoop request.

= DISABLE0

= ENABLE1

0 RW1 0x0

Lock:

This bit prevents writes to this region registers.

= FALSE0

= TRUE1

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3.3 General Purpose Direct Memory Access (DMA)

Engines

3.3.1 Overview

The NVIDIA Xavier series system-on-chip (SoC) has five instances of a General-Purpose DMA engine, all

based on the same architecture, as follows:

A General-Purpose Central DMA controller (GPC-DMA) placed on the Control Fabric. It has thirty-two fully

programmable independent channels which can be programmed by different masters.

A DMA engine as part of the AO subsystem (AON-DMA). It has eight fully programmable independent channels.

A DMA engine as part of the BPMP subsystem (BPMP-DMA). It has four fully programmable independent channels.

A DMA engine as part of the SCE subsystem (SCE-DMA). It has eight fully programmable independent channels.

A DMA engine as part of the RCE subsystem (RCE-DMA). It has eight fully programmable independent channels.

Each DMA engine provides the capability of either being used to write a block of data from Memory Mapped IO

(MMIO) devices, to DRAM or SysRAM system memory via the Memory Subsystem (MSS), or to read a block of

data from DRAM or SysRAM system memory to MMIO devices without any processor intervention. In addition,

GPC-DMA can copy data to and from any memory mapped peripheral to system memory with and without flow

control.

Note that APB is sometimes used in this document to refer to MMIO. The APB bus is still used in parts of the

control fabric, but the General-Purpose DMA engine is not restricted to only APB devices.

This document generally describes the central GPC-DMA controller block, but the instances of the DMA engine

are functionally alike except where noted.

GPC-DMA connections to the reset of Xavier is shown below.

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Figure 3.7 GPC-DMA Top Level Connection Block Diagram

Features

GPC-DMA engine serves APB clients that require memory access

GPC-DMA engine supports APB devices on any APB TNIU

GPC-DMA engine can copy data from any addressable memory to/from DRAM/SysRAM

GPC-DMA engine can copy data from DRAM/SysRAM to DRAM/SysRAM

Firmware backwards-compatibility with legacy APBDMA drivers

Maintain legacy flow-control

Removes the dependency on APB bus by issuing pipelined AXI requests

Direct access to memory via AXICIF

DMA engine has a standard interface

Channels are independent from each other

Allow multiple masters to control different DMA channels

Virtualization support: each channel's registers are in an independent 64K aperture

Functional safety by duplication, ECC for shared buffer and error collator

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New Hardware Features

Busy bit is now asserted by hardware to indicate the presence of any pending transaction on either MSS interface,

MMIO interface, or internal to DMA.

Pause mode now stalls the initiation of future Tx/Rx requests. Any pending transactions (requests or responses) are

allowed to make forward progress and complete. The Busy bit indicates if there is any pending transaction still in

flight.

Add a lock bit per channel in the Hypervisor controlled Channel to block any malicious GuestOS from changing key

registers that could end up in HOL blocking scenarios and potentially blocking another GuestOS channels from

making forward progress.

For Cortex-R5 DMAs only, the RDRSP queue (common response buffer for all channels) on the MSS read interface

has been increased from a depth of 16 bytes (2 x 8 transactions) to a depth of 256 bytes (32 x 8 transactions). The

increase in queue depth matches the maximum number of outstanding read responses in order to solve the DMA

deadlock scenario of DRAM access and TCM access at the same time.

Support for Legacy MMIO DMA Hardware Features

The Xavier GPC-DMA includes the following capabilities from the MMIO DMA hardware in prior NVIDIA SoCs.

Two modes of operation: single transfer (once) or continuous.

Enabled bit for each channel.

Programmable burst sizes of 1, 4, 8, and 16 words

Maximum transfer size is 1 GB per channel, with the minimum size being one word.

Per channel trigger and flow control mechanism support. These are additional controls apart from channel enable on

which the transfer depends. Trigger is used to start a channel on some event to start the transfer, and flow is used to

proceed with every new burst transfer. These events are under software control or hardware control.

Channel to channel trigger support, that is, the ability to link up channels to start at the end of another channel's

transfer, allowing scattering/gathering of physical memory.

Interrupt enable at the end of transfer with the ability to mask or route to a desired processor.

Wrap mode supported for all channels in Once mode.

Round robin arbitration among channels at burst granularity.

Direction bit to determine the direction of transfer MSS to MMIO or MMIO to MSS.

Separate source address and destination address. MSS addresses are 40-bit wide

Wrap feature: enables the address to wrap back to starting address after N words of transfer. For example, if the

address starts at 0x4 with a burst of four words, then the address would increment as 0x4, 0x8, 0xC, 0x10, 0x4, .... If

disabled, it would be 0x4, 0x8, 0xC, 0x10, 0x14.

New GPC-DMA Hardware Features

The Xavier GPC-DMA also includes these hardware features:

Runs on AXI/PCLK with 1:1 ratio synchronous clock

Two directional bits to determine the direction of transfer

SysRAM-SDRAM to SDRAM-SysRAM

Fixed pattern write to SysRAM-SDRAM

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Programmable burst sizes of 1, 2, 4, 8, 16 words on MMIO 2 and 16 words on memory

Transfer size in words

Byte enable support

Interrupts per channel can be routed to CCPLEX, BPMP, SCE, or SPE. An additional interrupt for common space.

Interrupt generation per channel after last burst write response (MMIO or Memory)

Support TrustZone and NV security privileges per channel for a given master

Error handling and DMA engine termination upon errors

Virtualization support by placing channel registers in a 64K aperture

Interrupt is generated when the last response data is received from the MSS for Rx mode, or once the last response

data is received from the MMIO bus while reading from MSS (Tx mode).

Memory to Memory DMA transfer

Supported Legacy Software Features

The FIFO trigger levels (in the modules) need to be programmed so they do not lead to an overflow/underflow of the

FIFO.

Software programs all the registers of channel ensuring that the channel enable bit is disabled. Set the channel

enable bit last.

If channel is disabled while transfer is in progress, the transfer ends after ongoing burst is completed and an interrupt

is generated (if that interrupt is enabled)

Busy bit gets set as soon as the DMA channel is enabled and gets cleared after transfer is completed.

Interrupts are "write 1 to clear"

The default wraparound on the MMIO side is wrapping on one word. It prevents unnecessary address switching on

the MMIO.

The parameters of the channel must be programmed first (base address, wrap-around….), then the control register of

that channel is programmed. If the control register is programmed first, the current parameters of the DMA would be

considered as the programmed values.

3.3.2 Functional Description

There are 32 channels in GPC-DMA. A DMA channel can transfer a specified range of data between a memory

address space (SysRAM or Ext MEM) and an MMIO address space. A DMA channel can also transfer data

between a memory address space and another memory address space (Mem-to-Mem copy). The DMA

controller follows a simple round robin arbitration scheme between the channels, starting with channel 0.

Each channel can have an independent burst transfer size programmed to one word, two words, four words,

eight words, or sixteen words. There is a corresponding read/write buffer in the memory buffer manager for

each channel. There is also a corresponding buffer for each channel on the peripheral side.

DMA Functionality: Mem-MMIO

After programming the DMA channel with the starting MMIO and MSS address, the burst size and the total

transfer byte count, the DMA engine can be enabled by setting the channel enable bit.

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Peripheral Rx-Mode: DMA Read from MMIO Peripheral to Memory

The burst size and the FIFO trigger levels in the MMIO slave need to be programmed such that they do not lead

to an overflow/underflow of the FIFOs in the peripheral. This means that the controller FIFO thresholds need to

be set correctly based on DMA request size. The DMA engine waits for the flow control request from the

peripheral controller to trigger a transfer to the DMA. The DMA transfers that burst for the given channel.

If the burst size is 8, then a 32-byte request can be initiated on the memory interface. For some clients that

have support like QSPI, a burst size of 16 words can be initiated to fill the 64-byte buffer in the buffer manager.

The buffer control uses byte enable control for unaligned transfers and for the residual bytes if the remaining

transfer is less than 32/64 bytes. A burst size of 4 is also supported, but in this case multiple bursts are needed

to initiate the 32/64 byte transfers on the memory interface. Once an Rx request has been initiated to the DMA

by the peripheral, the DMA engine initiates a read request from the peripheral FIFO.

In case the peripheral is fast enough to fill in the second burst and to increase the DMA engine performance,

the Peripheral Control block has the option of initiating two outstanding read requests to transfer bursts from the

peripheral FIFO to system memory. The number of MMIO outstanding requests is set in channel register space.

Peripheral Tx-Mode: DMA Write from Memory to MMIO

The burst size and the FIFO trigger levels in the MMIO slave need to be programmed so they do not lead to an

overflow/underflow of the FIFOs in the MMIO client. The DMA engine always initiates a 64-byte read from the

MSS for the best system memory utilization. Upon receiving the read data in the buffer, and in case the burst

size programmed is 8, then a 32-byte data transfer can occur to the MMIO slave. For clients that support a burst

size of 16 words, then all 64 bytes can be transferred.

Once a Tx request has been initiated to the DMA by the peripheral, the DMA engine initiates a read request

from memory. In case the peripheral is fast enough to read in the current burst request and to increase the DMA

engine performance, the Peripheral Control block has the option of initiating two outstanding write requests to

transfer bursts from the system memory to the peripheral FIFO. In this case, the second write request is queued

in the bridge until the peripheral is ready to consume the second burst. In this mode, the Peripheral Control

block has to keep track of the outstanding requests and their responses relative to the total transfer byte count

needed. The number of MMIO outstanding requests is set in channel register space.

MEM-MEM DMA Mode

MEM-MEM mode can read and write channels that are used to copy data from one memory location to another.

The read channel keeps track of the total transfer size. The RD_MEM engine initiates multiple outstanding read

requests to the MSS for higher bandwidth. Once the read data arrives, the RD_MEM block copies this data to

the corresponding write buffer in the WR_MEM block. The WR_MEM block in return sends the write data to

system memory with a different address. This process continues until all data is copied.

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3.3.3 Programming Guidelines

Main Programming Steps

All the registers of a channel need to be programmed before the Channel Enable bit is set.

Program the MSS Starting Address and MMIO Starting address in GPC-DMA-X Source Address Pointer and GPC-

DMA-X Destination Address Pointer registers.

Program the required BURST size, WRAP word window size, and BM_DATA_SWAP (byte swapping) option in the

GPC-DMA-X MSS Address Sequencer register. The MSS BUS width is fixed to 64-bit bus.

Program the required APB_BUS_WIDTH (as the peripheral), APB_DATA_BBTW (byte swapping) option, and WRAP

word window size in the MMIO Address Sequencer register.

Program the number of words to be transferred in the GPC_DMACHAN_CHANNEL_X_BCOUNT register.

Program the Trigger in GPC-DMA-X Control-Extended register.

Program the Interrupt option, FC mode, DMA transfer direction, Transfer mode, and Flow Enable in

GPC_DMACHAN_CHANNEL_X_CSR Register. Write the channel Enable bit in the same register.

Whenever the Channel ENB bit is enabled, the DMA starts the Data transfer. The security attributes after writing

Channel Enable are latched and used by the current DMA engine for peripheral access. MSS security is programmed

under GPC-DMA-X MSS Address Sequencer.

Each channel's status is observed by polling the GPC_DMACHAN_CHANNEL_X_STA register. The number of words

remaining to be transferred are in the GPC_DMACHAN_CHANNEL_X_BYTE_TRA register.

Tx/Rx Flow/Trigger requesters are programmed in the GPC_DMACHAN_CHANNEL_0_CSR registers.

GPC-DMA Address Space

For different DMA register programming, use the following address rules for IP base and IP register:

For GPC-DMA: NV_ADDRESS_MAP_GPCDMA_BASE + GPCDMA_CHANNEL_XXXXXXX

For BPMP DMA: NV_ADDRESS_MAP_BPMP_DMA_BASE + GPCDMA_BPMP_CHANNEL_XXXXXXX

For SCE DMA: NV_ADDRESS_MAP_SCE_DMA_BASE + GPCDMA_SCE_CHANNEL_XXXXXXX

For AO DMA: NV_ADDRESS_MAP_AO_DMA_BASE + GPCDMA_AO_CHANNEL_XXXXXXX

QSPI Tx Mode

For QSPI maximum performance, here is an example of setting BPMP DMA for Tx QSPI mode (MEM2MMIO)

on Channel 0:

Enable Clk and deassert Reset for QSPI

NV_ADDRESS_MAP_CAR_BASE + CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI_0 = 0xFFFFFFFF

NV_ADDRESS_MAP_CAR_BASE + CLK_RST_CONTROLLER_RST_DEV_QSPI_0 = 0x0

Release Reset on BPMP DMA and QSPI

NV_ADDRESS_MAP_CAR_BASE + CLK_RST_CONTROLLER_RST_DEV_BPMP_DMA_0 = 0x0

Enable FIXED mode in AXIP2P

NV_ADDRESS_MAP_AXIP2P_5_BASE+BPMP_BR_ERROR_CONFIG_0 = 0x0

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Set destination address to QSPI Tx FIFO

addrdec2xml.pl addrmap2dm_pd.pl fabric_amap_diff.+

GPCDMA_BPMP_CHANNEL_CH0_DST_PTR_0 = NV_ADDRESS_MAP_QSPI_BASE + QSPI_TX_FIFO_0

Set source address to MSS address

NV_ADDRESS_MAP_BPMP_DMA_BASE + GPCDMA_BPMP_CHANNEL_CH0_SRC_PTR_0 = lower 32 bits of

MC_SRAM_ADDR

NV_ADDRESS_MAP_BPMP_DMA_BASE + GPCDMA_BPMP_CHANNEL_CH0_HI_ADR_PTR_0[7:0] = Upper 8 bits

of MC_SRAM_ADDR

Set MSS configuration

MSS outstanding requests to 16

MSS burst size = 64B

No Wrap mode

AXIID = 1 or 0 (use 0 in this example)

No PROT bit

StreamID 0 = 0 – 127 (use 1 in this example)

NV_ADDRESS_MAP_BPMP_DMA_BASE + GPCDMA_BPMP_CHANNEL_CH0_MC_SEQ_0 = 0x21800001

Set MMIO configuration

Set MMIO outstanding requests to 4

Wrap = 1 and No PROT bit

NV_ADDRESS_MAP_BPMP_DMA_BASE + GPCDMA_BPMP_CHANNEL_CH0_MMIO_SEQ_0 =

0x27810000

Set Word Count size

NV_ADDRESS_MAP_BPMP_DMA_BASE + GPCDMA_BPMP_CHANNEL_CH0_BCOUNT_0 = 0xXXXXXXXX

Disable virtualization

NV_ADDRESS_MAP_BPMP_DMA_BASE +

GPCDMA_BPMP_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0 = 0x0

Set DMA configuration

Enable end of channel interrupt trigger and mask

Enable Once mode

Enable FC mode = 4

Enable MEM2MMIO with FC mode

Set peripheral ID to QSPI

Enable Channel

NV_ADDRESS_MAP_BPMP_DMA_BASE + GPCDMA_BPMP_CHANNEL_CH0_CSR_0 = 0xCB618400

QSPI Rx Mode

For QSPI maximum performance, here is an example of setting BPMP DMA for Rx QSPI mode (IO2MEM) on

Channel 0:

Enable Clk and deassert Reset for QSPI

NV_ADDRESS_MAP_CAR_BASE + CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI_0 = 0xFFFFFFFF

NV_ADDRESS_MAP_CAR_BASE + CLK_RST_CONTROLLER_RST_DEV_QSPI_0 = 0x0

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Release Reset on BPMP DMA and QSPI

NV_ADDRESS_MAP_CAR_BASE + CLK_RST_CONTROLLER_RST_DEV_BPMP_DMA_0 = 0x0

Enable FIXED mode in AXIP2P

NV_ADDRESS_MAP_AXIP2P_5_BASE + BPMP_BR_ERROR_CONFIG_0 = 0x0

Set source address to QSPI RX FIFO

NV_ADDRESS_MAP_BPMP_DMA_BASE + GPCDMA_BPMP_CHANNEL_CH0_SRC_PTR_0 =

NV_ADDRESS_MAP_QSPI_BASE + QSPI_RX_FIFO_0

Set destination address to MSS/SRAM address

NV_ADDRESS_MAP_BPMP_DMA_BASE + GPCDMA_BPMP_CHANNEL_CH0_DST_PTR_0 = lower 32 bits of

MC_SRAM_ADDR

NV_ADDRESS_MAP_BPMP_DMA_BASE + GPCDMA_BPMP_CHANNEL_CH0_HI_ADR_PTR_0[23:16] = Upper 8

bits of MC_SRAM_ADDR (Default setting is fine if using 4G system)

Set MSS configuration

MSS outstanding requests to 16

MSS burst size = 64B

No Wrap mode

AXIID = 1 or 0 (use 0 in this example)

No PROT bit

StreamID 0 = 0 – 127 (use 1 in this example)

NV_ADDRESS_MAP_BPMP_DMA_BASE + GPCDMA_BPMP_CHANNEL_CH0_MC_SEQ_0 = 0x21800001

Set MMIO configuration

Set MMIO outstanding requests to 4

Wrap = 1 and No PROT bit

NV_ADDRESS_MAP_BPMP_DMA_BASE + GPCDMA_BPMP_CHANNEL_CH0_MMIO_SEQ_0 =

0x27810000

Set Word Count size

NV_ADDRESS_MAP_BPMP_DMA_BASE + GPCDMA_BPMP_CHANNEL_CH0_BCOUNT_0 = 0xXXXXXXXX

Disable virtualization

NV_ADDRESS_MAP_BPMP_DMA_BASE +

GPCDMA_BPMP_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0 = 0x0

Set DMA configuration and Enable DMA

Enable end of channel interrupt trigger and mask

Enable Once mode

Enable FC mode = 4

Enable MMIO2MEM with FC mode

Set peripheral ID to QSPI

Enable Channel

NV_ADDRESS_MAP_BPMP_DMA_BASE + GPCDMA_BPMP_CHANNEL_CH0_CSR_0 = 0xCB218400

Pause Mode

Setting CHANNEL_PAUSE bit in GPC_DMACHAN_CHANNEL_0_CSRE blocks any controller requests from being

serviced. All transfers that are in progress are allowed to continue and make forward progress. Clearing

CHANNEL_PAUSE resumes the transfers.

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Do not disable a channel when a channel busy bit is asserted (BSY0-31). Pause mode flushes out all pending

requests from GPC-DMA and any inflight data on MSS and MMIO bus.

Upon pausing the channel, the programming sequence is:

Software waits for the DMA channel to be idle (busy bit deasserted)

Software now can disable the paused channel or un-pause the channel

To restart the channel after disable, the pause bit must be cleared first

In unaligned source/destination address cases, the pause mode does not flush out the data correctly

If there was a mismatch in burst sizes between MMIO and MSS (MMIO burst > MSS burst), the pause mode

does not flush out data correctly.

If an error occurred during pause mode, then an error interrupt is asserted and software shall reset the DMA

engine.

Maximum latency for waiting for MSS traffic from DMA to be committed is 100 µs.

Typically, all transactions have been committed by this time in pause mode.

Abrupt Channel Disable

If channel ENB is disabled abruptly while a transfer is in progress, the transfer ends after completing any burst

sequence that is in progress. GPC-DMA does not flush out remaining data in local buffers.

Busy Bit

The Busy bit is read only and gets set when there is any inflight transaction either internally to DMA, on the

MMIO interface, or on the MSS interface. The bit is cleared by Hardware after all pending transfers are

completed.

Enable (ENB) Bit

GPC-DMA channel enable bit ENB in GPCDMA_CHANNEL_CHX_CSR_0 is auto cleared after receiving an in-band

error. In that case, the enable bit is cleared after all pending transactions are completed.

GPC-DMA channel enable bit ENB in GPCDMA_CHANNEL_CHX_CSR_0 is auto cleared after all DMA transactions

are completed in single mode. In that case, the enable bit is cleared after all pending transactions are completed. For

re-use cases, software must enable the bit after reprogramming DMA.

DMA Interrupt

Interrupts are write-1-to-clear, i.e., interrupt bit is cleared when the value of write data corresponding to the bit

position of the interrupt bit is 1.

Controller FIFO Size

The APB burst size and the FIFO trigger levels (in the peripheral controller) need to be programmed so they do

not lead to an overflow/underflow of the FIFOs in the APB client. The current limitation is that they need to be

the same.

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Transfer Alignment

MSS requests are always aligned to 4 Bytes (lower 2 bits are zeros).

MMIO requests are always aligned to 4 Bytes (lower 2 bits are zeros).

When flow control is enabled, the number of words to be transferred must always be a multiple of the burst size

/MMIO trigger level.

The DMA wraparound needs to be programmed keeping in mind the address that is programmed in the BM start

address and the burst size.

BCOUNT Register

If the DMA channel is enabled, then source/destination addresses BCOUNT can be reprogrammed during data

transfer and after enabling the channel. BCOUNT can be a multiple of burst sizes:

In case of Mem2Mem copy, Word Count could be any non-zero number within 1 GB.

In case of mem2mmio or mmio2mem copy, Word Count should be a multiple of I/O burst size.

Continuous Mode

In continuous mode single buffer mode, software has two separate buffers that are maintained by software to

emulate the hardware ping pong buffer. In this mode, software enables the DMA with the ping-buffer address

and then reprograms the DMA with pong buffer after enabling the DMA. The DMA registers are shadowed

(latched) every time upon entering the continuous cycle. The register programming can be done for the pong

buffer either after enabling the channel (for the first reprogramming) or receiving an interrupt (for any

subsequent reprogramming). Software has requested 15 ms interrupt latency as the worst case requirement.

If interrupt latency is not guaranteed, then pausing the DMA channel is needed before reprogramming the new

addresss/word count. The pause mode must be done before receiving an end of transfer (EoT) interrupt which

guarantees it does not re-transfer to the same buffer.

If DMA channel in Rx mode is abruptly disabled in a continuous mode during a transfer, then:

For this mode use FC_mode = 0

Set MMIO burst size = 16W

When the IO controller generates an interrupt, the Rx request line should not be asserted

The last MSS request should be committed to MSS before disabling the channel

As a precautionary measure, the CPU should disable this channel after ensuring there is no DMA activity on MSS or

MMIO by reading the DMA_IO_MC_ACTIVE status register under GPCDMA_COMMON_DMA_ACTIVE_0

Any residual words in the IO controller FIFO should be cleared by host

HOL Blocking

Since DBB does not support OOO for all GPC-DMA channels, and if there is more than one channel running in

either Tx or Rx mode, a HOL blocking can occur on DBB if the outstanding request size is more than two for

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any of these channels. For BPMP-DMA/GPC-DMA only, If more than two channels are used, then FC_MODE =

0x3 and MMIO_BURST = 64B should never be programmed.

Non-continuous SPI mode

For non-continuous SPI mode:

The external device might stop sending data after some logical boundary, so Software programs GPCDMA for the

maximum possible Data Transfer size based upon use case

SPI is programmed for 4B/1W Rx mode as trigger level

GPCDMA channel is programmed for 4B/1W MMIO Burst Size

GPCDMA channel is programmed for 64B/16W MSS Burst Size (default value in spec, so no need to program

explicitly)

SPI generates an interrupt to the CPU when the external device stops sending data

Based upon this interrupt, DMA CH_BSY = 1 write DMA Channel Pause Bit and wait for

&& SPI RX_FIFO is empty,

CH_BSY status to go low

When CH_BSY bit is "0," it's expected that the SPI Transfer Count Status is equal to DMA_BYTE Count Status

If SPI Transfer count status < DMA_BYTE Count status by 1B/2B/3B, discard that data before providing it to

consumer

3.3.4 GPC-DMA Registers

COMMON

GPCDMA_COMMON_DMA_CHAN_STA_0

Offset: 0x0

Read/Write: RO

Parity Protection: N

SCR Protection: SCR_DMA_RO_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31 0x0

CH31

30 0x0

CH30

29 0x0

CH29

28 0x0

CH28

27 0x0

CH27

26 0x0

CH26

25 0x0

CH25

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Bit Reset Description

24 0x0

CH24

23 0x0

CH23

22 0x0

CH22

21 0x0

CH21

20 0x0

CH20

19 0x0

CH19

18 0x0

CH18

17 0x0

CH17

16 0x0

CH16

15 0x0

CH15

14 0x0

CH14

13 0x0

CH13

12 0x0

CH12

11 0x0

CH11

10 0x0

CH10

9 0x0

CH9

8 0x0

CH8

7 0x0

CH7

6 0x0

CH6

5 0x0

CH5

4 0x0

CH4

3 0x0

CH3

2 0x0

CH2

1 0x0

CH1

0 0x0

CH0

GPCDMA_COMMON_REQUESTORS_TX_0

Offset: 0x4

Read/Write: RO

Parity Protection: N

SCR Protection: SCR_DMA_RO_0

Reset: 0x00000000 (0b00xx,00x0,0000,0x00,0x00,xx00,x00x,0000)

Bit Reset Description

31 0x0

I2C9

30 0x0

I2C6

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Bit Reset Description

27 0x0

I2C7

26 0x0

I2C4

24 0x0

I2C5

23 0x0

I2C3

22 0x0

I2C2

21 0x0

I2C

20 0x0

UARTE

19 0x0

UARTD

17 0x0

SPI3

16 0x0

SPI2

15 0x0

SPI1

13 0x0

UARTH

12 0x0

UARTF

9 0x0

UARTB

8 0x0

UARTA

6 0x0

QSPI1

5 0x0

QSPI0

3 0x0

UARTC

2 0x0

UARTG

1 0x0

I2C10

0 0x0

I2C8

GPCDMA_COMMON_REQUESTORS_RX_0

Offset: 0x8

Read/Write: RO

Parity Protection: N

SCR Protection: SCR_DMA_RO_0

Reset: 0x00000000 (0b00xx,00x0,0000,0x00,0x00,xx00,x00x,0000)

Bit Reset Description

31 0x0

I2C9

30 0x0

I2C6

27 0x0

I2C7

26 0x0

I2C4

24 0x0

I2C5

23 0x0

I2C3

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Bit Reset Description

22 0x0

I2C2

21 0x0

I2C

20 0x0

UARTE

19 0x0

UARTD

17 0x0

SPI3

16 0x0

SPI2

15 0x0

SPI1

13 0x0

UARTH

12 0x0

UARTF

9 0x0

UARTB

8 0x0

UARTA

6 0x0

QSPI1

5 0x0

QSPI0

3 0x0

UARTC

2 0x0

UARTG

1 0x0

I2C10

0 0x0

I2C8

GPCDMA_COMMON_COMMON_ERROR_STA_0

Offset: 0xc

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_HYPER_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

ERROR_STATUS

GPCDMA_COMMON_CHANNEL_ERROR_STA_0

Offset: 0x10

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_HYPER_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

ERROR_STATUS

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GPCDMA_COMMON_CHANNEL_TRIG_REG_0

Offset: 0x18

Read/Write: RO

Parity Protection: N

SCR Protection: SCR_DMA_RO_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31 0x0

CH31

30 0x0

CH30

29 0x0

CH29

28 0x0

CH28

27 0x0

CH27

26 0x0

CH26

25 0x0

CH25

24 0x0

CH24

23 0x0

CH23

22 0x0

CH22

21 0x0

CH21

20 0x0

CH20

19 0x0

CH19

18 0x0

CH18

17 0x0

CH17

16 0x0

CH16

15 0x0

CH15

14 0x0

CH14

13 0x0

CH13

12 0x0

CH12

11 0x0

CH11

10 0x0

CH10

9 0x0

CH9

8 0x0

CH8

7 0x0

CH7

6 0x0

CH6

5 0x0

CH5

4 0x0

CH4

3 0x0

CH3

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Bit Reset Description

2 0x0

CH2

1 0x0

CH1

0 0x0

CH0

GPCDMA_COMMON_MASKED_INTR_REG_0

Offset: 0x1c

Read/Write: RO

Parity Protection: N

SCR Protection: SCR_DMA_RO_0

Reset: 0xffffffff (0b1111,1111,1111,1111,1111,1111,1111,1111)

Bit Reset Description

31 0x1

CH31

30 0x1

CH30

29 0x1

CH29

28 0x1

CH28

27 0x1

CH27

26 0x1

CH26

25 0x1

CH25

24 0x1

CH24

23 0x1

CH23

22 0x1

CH22

21 0x1

CH21

20 0x1

CH20

19 0x1

CH19

18 0x1

CH18

17 0x1

CH17

16 0x1

CH16

15 0x1

CH15

14 0x1

CH14

13 0x1

CH13

12 0x1

CH12

11 0x1

CH11

10 0x1

CH10

9 0x1

CH9

8 0x1

CH8

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Bit Reset Description

7 0x1

CH7

6 0x1

CH6

5 0x1

CH5

4 0x1

CH4

3 0x1

CH3

2 0x1

CH2

1 0x1

CH1

0 0x1

CH0

GPCDMA_COMMON_CHANNEL_INTR_STA_0

Offset: 0x20

Read/Write: RO

Parity Protection: N

SCR Protection: SCR_DMA_RO_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31 0x0

CH31

30 0x0

CH30

29 0x0

CH29

28 0x0

CH28

27 0x0

CH27

26 0x0

CH26

25 0x0

CH25

24 0x0

CH24

23 0x0

CH23

22 0x0

CH22

21 0x0

CH21

20 0x0

CH20

19 0x0

CH19

18 0x0

CH18

17 0x0

CH17

16 0x0

CH16

15 0x0

CH15

14 0x0

CH14

13 0x0

CH13

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Bit Reset Description

12 0x0

CH12

11 0x0

CH11

10 0x0

CH10

9 0x0

CH9

8 0x0

CH8

7 0x0

CH7

6 0x0

CH6

5 0x0

CH5

4 0x0

CH4

3 0x0

CH3

2 0x0

CH2

1 0x0

CH1

0 0x0

CH0

GPCDMA_COMMON_COMMON_INTR_0

Offset: 0x24

Read/Write: See table below

Parity Protection: N

SCR Protection: SCR_HYPER_0

Reset: 0x00000000 (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxx0,0000)

Bit R/W Reset Description

4 RO 0x0

RAW_INTR_STATUS

3 RO 0x0

IRQ_INTR_STATUS

2 RW 0x0

IS_EOC

1 RW 0x0

INTR_MASK

0 RW 0x0

IE_EOC

GPCDMA_COMMON_CHANNEL_REG_LOCK_0

Offset: 0x28

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_HYPER_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

REGLOCK

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GPCDMA_COMMON_CH0_PERI_ID_MASK_0

Offset: 0x80

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_HYPER_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

CH0_PERI_ID_MASK

GPCDMA_COMMON_CH1_PERI_ID_MASK_0

Offset: 0x84

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_HYPER_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

CH1_PERI_ID_MASK

GPCDMA_COMMON_CH2_PERI_ID_MASK_0

Offset: 0x88

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_HYPER_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

CH2_PERI_ID_MASK

GPCDMA_COMMON_CH3_PERI_ID_MASK_0

Offset: 0x8c

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_HYPER_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

CH3_PERI_ID_MASK

GPCDMA_COMMON_CH4_PERI_ID_MASK_0

Offset: 0x90

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Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_HYPER_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

CH4_PERI_ID_MASK

GPCDMA_COMMON_CH5_PERI_ID_MASK_0

Offset: 0x94

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_HYPER_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

CH5_PERI_ID_MASK

GPCDMA_COMMON_CH6_PERI_ID_MASK_0

Offset: 0x98

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_HYPER_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

CH6_PERI_ID_MASK

GPCDMA_COMMON_CH7_PERI_ID_MASK_0

Offset: 0x9c

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_HYPER_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

CH7_PERI_ID_MASK

GPCDMA_COMMON_CH8_PERI_ID_MASK_0

Offset: 0xa0

Read/Write: R/W

Parity Protection: N

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SCR Protection: SCR_HYPER_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

CH8_PERI_ID_MASK

GPCDMA_COMMON_CH9_PERI_ID_MASK_0

Offset: 0xa4

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_HYPER_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

CH9_PERI_ID_MASK

GPCDMA_COMMON_CH10_PERI_ID_MASK_0

Offset: 0xa8

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_HYPER_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

CH10_PERI_ID_MASK

GPCDMA_COMMON_CH11_PERI_ID_MASK_0

Offset: 0xac

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_HYPER_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

CH11_PERI_ID_MASK

GPCDMA_COMMON_CH12_PERI_ID_MASK_0

Offset: 0xb0

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_HYPER_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

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Bit Reset Description

31:0 0x0

CH12_PERI_ID_MASK

GPCDMA_COMMON_CH13_PERI_ID_MASK_0

Offset: 0xb4

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_HYPER_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

CH13_PERI_ID_MASK

GPCDMA_COMMON_CH14_PERI_ID_MASK_0

Offset: 0xb8

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_HYPER_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

CH14_PERI_ID_MASK

GPCDMA_COMMON_CH15_PERI_ID_MASK_0

Offset: 0xbc

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_HYPER_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

CH15_PERI_ID_MASK

GPCDMA_COMMON_CH16_PERI_ID_MASK_0

Offset: 0xc0

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_HYPER_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

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Bit Reset Description

31:0 0x0

CH16_PERI_ID_MASK

GPCDMA_COMMON_CH17_PERI_ID_MASK_0

Offset: 0xc4

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_HYPER_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

CH17_PERI_ID_MASK

GPCDMA_COMMON_CH18_PERI_ID_MASK_0

Offset: 0xc8

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_HYPER_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

CH18_PERI_ID_MASK

GPCDMA_COMMON_CH19_PERI_ID_MASK_0

Offset: 0xcc

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_HYPER_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

CH19_PERI_ID_MASK

GPCDMA_COMMON_CH20_PERI_ID_MASK_0

Offset: 0xd0

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_HYPER_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

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Bit Reset Description

31:0 0x0

CH20_PERI_ID_MASK

GPCDMA_COMMON_CH21_PERI_ID_MASK_0

Offset: 0xd4

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_HYPER_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

CH21_PERI_ID_MASK

GPCDMA_COMMON_CH22_PERI_ID_MASK_0

Offset: 0xd8

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_HYPER_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

CH22_PERI_ID_MASK

GPCDMA_COMMON_CH23_PERI_ID_MASK_0

Offset: 0xdc

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_HYPER_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

CH23_PERI_ID_MASK

GPCDMA_COMMON_CH24_PERI_ID_MASK_0

Offset: 0xe0

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_HYPER_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

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Bit Reset Description

31:0 0x0

CH24_PERI_ID_MASK

GPCDMA_COMMON_CH25_PERI_ID_MASK_0

Offset: 0xe4

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_HYPER_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

CH25_PERI_ID_MASK

GPCDMA_COMMON_CH26_PERI_ID_MASK_0

Offset: 0xe8

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_HYPER_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

CH26_PERI_ID_MASK

GPCDMA_COMMON_CH27_PERI_ID_MASK_0

Offset: 0xec

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_HYPER_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

CH27_PERI_ID_MASK

GPCDMA_COMMON_CH28_PERI_ID_MASK_0

Offset: 0xf0

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_HYPER_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

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Bit Reset Description

31:0 0x0

CH28_PERI_ID_MASK

GPCDMA_COMMON_CH29_PERI_ID_MASK_0

Offset: 0xf4

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_HYPER_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

CH29_PERI_ID_MASK

GPCDMA_COMMON_CH30_PERI_ID_MASK_0

Offset: 0xf8

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_HYPER_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

CH30_PERI_ID_MASK

GPCDMA_COMMON_CH31_PERI_ID_MASK_0

Offset: 0xfc

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_HYPER_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

CH31_PERI_ID_MASK

GPCDMA_COMMON_PER0_PERI_ADDR_0

Offset: 0x100

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_HYPER_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

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Bit Reset Description

31:16 0x0

PER0_PERI_START_ADDR

15:0 0x0

PER0_PERI_OFFSET

GPCDMA_COMMON_PER1_PERI_ADDR_0

Offset: 0x104

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_HYPER_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:16 0x0

PER1_PERI_START_ADDR

15:0 0x0

PER1_PERI_OFFSET

GPCDMA_COMMON_PER2_PERI_ADDR_0

Offset: 0x108

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_HYPER_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:16 0x0

PER2_PERI_START_ADDR

15:0 0x0

PER2_PERI_OFFSET

GPCDMA_COMMON_PER3_PERI_ADDR_0

Offset: 0x10c

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_HYPER_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:16 0x0

PER3_PERI_START_ADDR

15:0 0x0

PER3_PERI_OFFSET

GPCDMA_COMMON_PER5_PERI_ADDR_0

Offset: 0x110

Read/Write: R/W

Parity Protection: N

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SCR Protection: SCR_HYPER_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:16 0x0

PER5_PERI_START_ADDR

15:0 0x0

PER5_PERI_OFFSET

GPCDMA_COMMON_PER6_PERI_ADDR_0

Offset: 0x114

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_HYPER_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:16 0x0

PER6_PERI_START_ADDR

15:0 0x0

PER6_PERI_OFFSET

GPCDMA_COMMON_PER8_PERI_ADDR_0

Offset: 0x118

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_HYPER_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:16 0x0

PER8_PERI_START_ADDR

15:0 0x0

PER8_PERI_OFFSET

GPCDMA_COMMON_PER9_PERI_ADDR_0

Offset: 0x11c

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_HYPER_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:16 0x0

PER9_PERI_START_ADDR

15:0 0x0

PER9_PERI_OFFSET

GPCDMA_COMMON_PER12_PERI_ADDR_0

Offset: 0x120

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Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_HYPER_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:16 0x0

PER12_PERI_START_ADDR

15:0 0x0

PER12_PERI_OFFSET

GPCDMA_COMMON_PER13_PERI_ADDR_0

Offset: 0x124

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_HYPER_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:16 0x0

PER13_PERI_START_ADDR

15:0 0x0

PER13_PERI_OFFSET

GPCDMA_COMMON_PER15_PERI_ADDR_0

Offset: 0x128

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_HYPER_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:16 0x0

PER15_PERI_START_ADDR

15:0 0x0

PER15_PERI_OFFSET

GPCDMA_COMMON_PER16_PERI_ADDR_0

Offset: 0x12c

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_HYPER_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:16 0x0

PER16_PERI_START_ADDR

15:0 0x0

PER16_PERI_OFFSET

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GPCDMA_COMMON_PER17_PERI_ADDR_0

Offset: 0x130

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_HYPER_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:16 0x0

PER17_PERI_START_ADDR

15:0 0x0

PER17_PERI_OFFSET

GPCDMA_COMMON_PER19_PERI_ADDR_0

Offset: 0x134

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_HYPER_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:16 0x0

PER19_PERI_START_ADDR

15:0 0x0

PER19_PERI_OFFSET

GPCDMA_COMMON_PER20_PERI_ADDR_0

Offset: 0x138

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_HYPER_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:16 0x0

PER20_PERI_START_ADDR

15:0 0x0

PER20_PERI_OFFSET

GPCDMA_COMMON_PER21_PERI_ADDR_0

Offset: 0x13c

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_HYPER_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

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Bit Reset Description

31:16 0x0

PER21_PERI_START_ADDR

15:0 0x0

PER21_PERI_OFFSET

GPCDMA_COMMON_PER22_PERI_ADDR_0

Offset: 0x140

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_HYPER_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:16 0x0

PER22_PERI_START_ADDR

15:0 0x0

PER22_PERI_OFFSET

GPCDMA_COMMON_PER23_PERI_ADDR_0

Offset: 0x144

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_HYPER_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:16 0x0

PER23_PERI_START_ADDR

15:0 0x0

PER23_PERI_OFFSET

GPCDMA_COMMON_PER24_PERI_ADDR_0

Offset: 0x148

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_HYPER_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:16 0x0

PER24_PERI_START_ADDR

15:0 0x0

PER24_PERI_OFFSET

GPCDMA_COMMON_PER26_PERI_ADDR_0

Offset: 0x14c

Read/Write: R/W

Parity Protection: N

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SCR Protection: SCR_HYPER_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:16 0x0

PER26_PERI_START_ADDR

15:0 0x0

PER26_PERI_OFFSET

GPCDMA_COMMON_PER27_PERI_ADDR_0

Offset: 0x150

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_HYPER_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:16 0x0

PER27_PERI_START_ADDR

15:0 0x0

PER27_PERI_OFFSET

GPCDMA_COMMON_PER30_PERI_ADDR_0

Offset: 0x154

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_HYPER_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:16 0x0

PER30_PERI_START_ADDR

15:0 0x0

PER30_PERI_OFFSET

GPCDMA_COMMON_PER31_PERI_ADDR_0

Offset: 0x158

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_HYPER_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:16 0x0

PER31_PERI_START_ADDR

15:0 0x0

PER31_PERI_OFFSET

GPCDMA_COMMON_CH0_STREAM_ID0_MASK_0

Offset: 0x180

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Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_HYPER_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

CH0_STREAM_ID0_MASK

GPCDMA_COMMON_CH1_STREAM_ID0_MASK_0

Offset: 0x184

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_HYPER_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

CH1_STREAM_ID0_MASK

GPCDMA_COMMON_CH2_STREAM_ID0_MASK_0

Offset: 0x188

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_HYPER_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

CH2_STREAM_ID0_MASK

GPCDMA_COMMON_CH3_STREAM_ID0_MASK_0

Offset: 0x18c

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_HYPER_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

CH3_STREAM_ID0_MASK

GPCDMA_COMMON_CH4_STREAM_ID0_MASK_0

Offset: 0x190

Read/Write: R/W

Parity Protection: N

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SCR Protection: SCR_HYPER_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

CH4_STREAM_ID0_MASK

GPCDMA_COMMON_CH5_STREAM_ID0_MASK_0

Offset: 0x194

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_HYPER_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

CH5_STREAM_ID0_MASK

GPCDMA_COMMON_CH6_STREAM_ID0_MASK_0

Offset: 0x198

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_HYPER_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

CH6_STREAM_ID0_MASK

GPCDMA_COMMON_CH7_STREAM_ID0_MASK_0

Offset: 0x19c

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_HYPER_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

CH7_STREAM_ID0_MASK

GPCDMA_COMMON_CH8_STREAM_ID0_MASK_0

Offset: 0x1a0

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_HYPER_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

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Bit Reset Description

31:0 0x0

CH8_STREAM_ID0_MASK

GPCDMA_COMMON_CH9_STREAM_ID0_MASK_0

Offset: 0x1a4

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_HYPER_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

CH9_STREAM_ID0_MASK

GPCDMA_COMMON_CH10_STREAM_ID0_MASK_0

Offset: 0x1a8

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_HYPER_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

CH10_STREAM_ID0_MASK

GPCDMA_COMMON_CH11_STREAM_ID0_MASK_0

Offset: 0x1ac

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_HYPER_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

CH11_STREAM_ID0_MASK

GPCDMA_COMMON_CH12_STREAM_ID0_MASK_0

Offset: 0x1b0

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_HYPER_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

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Bit Reset Description

31:0 0x0

CH12_STREAM_ID0_MASK

GPCDMA_COMMON_CH13_STREAM_ID0_MASK_0

Offset: 0x1b4

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_HYPER_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

CH13_STREAM_ID0_MASK

GPCDMA_COMMON_CH14_STREAM_ID0_MASK_0

Offset: 0x1b8

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_HYPER_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

CH14_STREAM_ID0_MASK

GPCDMA_COMMON_CH15_STREAM_ID0_MASK_0

Offset: 0x1bc

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_HYPER_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

CH15_STREAM_ID0_MASK

GPCDMA_COMMON_CH16_STREAM_ID0_MASK_0

Offset: 0x1c0

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_HYPER_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

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Bit Reset Description

31:0 0x0

CH16_STREAM_ID0_MASK

GPCDMA_COMMON_CH17_STREAM_ID0_MASK_0

Offset: 0x1c4

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_HYPER_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

CH17_STREAM_ID0_MASK

GPCDMA_COMMON_CH18_STREAM_ID0_MASK_0

Offset: 0x1c8

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_HYPER_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

CH18_STREAM_ID0_MASK

GPCDMA_COMMON_CH19_STREAM_ID0_MASK_0

Offset: 0x1cc

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_HYPER_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

CH19_STREAM_ID0_MASK

GPCDMA_COMMON_CH20_STREAM_ID0_MASK_0

Offset: 0x1d0

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_HYPER_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

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Bit Reset Description

31:0 0x0

CH20_STREAM_ID0_MASK

GPCDMA_COMMON_CH21_STREAM_ID0_MASK_0

Offset: 0x1d4

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_HYPER_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

CH21_STREAM_ID0_MASK

GPCDMA_COMMON_CH22_STREAM_ID0_MASK_0

Offset: 0x1d8

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_HYPER_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

CH22_STREAM_ID0_MASK

GPCDMA_COMMON_CH23_STREAM_ID0_MASK_0

Offset: 0x1dc

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_HYPER_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

CH23_STREAM_ID0_MASK

GPCDMA_COMMON_CH24_STREAM_ID0_MASK_0

Offset: 0x1e0

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_HYPER_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

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Bit Reset Description

31:0 0x0

CH24_STREAM_ID0_MASK

GPCDMA_COMMON_CH25_STREAM_ID0_MASK_0

Offset: 0x1e4

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_HYPER_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

CH25_STREAM_ID0_MASK

GPCDMA_COMMON_CH26_STREAM_ID0_MASK_0

Offset: 0x1e8

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_HYPER_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

CH26_STREAM_ID0_MASK

GPCDMA_COMMON_CH27_STREAM_ID0_MASK_0

Offset: 0x1ec

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_HYPER_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

CH27_STREAM_ID0_MASK

GPCDMA_COMMON_CH28_STREAM_ID0_MASK_0

Offset: 0x1f0

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_HYPER_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

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Bit Reset Description

31:0 0x0

CH28_STREAM_ID0_MASK

GPCDMA_COMMON_CH29_STREAM_ID0_MASK_0

Offset: 0x1f4

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_HYPER_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

CH29_STREAM_ID0_MASK

GPCDMA_COMMON_CH30_STREAM_ID0_MASK_0

Offset: 0x1f8

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_HYPER_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

CH30_STREAM_ID0_MASK

GPCDMA_COMMON_CH31_STREAM_ID0_MASK_0

Offset: 0x1fc

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_HYPER_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

CH31_STREAM_ID0_MASK

GPCDMA_COMMON_CH0_STREAM_ID1_MASK_0

Offset: 0x200

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_HYPER_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

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Bit Reset Description

31:0 0x0

CH0_STREAM_ID1_MASK

GPCDMA_COMMON_CH1_STREAM_ID1_MASK_0

Offset: 0x204

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_HYPER_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

CH1_STREAM_ID1_MASK

GPCDMA_COMMON_CH2_STREAM_ID1_MASK_0

Offset: 0x208

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_HYPER_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

CH2_STREAM_ID1_MASK

GPCDMA_COMMON_CH3_STREAM_ID1_MASK_0

Offset: 0x20c

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_HYPER_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

CH3_STREAM_ID1_MASK

GPCDMA_COMMON_CH4_STREAM_ID1_MASK_0

Offset: 0x210

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_HYPER_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

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Bit Reset Description

31:0 0x0

CH4_STREAM_ID1_MASK

GPCDMA_COMMON_CH5_STREAM_ID1_MASK_0

Offset: 0x214

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_HYPER_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

CH5_STREAM_ID1_MASK

GPCDMA_COMMON_CH6_STREAM_ID1_MASK_0

Offset: 0x218

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_HYPER_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

CH6_STREAM_ID1_MASK

GPCDMA_COMMON_CH7_STREAM_ID1_MASK_0

Offset: 0x21c

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_HYPER_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

CH7_STREAM_ID1_MASK

GPCDMA_COMMON_CH8_STREAM_ID1_MASK_0

Offset: 0x220

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_HYPER_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

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Bit Reset Description

31:0 0x0

CH8_STREAM_ID1_MASK

GPCDMA_COMMON_CH9_STREAM_ID1_MASK_0

Offset: 0x224

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_HYPER_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

CH9_STREAM_ID1_MASK

GPCDMA_COMMON_CH10_STREAM_ID1_MASK_0

Offset: 0x228

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_HYPER_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

CH10_STREAM_ID1_MASK

GPCDMA_COMMON_CH11_STREAM_ID1_MASK_0

Offset: 0x22c

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_HYPER_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

CH11_STREAM_ID1_MASK

GPCDMA_COMMON_CH12_STREAM_ID1_MASK_0

Offset: 0x230

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_HYPER_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

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Bit Reset Description

31:0 0x0

CH12_STREAM_ID1_MASK

GPCDMA_COMMON_CH13_STREAM_ID1_MASK_0

Offset: 0x234

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_HYPER_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

CH13_STREAM_ID1_MASK

GPCDMA_COMMON_CH14_STREAM_ID1_MASK_0

Offset: 0x238

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_HYPER_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

CH14_STREAM_ID1_MASK

GPCDMA_COMMON_CH15_STREAM_ID1_MASK_0

Offset: 0x23c

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_HYPER_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

CH15_STREAM_ID1_MASK

GPCDMA_COMMON_CH16_STREAM_ID1_MASK_0

Offset: 0x240

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_HYPER_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

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Bit Reset Description

31:0 0x0

CH16_STREAM_ID1_MASK

GPCDMA_COMMON_CH17_STREAM_ID1_MASK_0

Offset: 0x244

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_HYPER_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

CH17_STREAM_ID1_MASK

GPCDMA_COMMON_CH18_STREAM_ID1_MASK_0

Offset: 0x248

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_HYPER_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

CH18_STREAM_ID1_MASK

GPCDMA_COMMON_CH19_STREAM_ID1_MASK_0

Offset: 0x24c

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_HYPER_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

CH19_STREAM_ID1_MASK

GPCDMA_COMMON_CH20_STREAM_ID1_MASK_0

Offset: 0x250

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_HYPER_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

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Bit Reset Description

31:0 0x0

CH20_STREAM_ID1_MASK

GPCDMA_COMMON_CH21_STREAM_ID1_MASK_0

Offset: 0x254

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_HYPER_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

CH21_STREAM_ID1_MASK

GPCDMA_COMMON_CH22_STREAM_ID1_MASK_0

Offset: 0x258

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_HYPER_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

CH22_STREAM_ID1_MASK

GPCDMA_COMMON_CH23_STREAM_ID1_MASK_0

Offset: 0x25c

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_HYPER_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

CH23_STREAM_ID1_MASK

GPCDMA_COMMON_CH24_STREAM_ID1_MASK_0

Offset: 0x260

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_HYPER_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

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Bit Reset Description

31:0 0x0

CH24_STREAM_ID1_MASK

GPCDMA_COMMON_CH25_STREAM_ID1_MASK_0

Offset: 0x264

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_HYPER_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

CH25_STREAM_ID1_MASK

GPCDMA_COMMON_CH26_STREAM_ID1_MASK_0

Offset: 0x268

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_HYPER_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

CH26_STREAM_ID1_MASK

GPCDMA_COMMON_CH27_STREAM_ID1_MASK_0

Offset: 0x26c

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_HYPER_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

CH27_STREAM_ID1_MASK

GPCDMA_COMMON_CH28_STREAM_ID1_MASK_0

Offset: 0x270

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_HYPER_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

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Bit Reset Description

31:0 0x0

CH28_STREAM_ID1_MASK

GPCDMA_COMMON_CH29_STREAM_ID1_MASK_0

Offset: 0x274

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_HYPER_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

CH29_STREAM_ID1_MASK

GPCDMA_COMMON_CH30_STREAM_ID1_MASK_0

Offset: 0x278

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_HYPER_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

CH30_STREAM_ID1_MASK

GPCDMA_COMMON_CH31_STREAM_ID1_MASK_0

Offset: 0x27c

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_HYPER_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

CH31_STREAM_ID1_MASK

GPCDMA_COMMON_CH0_STREAM_ID2_MASK_0

Offset: 0x280

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_HYPER_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

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Bit Reset Description

31:0 0x0

CH0_STREAM_ID2_MASK

GPCDMA_COMMON_CH1_STREAM_ID2_MASK_0

Offset: 0x284

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_HYPER_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

CH1_STREAM_ID2_MASK

GPCDMA_COMMON_CH2_STREAM_ID2_MASK_0

Offset: 0x288

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_HYPER_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

CH2_STREAM_ID2_MASK

GPCDMA_COMMON_CH3_STREAM_ID2_MASK_0

Offset: 0x28c

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_HYPER_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

CH3_STREAM_ID2_MASK

GPCDMA_COMMON_CH4_STREAM_ID2_MASK_0

Offset: 0x290

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_HYPER_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

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Bit Reset Description

31:0 0x0

CH4_STREAM_ID2_MASK

GPCDMA_COMMON_CH5_STREAM_ID2_MASK_0

Offset: 0x294

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_HYPER_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

CH5_STREAM_ID2_MASK

GPCDMA_COMMON_CH6_STREAM_ID2_MASK_0

Offset: 0x298

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_HYPER_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

CH6_STREAM_ID2_MASK

GPCDMA_COMMON_CH7_STREAM_ID2_MASK_0

Offset: 0x29c

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_HYPER_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

CH7_STREAM_ID2_MASK

GPCDMA_COMMON_CH8_STREAM_ID2_MASK_0

Offset: 0x2a0

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_HYPER_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

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Bit Reset Description

31:0 0x0

CH8_STREAM_ID2_MASK

GPCDMA_COMMON_CH9_STREAM_ID2_MASK_0

Offset: 0x2a4

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_HYPER_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

CH9_STREAM_ID2_MASK

GPCDMA_COMMON_CH10_STREAM_ID2_MASK_0

Offset: 0x2a8

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_HYPER_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

CH10_STREAM_ID2_MASK

GPCDMA_COMMON_CH11_STREAM_ID2_MASK_0

Offset: 0x2ac

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_HYPER_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

CH11_STREAM_ID2_MASK

GPCDMA_COMMON_CH12_STREAM_ID2_MASK_0

Offset: 0x2b0

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_HYPER_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

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Bit Reset Description

31:0 0x0

CH12_STREAM_ID2_MASK

GPCDMA_COMMON_CH13_STREAM_ID2_MASK_0

Offset: 0x2b4

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_HYPER_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

CH13_STREAM_ID2_MASK

GPCDMA_COMMON_CH14_STREAM_ID2_MASK_0

Offset: 0x2b8

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_HYPER_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

CH14_STREAM_ID2_MASK

GPCDMA_COMMON_CH15_STREAM_ID2_MASK_0

Offset: 0x2bc

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_HYPER_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

CH15_STREAM_ID2_MASK

GPCDMA_COMMON_CH16_STREAM_ID2_MASK_0

Offset: 0x2c0

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_HYPER_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

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Bit Reset Description

31:0 0x0

CH16_STREAM_ID2_MASK

GPCDMA_COMMON_CH17_STREAM_ID2_MASK_0

Offset: 0x2c4

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_HYPER_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

CH17_STREAM_ID2_MASK

GPCDMA_COMMON_CH18_STREAM_ID2_MASK_0

Offset: 0x2c8

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_HYPER_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

CH18_STREAM_ID2_MASK

GPCDMA_COMMON_CH19_STREAM_ID2_MASK_0

Offset: 0x2cc

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_HYPER_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

CH19_STREAM_ID2_MASK

GPCDMA_COMMON_CH20_STREAM_ID2_MASK_0

Offset: 0x2d0

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_HYPER_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

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Bit Reset Description

31:0 0x0

CH20_STREAM_ID2_MASK

GPCDMA_COMMON_CH21_STREAM_ID2_MASK_0

Offset: 0x2d4

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_HYPER_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

CH21_STREAM_ID2_MASK

GPCDMA_COMMON_CH22_STREAM_ID2_MASK_0

Offset: 0x2d8

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_HYPER_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

CH22_STREAM_ID2_MASK

GPCDMA_COMMON_CH23_STREAM_ID2_MASK_0

Offset: 0x2dc

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_HYPER_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

CH23_STREAM_ID2_MASK

GPCDMA_COMMON_CH24_STREAM_ID2_MASK_0

Offset: 0x2e0

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_HYPER_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

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Bit Reset Description

31:0 0x0

CH24_STREAM_ID2_MASK

GPCDMA_COMMON_CH25_STREAM_ID2_MASK_0

Offset: 0x2e4

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_HYPER_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

CH25_STREAM_ID2_MASK

GPCDMA_COMMON_CH26_STREAM_ID2_MASK_0

Offset: 0x2e8

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_HYPER_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

CH26_STREAM_ID2_MASK

GPCDMA_COMMON_CH27_STREAM_ID2_MASK_0

Offset: 0x2ec

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_HYPER_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

CH27_STREAM_ID2_MASK

GPCDMA_COMMON_CH28_STREAM_ID2_MASK_0

Offset: 0x2f0

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_HYPER_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

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Bit Reset Description

31:0 0x0

CH28_STREAM_ID2_MASK

GPCDMA_COMMON_CH29_STREAM_ID2_MASK_0

Offset: 0x2f4

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_HYPER_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

CH29_STREAM_ID2_MASK

GPCDMA_COMMON_CH30_STREAM_ID2_MASK_0

Offset: 0x2f8

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_HYPER_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

CH30_STREAM_ID2_MASK

GPCDMA_COMMON_CH31_STREAM_ID2_MASK_0

Offset: 0x2fc

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_HYPER_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

CH31_STREAM_ID2_MASK

GPCDMA_COMMON_CH0_STREAM_ID3_MASK_0

Offset: 0x300

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_HYPER_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

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Bit Reset Description

31:0 0x0

CH0_STREAM_ID3_MASK

GPCDMA_COMMON_CH1_STREAM_ID3_MASK_0

Offset: 0x304

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_HYPER_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

CH1_STREAM_ID3_MASK

GPCDMA_COMMON_CH2_STREAM_ID3_MASK_0

Offset: 0x308

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_HYPER_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

CH2_STREAM_ID3_MASK

GPCDMA_COMMON_CH3_STREAM_ID3_MASK_0

Offset: 0x30c

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_HYPER_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

CH3_STREAM_ID3_MASK

GPCDMA_COMMON_CH4_STREAM_ID3_MASK_0

Offset: 0x310

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_HYPER_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

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Bit Reset Description

31:0 0x0

CH4_STREAM_ID3_MASK

GPCDMA_COMMON_CH5_STREAM_ID3_MASK_0

Offset: 0x314

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_HYPER_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

CH5_STREAM_ID3_MASK

GPCDMA_COMMON_CH6_STREAM_ID3_MASK_0

Offset: 0x318

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_HYPER_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

CH6_STREAM_ID3_MASK

GPCDMA_COMMON_CH7_STREAM_ID3_MASK_0

Offset: 0x31c

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_HYPER_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

CH7_STREAM_ID3_MASK

GPCDMA_COMMON_CH8_STREAM_ID3_MASK_0

Offset: 0x320

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_HYPER_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

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Bit Reset Description

31:0 0x0

CH8_STREAM_ID3_MASK

GPCDMA_COMMON_CH9_STREAM_ID3_MASK_0

Offset: 0x324

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_HYPER_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

CH9_STREAM_ID3_MASK

GPCDMA_COMMON_CH10_STREAM_ID3_MASK_0

Offset: 0x328

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_HYPER_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

CH10_STREAM_ID3_MASK

GPCDMA_COMMON_CH11_STREAM_ID3_MASK_0

Offset: 0x32c

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_HYPER_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

CH11_STREAM_ID3_MASK

GPCDMA_COMMON_CH12_STREAM_ID3_MASK_0

Offset: 0x330

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_HYPER_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

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Bit Reset Description

31:0 0x0

CH12_STREAM_ID3_MASK

GPCDMA_COMMON_CH13_STREAM_ID3_MASK_0

Offset: 0x334

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_HYPER_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

CH13_STREAM_ID3_MASK

GPCDMA_COMMON_CH14_STREAM_ID3_MASK_0

Offset: 0x338

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_HYPER_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

CH14_STREAM_ID3_MASK

GPCDMA_COMMON_CH15_STREAM_ID3_MASK_0

Offset: 0x33c

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_HYPER_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

CH15_STREAM_ID3_MASK

GPCDMA_COMMON_CH16_STREAM_ID3_MASK_0

Offset: 0x340

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_HYPER_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

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Bit Reset Description

31:0 0x0

CH16_STREAM_ID3_MASK

GPCDMA_COMMON_CH17_STREAM_ID3_MASK_0

Offset: 0x344

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_HYPER_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

CH17_STREAM_ID3_MASK

GPCDMA_COMMON_CH18_STREAM_ID3_MASK_0

Offset: 0x348

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_HYPER_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

CH18_STREAM_ID3_MASK

GPCDMA_COMMON_CH19_STREAM_ID3_MASK_0

Offset: 0x34c

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_HYPER_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

CH19_STREAM_ID3_MASK

GPCDMA_COMMON_CH20_STREAM_ID3_MASK_0

Offset: 0x350

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_HYPER_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

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Bit Reset Description

31:0 0x0

CH20_STREAM_ID3_MASK

GPCDMA_COMMON_CH21_STREAM_ID3_MASK_0

Offset: 0x354

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_HYPER_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

CH21_STREAM_ID3_MASK

GPCDMA_COMMON_CH22_STREAM_ID3_MASK_0

Offset: 0x358

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_HYPER_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

CH22_STREAM_ID3_MASK

GPCDMA_COMMON_CH23_STREAM_ID3_MASK_0

Offset: 0x35c

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_HYPER_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

CH23_STREAM_ID3_MASK

GPCDMA_COMMON_CH24_STREAM_ID3_MASK_0

Offset: 0x360

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_HYPER_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

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Bit Reset Description

31:0 0x0

CH24_STREAM_ID3_MASK

GPCDMA_COMMON_CH25_STREAM_ID3_MASK_0

Offset: 0x364

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_HYPER_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

CH25_STREAM_ID3_MASK

GPCDMA_COMMON_CH26_STREAM_ID3_MASK_0

Offset: 0x368

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_HYPER_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

CH26_STREAM_ID3_MASK

GPCDMA_COMMON_CH27_STREAM_ID3_MASK_0

Offset: 0x36c

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_HYPER_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

CH27_STREAM_ID3_MASK

GPCDMA_COMMON_CH28_STREAM_ID3_MASK_0

Offset: 0x370

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_HYPER_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

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Bit Reset Description

31:0 0x0

CH28_STREAM_ID3_MASK

GPCDMA_COMMON_CH29_STREAM_ID3_MASK_0

Offset: 0x374

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_HYPER_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

CH29_STREAM_ID3_MASK

GPCDMA_COMMON_CH30_STREAM_ID3_MASK_0

Offset: 0x378

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_HYPER_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

CH30_STREAM_ID3_MASK

GPCDMA_COMMON_CH31_STREAM_ID3_MASK_0

Offset: 0x37c

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_HYPER_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

CH31_STREAM_ID3_MASK

GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0

Offset: 0x380

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_HYPER_0

Reset: 0xffffffff (0b1111,1111,1111,1111,1111,1111,1111,1111)

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Bit Reset Description

31 0x1

CH31

30 0x1

CH30

29 0x1

CH29

28 0x1

CH28

27 0x1

CH27

26 0x1

CH26

25 0x1

CH25

24 0x1

CH24

23 0x1

CH23

22 0x1

CH22

21 0x1

CH21

20 0x1

CH20

19 0x1

CH19

18 0x1

CH18

17 0x1

CH17

16 0x1

CH16

15 0x1

CH15

14 0x1

CH14

13 0x1

CH13

12 0x1

CH12

11 0x1

CH11

10 0x1

CH10

9 0x1

CH9

8 0x1

CH8

7 0x1

CH7

6 0x1

CH6

5 0x1

CH5

4 0x1

CH4

3 0x1

CH3

2 0x1

CH2

1 0x1

CH1

0 0x1

CH0

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GPCDMA_COMMON_DMA_ICG_EN_OVERRIDE_0

Offset: 0x384

Read/Write: R/W

Parity Protection: N

Reset: 0x00000000 (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxx0)

Bit Reset Description

0 0x0

DMA_ICG_EN_OVERRIDE

GPCDMA_COMMON_DMA_ACTIVE_0

Offset: 0x388

Read/Write: RO

Parity Protection: N

Reset: 0x00000000 (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,0000)

Bit Reset Description

3 0x0

DMA_IO_ACTIVE

2 0x0

DMA_MC_ACTIVE

1 0x0

DMA_IO_MC_ACTIVE

0 0x0

DMA_ACTIVE

GPCDMA_COMMON_SAFETY_LOGIC_CLK_DISABLE_0

Offset: 0x390

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_SAFETY_0

Reset: 0x00000002 (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xx10)

Bit Reset Description

1:0 0x2

SAFETY_LOGIC_CLK_DISABLE

GPCDMA_ERRCOLLATOR_FEATURE_0

Offset: 0xff00

Read/Write: RO

Parity Protection: N

SCR Protection: EC_SCR_0

Reset: 0x000c0001 (0b0000,0000,0000,1100,xxxx,xxxx,xx00,0001)

Bit Reset Description

31:16 0xc

NUM_ERR:

Number of errors connected to this collator. This is passed as a build time option to the plugin

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Bit Reset Description

5:0 0x1

NUM_ERR_SLICES:

Number of error slices supported by this error collator, does not include the GlobalSpace and is

derived by ceil (NUM_ERR/32). Software shall first read this register to determine the number of slices

and read the required number of Error_Status registers .

GPCDMA_ERRCOLLATOR_SWRESET_0

Offset: 0xff04

Read/Write: WO

Parity Protection: N

SCR Protection: EC_SCR_0

Reset: 0x00000000 (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxx0)

Bit Reset Description

0 0x0

SWRST:

1'b1 : Issue a Software reset to the Error Collator. This will reset all the registers(Except SCR), counters

and logic of the Error Collator. Software can use this bit to flush errors logged into the error collator

for example, after Boot, SC7/8 exit.

1'b0 : Do nothing, reset value.

This bit is auto-cleared.

GPCDMA_ERRCOLLATOR_MISSIONERR_TYPE_0

Offset: 0xff08

Read/Write: RO

Parity Protection: N

SCR Protection: EC_SCR_0

Reset: 0x00000005 (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xx00,0101)

Bit Reset Description

5:0

0x5

CODE:

This register indicates the fault code of the error line based on the value of MISSIONERR_INDEX Register.

This can be used by a fault handling agent to triage an error without requiring device-specific code.The

possible values of this field are:

6'd0 : None

6'd1 : Parity Error on internal data path

6'd2 : ECC SEC Error on internal data path

6'd3 : ECC DED Error on internal data path

6'd4 : Comparator Error

6'd5 : Register Parity Error

6'd6 : Parity Error from on-chip SRAM/FIFO

6'd7 : ECC SEC Error from on-chip SRAM/FIFO

6'd8 : ECC DED Error from on-chip SRAM/FIFO

6'd9 : Clock Monitor Error

6'd10 : Voltage Error

6'd11 : Temperature Error

6'd16 : Software Correctable Error

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Bit Reset Description

6'd17 : Software Un-Correctable Error

6'd32 : Other Hardware Correctable Error

6'd33 : Other Hardware Uncorrectable Error

All other values : Reserved for future use.

GPCDMA_ERRCOLLATOR_CURRENT_COUNTER_VALUE_0

Offset: 0xff0c

Read/Write: RO

Parity Protection: N

SCR Protection: EC_SCR_0

Reset: 0x00000000 (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxx0,0000,0000)

Bit Reset Description

8:0 0x0

VALUE:

Provides the current value of the counter corresponding to the error in MissionErr_Index Register.

Default provides the value of error 0 counter.

Bit[8] is the overflow bit post which the counter saturates and does not counter further.

GPCDMA_ERRCOLLATOR_MISSIONERR_INDEX_0

Offset: 0xff14

Read/Write: R/W

Parity Protection: Y

SCR Protection: EC_SCR_0

Reset: 0x00000000 (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,0000)

Bit Reset Description

3:0 0x0

IDX:

BINARY Encoded. For error number 32, register should be programmed with value 0x20.

Write to this register with Error number will update:

- MISSIONERR_TYPE Register with the Error-Code for the Error.

- CURRENT_COUNTER_VALUE Register with the error's SEC/DED Counter.

- MISSIONERR_USERVALUE with value of the first error_<i>_user signal.

Software can use this to trage the error.

number shall update the MISSIONERR_TYPE register with the error code and the Current_Counter_Value

with the value of the errors SEC/DED counter. SW can use this register to triage the error.

GPCDMA_ERRCOLLATOR_CORRECTABLE_THRESHOLD_0

Offset: 0xff18

Read/Write: R/W

Parity Protection: Y

SCR Protection: EC_SCR_0

Reset: 0x000000ff (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,1111,1111)

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Bit Reset Description

7:0 0xff

COUNT:

Threshold value for all SEC Fault Reporting Units connected to this error collator.

SEC Errors are logged once the threshold is reached and the overflow bit is set.

7'b0 : Log SEC error after receiving 1 Error.

7'b1 : Log SEC error after receiving 2 Errors.

...

7'bFF : Log SEC error after receiving 256 Errors.

GPCDMA_ERRCOLLATOR_MISSIONERR_INJECT_UNLOCK_0

Offset: 0xff1c

Read/Write: R/W

Parity Protection: N

SCR Protection: EC_SCR_0

Reset: 0x00000000 (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,0000,0000)

Bit Reset Description

7:0 0x0

VALUE:

Writes to ERRSLICE_XXX_MISSIONERR_INJECT registers are disabled until this register is written with a

value of 0xE1.

This is to prevent an inadvertent safety error injection in the safety plugin due to:

1. A fault on ERRSLICE_XXX_MISSIONERR_INJECT register itself.

2. Erroneous Software.

The register shall be written with a value of 0x0 to reestablish the lock after user has completed the error

injection testing.

0xE1 : Unlock the MISSIONERR_INJECT Register

0x0 : Lock the MISSIONERR_INJECT Register

= LOCK0

= UNLOCK225

GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_ENABLE_0

Offset: 0xff30

Read/Write: R/W

Parity Protection: Y

SCR Protection: EC_SCR_0

Reset: 0x00001fff (0bxxxx,xxxx,xxxx,xxxx,xxx1,1111,1111,1111)

Bit Reset Description

0x1

ERR12:

1'b1 -> Enable Mission Error Reporting for Comparator Error from sys0_0.u_NV_gpcdma.u_regwrap.clkdis

1'b0 -> Disable Mission Error Reporting for Comparator Error from sys0_0.u_NV_gpcdma.u_regwrap.clkdis

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Bit Reset Description

= DISABLE0

= ENABLE1

11 0x1

ERR11:

1'b1 -> Enable Mission Error Reporting for Register Parity Error from sys0_0.u_NV_gpcdma.

u_safety_plugins.u_err_collator_scrwrap

1'b0 -> Disable Mission Error Reporting for Register Parity Error from sys0_0.u_NV_gpcdma.

u_safety_plugins.u_err_collator_scrwrap

= DISABLE0

= ENABLE1

10 0x1

ERR10:

1'b1 -> Enable Mission Error Reporting for ECC DED Error from on-chip SRAM/FIFO from sys0_0.

u_NV_gpcdma.u_ramwrap

1'b0 -> Disable Mission Error Reporting for ECC DED Error from on-chip SRAM/FIFO from sys0_0.

u_NV_gpcdma.u_ramwrap

= DISABLE0

= ENABLE1

9 0x1

ERR9:

1'b1 -> Enable Mission Error Reporting for ECC DED Error from on-chip SRAM/FIFO from sys0_0.

u_NV_gpcdma.u_ramwrap

1'b0 -> Disable Mission Error Reporting for ECC DED Error from on-chip SRAM/FIFO from sys0_0.

u_NV_gpcdma.u_ramwrap

= DISABLE0

= ENABLE1

8 0x1

ERR8:

1'b1 -> Enable Mission Error Reporting for ECC SEC Error from on-chip SRAM/FIFO from sys0_0.

u_NV_gpcdma.u_ramwrap

1'b0 -> Disable Mission Error Reporting for ECC SEC Error from on-chip SRAM/FIFO from sys0_0.

u_NV_gpcdma.u_ramwrap

= DISABLE0

= ENABLE1

7 0x1

ERR7:

1'b1 -> Enable Mission Error Reporting for ECC SEC Error from on-chip SRAM/FIFO from sys0_0.

u_NV_gpcdma.u_ramwrap

1'b0 -> Disable Mission Error Reporting for ECC SEC Error from on-chip SRAM/FIFO from sys0_0.

u_NV_gpcdma.u_ramwrap

= DISABLE0

= ENABLE1

0x1

ERR6:

1'b1 -> Enable Mission Error Reporting for Comparator Error from sys0_0.u_NV_gpcdma.u_ramintf

1'b0 -> Disable Mission Error Reporting for Comparator Error from sys0_0.u_NV_gpcdma.u_ramintf

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Bit Reset Description

= DISABLE0

= ENABLE1

5 0x1

ERR5:

1'b1 -> Enable Mission Error Reporting for Comparator Error from sys0_0.u_NV_gpcdma.u_regwrap.activity

1'b0 -> Disable Mission Error Reporting for Comparator Error from sys0_0.u_NV_gpcdma.u_regwrap.activity

= DISABLE0

= ENABLE1

4 0x1

ERR4:

1'b1 -> Enable Mission Error Reporting for Comparator Error from sys0_0.u_NV_gpcdma.u_regwrap.intbus

1'b0 -> Disable Mission Error Reporting for Comparator Error from sys0_0.u_NV_gpcdma.u_regwrap.intbus

= DISABLE0

= ENABLE1

3 0x1

ERR3:

1'b1 -> Enable Mission Error Reporting for Comparator Error from sys0_0.u_NV_gpcdma.u_regwrap

1'b0 -> Disable Mission Error Reporting for Comparator Error from sys0_0.u_NV_gpcdma.u_regwrap

= DISABLE0

= ENABLE1

2 0x1

ERR2:

1'b1 -> Enable Mission Error Reporting for Comparator Error from sys0_0.u_NV_gpcdma.u_io_axi

1'b0 -> Disable Mission Error Reporting for Comparator Error from sys0_0.u_NV_gpcdma.u_io_axi

= DISABLE0

= ENABLE1

1 0x1

ERR1:

1'b1 -> Enable Mission Error Reporting for Comparator Error from sys0_0.u_NV_gpcdma.u_mc_axi

1'b0 -> Disable Mission Error Reporting for Comparator Error from sys0_0.u_NV_gpcdma.u_mc_axi

= DISABLE0

= ENABLE1

0 0x1

ERR0:

1'b1 -> Enable Mission Error Reporting for Register Parity Error from NV_GPCDMA_err_collator

1'b0 -> Disable Mission Error Reporting for Register Parity Error from NV_GPCDMA_err_collator

= DISABLE0

= ENABLE1

GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_FORCE_0

Offset: 0xff34

Read/Write: WO

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Parity Protection: N

SCR Protection: EC_SCR_0

Reset: 0x00000000 (0bxxxx,xxxx,xxxx,xxxx,xxx0,0000,0000,0000)

Bit Reset Description

12 0x0

ERR12:

1'b1 -> Force Assertion of Mission Error Reporting for Comparator Error from sys0_0.u_NV_gpcdma.

u_regwrap.clkdis

1'b0 -> Do Nothing

= NOFORCE0

= FORCE1

11 0x0

ERR11:

1'b1 -> Force Assertion of Mission Error Reporting for Register Parity Error from sys0_0.u_NV_gpcdma.

u_safety_plugins.u_err_collator_scrwrap

1'b0 -> Do Nothing

= NOFORCE0

= FORCE1

10 0x0

ERR10:

1'b1 -> Force Assertion of Mission Error Reporting for ECC DED Error from on-chip SRAM/FIFO from sys0_0.

u_NV_gpcdma.u_ramwrap

1'b0 -> Do Nothing

= NOFORCE0

= FORCE1

9 0x0

ERR9:

1'b1 -> Force Assertion of Mission Error Reporting for ECC DED Error from on-chip SRAM/FIFO from sys0_0.

u_NV_gpcdma.u_ramwrap

1'b0 -> Do Nothing

= NOFORCE0

= FORCE1

8 0x0

ERR8:

1'b1 -> Force Assertion of Mission Error Reporting for ECC SEC Error from on-chip SRAM/FIFO from sys0_0.

u_NV_gpcdma.u_ramwrap

1'b0 -> Do Nothing

= NOFORCE0

= FORCE1

0x0

ERR7:

1'b1 -> Force Assertion of Mission Error Reporting for ECC SEC Error from on-chip SRAM/FIFO from sys0_0.

u_NV_gpcdma.u_ramwrap

1'b0 -> Do Nothing

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Bit Reset Description

= NOFORCE0

= FORCE1

6 0x0

ERR6:

1'b1 -> Force Assertion of Mission Error Reporting for Comparator Error from sys0_0.u_NV_gpcdma.

u_ramintf

1'b0 -> Do Nothing

= NOFORCE0

= FORCE1

5 0x0

ERR5:

1'b1 -> Force Assertion of Mission Error Reporting for Comparator Error from sys0_0.u_NV_gpcdma.

u_regwrap.activity

1'b0 -> Do Nothing

= NOFORCE0

= FORCE1

4 0x0

ERR4:

1'b1 -> Force Assertion of Mission Error Reporting for Comparator Error from sys0_0.u_NV_gpcdma.

u_regwrap.intbus

1'b0 -> Do Nothing

= NOFORCE0

= FORCE1

3 0x0

ERR3:

1'b1 -> Force Assertion of Mission Error Reporting for Comparator Error from sys0_0.u_NV_gpcdma.

u_regwrap

1'b0 -> Do Nothing

= NOFORCE0

= FORCE1

2 0x0

ERR2:

1'b1 -> Force Assertion of Mission Error Reporting for Comparator Error from sys0_0.u_NV_gpcdma.u_io_axi

1'b0 -> Do Nothing

= NOFORCE0

= FORCE1

1 0x0

ERR1:

1'b1 -> Force Assertion of Mission Error Reporting for Comparator Error from sys0_0.u_NV_gpcdma.

u_mc_axi

1'b0 -> Do Nothing

= NOFORCE0

= FORCE1

0x0

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Bit Reset Description

ERR0:

1'b1 -> Force Assertion of Mission Error Reporting for Register Parity Error from NV_GPCDMA_err_collator

1'b0 -> Do Nothing

= NOFORCE0

= FORCE1

GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_STATUS_0

Software must write 1 to clear the fields of this register.

Bits in this register continue to be logged independent of the value of MissionError_Enable register, to avoid

silent dropping of errors.

Offset: 0xff38

Read/Write: R/W

Parity Protection: Y

SCR Protection: EC_SCR_0

Reset: 0x00000000 (0bxxxx,xxxx,xxxx,xxxx,xxx0,0000,0000,0000)

Bit Reset Description

12 0x0

ERR12:

1'b1 -> Error_12_pulse[1:0] for Comparator Error from sys0_0.u_NV_gpcdma.u_regwrap.clkdis was equal to

2'b10.

1'b0 -> Error_12_pulse[1:0] for Comparator Error from sys0_0.u_NV_gpcdma.u_regwrap.clkdis was equal to

2'b01.

11 0x0

ERR11:

1'b1 -> Error_11_pulse[1:0] for Register Parity Error from sys0_0.u_NV_gpcdma.u_safety_plugins.

u_err_collator_scrwrap was equal to 2'b10.

1'b0 -> Error_11_pulse[1:0] for Register Parity Error from sys0_0.u_NV_gpcdma.u_safety_plugins.

u_err_collator_scrwrap was equal to 2'b01.

10 0x0

ERR10:

1'b1 -> Error_10_pulse[1:0] for ECC DED Error from on-chip SRAM/FIFO from sys0_0.u_NV_gpcdma.

u_ramwrap was equal to 2'b10.

1'b0 -> Error_10_pulse[1:0] for ECC DED Error from on-chip SRAM/FIFO from sys0_0.u_NV_gpcdma.

u_ramwrap was equal to 2'b01.

9 0x0

ERR9:

1'b1 -> Error_9_pulse[1:0] for ECC DED Error from on-chip SRAM/FIFO from sys0_0.u_NV_gpcdma.

u_ramwrap was equal to 2'b10.

1'b0 -> Error_9_pulse[1:0] for ECC DED Error from on-chip SRAM/FIFO from sys0_0.u_NV_gpcdma.

u_ramwrap was equal to 2'b01.

8 0x0

ERR8:

1'b1 -> Error_8_pulse[1:0] for ECC SEC Error from on-chip SRAM/FIFO from sys0_0.u_NV_gpcdma.

u_ramwrap was equal to 2'b10.

1'b0 -> Error_8_pulse[1:0] for ECC SEC Error from on-chip SRAM/FIFO from sys0_0.u_NV_gpcdma.

u_ramwrap was equal to 2'b01.

0x0

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Bit Reset Description

ERR7:

1'b1 -> Error_7_pulse[1:0] for ECC SEC Error from on-chip SRAM/FIFO from sys0_0.u_NV_gpcdma.

u_ramwrap was equal to 2'b10.

1'b0 -> Error_7_pulse[1:0] for ECC SEC Error from on-chip SRAM/FIFO from sys0_0.u_NV_gpcdma.

u_ramwrap was equal to 2'b01.

6 0x0

ERR6:

1'b1 -> Error_6_pulse[1:0] for Comparator Error from sys0_0.u_NV_gpcdma.u_ramintf was equal to 2'b10.

1'b0 -> Error_6_pulse[1:0] for Comparator Error from sys0_0.u_NV_gpcdma.u_ramintf was equal to 2'b01.

5 0x0

ERR5:

1'b1 -> Error_5_pulse[1:0] for Comparator Error from sys0_0.u_NV_gpcdma.u_regwrap.activity was equal to

2'b10.

1'b0 -> Error_5_pulse[1:0] for Comparator Error from sys0_0.u_NV_gpcdma.u_regwrap.activity was equal to

2'b01.

4 0x0

ERR4:

1'b1 -> Error_4_pulse[1:0] for Comparator Error from sys0_0.u_NV_gpcdma.u_regwrap.intbus was equal to

2'b10.

1'b0 -> Error_4_pulse[1:0] for Comparator Error from sys0_0.u_NV_gpcdma.u_regwrap.intbus was equal to

2'b01.

3 0x0

ERR3:

1'b1 -> Error_3_pulse[1:0] for Comparator Error from sys0_0.u_NV_gpcdma.u_regwrap was equal to 2'b10.

1'b0 -> Error_3_pulse[1:0] for Comparator Error from sys0_0.u_NV_gpcdma.u_regwrap was equal to 2'b01.

2 0x0

ERR2:

1'b1 -> Error_2_pulse[1:0] for Comparator Error from sys0_0.u_NV_gpcdma.u_io_axi was equal to 2'b10.

1'b0 -> Error_2_pulse[1:0] for Comparator Error from sys0_0.u_NV_gpcdma.u_io_axi was equal to 2'b01.

1 0x0

ERR1:

1'b1 -> Error_1_pulse[1:0] for Comparator Error from sys0_0.u_NV_gpcdma.u_mc_axi was equal to 2'b10.

1'b0 -> Error_1_pulse[1:0] for Comparator Error from sys0_0.u_NV_gpcdma.u_mc_axi was equal to 2'b01.

0 0x0

ERR0:

1'b1 -> Error_0_pulse[1:0] for Register Parity Error from NV_GPCDMA_err_collator was equal to 2'b10.

1'b0 -> Error_0_pulse[1:0] for Register Parity Error from NV_GPCDMA_err_collator was equal to 2'b01.

GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_INJECT_0

Offset: 0xff3c

Read/Write: R/W

Parity Protection: N

SCR Protection: EC_SCR_0

Reset: 0x00000000 (0bxxxx,xxxx,xxxx,xxxx,xxx0,0000,0000,0000)

Bit Reset Description

0x0

ERR12:

1'b1 -> Assert the inject_error_12 output for Comparator Error to sys0_0.u_NV_gpcdma.u_regwrap.clkdis to

allow for error injection.

1'b0 -> De-Assert inject_error_12 output.

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Bit Reset Description

= DISABLE0

= ENABLE1

11 0x0

ERR11:

1'b1 -> Assert the inject_error_11 output for Register Parity Error to sys0_0.u_NV_gpcdma.u_safety_plugins.

u_err_collator_scrwrap to allow for error injection.

1'b0 -> De-Assert inject_error_11 output.

= DISABLE0

= ENABLE1

10 0x0

ERR10:

1'b1 -> Assert the inject_error_10 output for ECC DED Error from on-chip SRAM/FIFO to sys0_0.

u_NV_gpcdma.u_ramwrap to allow for error injection.

1'b0 -> De-Assert inject_error_10 output.

= DISABLE0

= ENABLE1

9 0x0

ERR9:

1'b1 -> Assert the inject_error_9 output for ECC DED Error from on-chip SRAM/FIFO to sys0_0.

u_NV_gpcdma.u_ramwrap to allow for error injection.

1'b0 -> De-Assert inject_error_9 output.

= DISABLE0

= ENABLE1

8 0x0

ERR8:

1'b1 -> Assert the inject_error_8 output for ECC SEC Error from on-chip SRAM/FIFO to sys0_0.

u_NV_gpcdma.u_ramwrap to allow for error injection.

1'b0 -> De-Assert inject_error_8 output.

= DISABLE0

= ENABLE1

7 0x0

ERR7:

1'b1 -> Assert the inject_error_7 output for ECC SEC Error from on-chip SRAM/FIFO to sys0_0.

u_NV_gpcdma.u_ramwrap to allow for error injection.

1'b0 -> De-Assert inject_error_7 output.

= DISABLE0

= ENABLE1

6 0x0

ERR6:

1'b1 -> Assert the inject_error_6 output for Comparator Error to sys0_0.u_NV_gpcdma.u_ramintf to allow for

error injection.

1'b0 -> De-Assert inject_error_6 output.

= DISABLE0

= ENABLE1

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Bit Reset Description

5 0x0

ERR5:

1'b1 -> Assert the inject_error_5 output for Comparator Error to sys0_0.u_NV_gpcdma.u_regwrap.activity to

allow for error injection.

1'b0 -> De-Assert inject_error_5 output.

= DISABLE0

= ENABLE1

4 0x0

ERR4:

1'b1 -> Assert the inject_error_4 output for Comparator Error to sys0_0.u_NV_gpcdma.u_regwrap.intbus to

allow for error injection.

1'b0 -> De-Assert inject_error_4 output.

= DISABLE0

= ENABLE1

3 0x0

ERR3:

1'b1 -> Assert the inject_error_3 output for Comparator Error to sys0_0.u_NV_gpcdma.u_regwrap to allow

for error injection.

1'b0 -> De-Assert inject_error_3 output.

= DISABLE0

= ENABLE1

2 0x0

ERR2:

1'b1 -> Assert the inject_error_2 output for Comparator Error to sys0_0.u_NV_gpcdma.u_io_axi to allow for

error injection.

1'b0 -> De-Assert inject_error_2 output.

= DISABLE0

= ENABLE1

1 0x0

ERR1:

1'b1 -> Assert the inject_error_1 output for Comparator Error to sys0_0.u_NV_gpcdma.u_mc_axi to allow for

error injection.

1'b0 -> De-Assert inject_error_1 output.

= DISABLE0

= ENABLE1

0 0x0

ERR0:

1'b1 -> Assert the inject_error_0 output for Register Parity Error to NV_GPCDMA_err_collator to allow for

error injection.

1'b0 -> De-Assert inject_error_0 output.

= DISABLE0

= ENABLE1

GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_ENABLE_0

Offset: 0xff40

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Read/Write: R/W

Parity Protection: Y

SCR Protection: EC_SCR_0

Reset: 0x00001fff (0bxxxx,xxxx,xxxx,xxxx,xxx1,1111,1111,1111)

Bit Reset Description

12 0x1

ERR12:

1'b1 -> Enable Latent Error Reporting for Comparator Error from sys0_0.u_NV_gpcdma.u_regwrap.clkdis

1'b0 -> Disable Latent Error Reporting for Comparator Error from sys0_0.u_NV_gpcdma.u_regwrap.clkdis

= DISABLE0

= ENABLE1

11 0x1

ERR11:

1'b1 -> Enable Latent Error Reporting for Register Parity Error from sys0_0.u_NV_gpcdma.u_safety_plugins.

u_err_collator_scrwrap

1'b0 -> Disable Latent Error Reporting for Register Parity Error from sys0_0.u_NV_gpcdma.u_safety_plugins.

u_err_collator_scrwrap

= DISABLE0

= ENABLE1

10 0x1

ERR10:

1'b1 -> Enable Latent Error Reporting for ECC DED Error from on-chip SRAM/FIFO from sys0_0.

u_NV_gpcdma.u_ramwrap

1'b0 -> Disable Latent Error Reporting for ECC DED Error from on-chip SRAM/FIFO from sys0_0.

u_NV_gpcdma.u_ramwrap

= DISABLE0

= ENABLE1

9 0x1

ERR9:

1'b1 -> Enable Latent Error Reporting for ECC DED Error from on-chip SRAM/FIFO from sys0_0.

u_NV_gpcdma.u_ramwrap

1'b0 -> Disable Latent Error Reporting for ECC DED Error from on-chip SRAM/FIFO from sys0_0.

u_NV_gpcdma.u_ramwrap

= DISABLE0

= ENABLE1

8 0x1

ERR8:

1'b1 -> Enable Latent Error Reporting for ECC SEC Error from on-chip SRAM/FIFO from sys0_0.

u_NV_gpcdma.u_ramwrap

1'b0 -> Disable Latent Error Reporting for ECC SEC Error from on-chip SRAM/FIFO from sys0_0.

u_NV_gpcdma.u_ramwrap

= DISABLE0

= ENABLE1

0x1

ERR7:

1'b1 -> Enable Latent Error Reporting for ECC SEC Error from on-chip SRAM/FIFO from sys0_0.

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Bit Reset Description

u_NV_gpcdma.u_ramwrap

1'b0 -> Disable Latent Error Reporting for ECC SEC Error from on-chip SRAM/FIFO from sys0_0.

u_NV_gpcdma.u_ramwrap

= DISABLE0

= ENABLE1

6 0x1

ERR6:

1'b1 -> Enable Latent Error Reporting for Comparator Error from sys0_0.u_NV_gpcdma.u_ramintf

1'b0 -> Disable Latent Error Reporting for Comparator Error from sys0_0.u_NV_gpcdma.u_ramintf

= DISABLE0

= ENABLE1

5 0x1

ERR5:

1'b1 -> Enable Latent Error Reporting for Comparator Error from sys0_0.u_NV_gpcdma.u_regwrap.activity

1'b0 -> Disable Latent Error Reporting for Comparator Error from sys0_0.u_NV_gpcdma.u_regwrap.activity

= DISABLE0

= ENABLE1

4 0x1

ERR4:

1'b1 -> Enable Latent Error Reporting for Comparator Error from sys0_0.u_NV_gpcdma.u_regwrap.intbus

1'b0 -> Disable Latent Error Reporting for Comparator Error from sys0_0.u_NV_gpcdma.u_regwrap.intbus

= DISABLE0

= ENABLE1

3 0x1

ERR3:

1'b1 -> Enable Latent Error Reporting for Comparator Error from sys0_0.u_NV_gpcdma.u_regwrap

1'b0 -> Disable Latent Error Reporting for Comparator Error from sys0_0.u_NV_gpcdma.u_regwrap

= DISABLE0

= ENABLE1

2 0x1

ERR2:

1'b1 -> Enable Latent Error Reporting for Comparator Error from sys0_0.u_NV_gpcdma.u_io_axi

1'b0 -> Disable Latent Error Reporting for Comparator Error from sys0_0.u_NV_gpcdma.u_io_axi

= DISABLE0

= ENABLE1

1 0x1

ERR1:

1'b1 -> Enable Latent Error Reporting for Comparator Error from sys0_0.u_NV_gpcdma.u_mc_axi

1'b0 -> Disable Latent Error Reporting for Comparator Error from sys0_0.u_NV_gpcdma.u_mc_axi

= DISABLE0

= ENABLE1

0x1

ERR0:

1'b1 -> Enable Latent Error Reporting for Register Parity Error from NV_GPCDMA_err_collator

1'b0 -> Disable Latent Error Reporting for Register Parity Error from NV_GPCDMA_err_collator

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Bit Reset Description

= DISABLE0

= ENABLE1

GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_FORCE_0

Offset: 0xff44

Read/Write: WO

Parity Protection: N

SCR Protection: EC_SCR_0

Reset: 0x00000000 (0bxxxx,xxxx,xxxx,xxxx,xxx0,0000,0000,0000)

Bit Reset Description

12 0x0

ERR12:

1'b1 -> Force Assertion of Latent Error Reporting for Comparator Error from sys0_0.u_NV_gpcdma.

u_regwrap.clkdis

1'b0 -> Do Nothing

= NOFORCE0

= FORCE1

11 0x0

ERR11:

1'b1 -> Force Assertion of Latent Error Reporting for Register Parity Error from sys0_0.u_NV_gpcdma.

u_safety_plugins.u_err_collator_scrwrap

1'b0 -> Do Nothing

= NOFORCE0

= FORCE1

10 0x0

ERR10:

1'b1 -> Force Assertion of Latent Error Reporting for ECC DED Error from on-chip SRAM/FIFO from sys0_0.

u_NV_gpcdma.u_ramwrap

1'b0 -> Do Nothing

= NOFORCE0

= FORCE1

9 0x0

ERR9:

1'b1 -> Force Assertion of Latent Error Reporting for ECC DED Error from on-chip SRAM/FIFO from sys0_0.

u_NV_gpcdma.u_ramwrap

1'b0 -> Do Nothing

= NOFORCE0

= FORCE1

0x0

ERR8:

1'b1 -> Force Assertion of Latent Error Reporting for ECC SEC Error from on-chip SRAM/FIFO from sys0_0.

u_NV_gpcdma.u_ramwrap

1'b0 -> Do Nothing

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Bit Reset Description

= NOFORCE0

= FORCE1

7 0x0

ERR7:

1'b1 -> Force Assertion of Latent Error Reporting for ECC SEC Error from on-chip SRAM/FIFO from sys0_0.

u_NV_gpcdma.u_ramwrap

1'b0 -> Do Nothing

= NOFORCE0

= FORCE1

6 0x0

ERR6:

1'b1 -> Force Assertion of Latent Error Reporting for Comparator Error from sys0_0.u_NV_gpcdma.u_ramintf

1'b0 -> Do Nothing

= NOFORCE0

= FORCE1

5 0x0

ERR5:

1'b1 -> Force Assertion of Latent Error Reporting for Comparator Error from sys0_0.u_NV_gpcdma.

u_regwrap.activity

1'b0 -> Do Nothing

= NOFORCE0

= FORCE1

4 0x0

ERR4:

1'b1 -> Force Assertion of Latent Error Reporting for Comparator Error from sys0_0.u_NV_gpcdma.

u_regwrap.intbus

1'b0 -> Do Nothing

= NOFORCE0

= FORCE1

3 0x0

ERR3:

1'b1 -> Force Assertion of Latent Error Reporting for Comparator Error from sys0_0.u_NV_gpcdma.

u_regwrap

1'b0 -> Do Nothing

= NOFORCE0

= FORCE1

2 0x0

ERR2:

1'b1 -> Force Assertion of Latent Error Reporting for Comparator Error from sys0_0.u_NV_gpcdma.u_io_axi

1'b0 -> Do Nothing

= NOFORCE0

= FORCE1

0x0

ERR1:

1'b1 -> Force Assertion of Latent Error Reporting for Comparator Error from sys0_0.u_NV_gpcdma.u_mc_axi

1'b0 -> Do Nothing

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Bit Reset Description

= NOFORCE0

= FORCE1

0 0x0

ERR0:

1'b1 -> Force Assertion of Latent Error Reporting for Register Parity Error from NV_GPCDMA_err_collator

1'b0 -> Do Nothing

= NOFORCE0

= FORCE1

GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_STATUS_0

Software must write 1 to clear the fields of this register.

Bits in this register continue to be logged independent of the value of LatentError_Enable register, to avoid

silent dropping of errors.

Offset: 0xff48

Read/Write: R/W

Parity Protection: Y

SCR Protection: EC_SCR_0

Reset: 0x00000000 (0bxxxx,xxxx,xxxx,xxxx,xxx0,0000,0000,0000)

Bit Reset Description

12 0x0

ERR12:

1'b1 -> Error_12_pulse[1:0] for Comparator Error from sys0_0.u_NV_gpcdma.u_regwrap.clkdis was equal to

2'b00 or 2'b11.

1'b0 -> Error_12_pulse[1:0] for Comparator Error from sys0_0.u_NV_gpcdma.u_regwrap.clkdis was equal to

2'b01 or 2'b10, but no latent error.

11 0x0

ERR11:

1'b1 -> Error_11_pulse[1:0] for Register Parity Error from sys0_0.u_NV_gpcdma.u_safety_plugins.

u_err_collator_scrwrap was equal to 2'b00 or 2'b11.

1'b0 -> Error_11_pulse[1:0] for Register Parity Error from sys0_0.u_NV_gpcdma.u_safety_plugins.

u_err_collator_scrwrap was equal to 2'b01 or 2'b10, but no latent error.

10 0x0

ERR10:

1'b1 -> Error_10_pulse[1:0] for ECC DED Error from on-chip SRAM/FIFO from sys0_0.u_NV_gpcdma.

u_ramwrap was equal to 2'b00 or 2'b11.

1'b0 -> Error_10_pulse[1:0] for ECC DED Error from on-chip SRAM/FIFO from sys0_0.u_NV_gpcdma.

u_ramwrap was equal to 2'b01 or 2'b10, but no latent error.

9 0x0

ERR9:

1'b1 -> Error_9_pulse[1:0] for ECC DED Error from on-chip SRAM/FIFO from sys0_0.u_NV_gpcdma.

u_ramwrap was equal to 2'b00 or 2'b11.

1'b0 -> Error_9_pulse[1:0] for ECC DED Error from on-chip SRAM/FIFO from sys0_0.u_NV_gpcdma.

u_ramwrap was equal to 2'b01 or 2'b10, but no latent error.

0x0

ERR8:

1'b1 -> Error_8_pulse[1:0] for ECC SEC Error from on-chip SRAM/FIFO from sys0_0.u_NV_gpcdma.

u_ramwrap was equal to 2'b00 or 2'b11.

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Bit Reset Description

1'b0 -> Error_8_pulse[1:0] for ECC SEC Error from on-chip SRAM/FIFO from sys0_0.u_NV_gpcdma.

u_ramwrap was equal to 2'b01 or 2'b10, but no latent error.

7 0x0

ERR7:

1'b1 -> Error_7_pulse[1:0] for ECC SEC Error from on-chip SRAM/FIFO from sys0_0.u_NV_gpcdma.

u_ramwrap was equal to 2'b00 or 2'b11.

1'b0 -> Error_7_pulse[1:0] for ECC SEC Error from on-chip SRAM/FIFO from sys0_0.u_NV_gpcdma.

u_ramwrap was equal to 2'b01 or 2'b10, but no latent error.

6 0x0

ERR6:

1'b1 -> Error_6_pulse[1:0] for Comparator Error from sys0_0.u_NV_gpcdma.u_ramintf was equal to 2'b00 or

2'b11.

1'b0 -> Error_6_pulse[1:0] for Comparator Error from sys0_0.u_NV_gpcdma.u_ramintf was equal to 2'b01 or

2'b10, but no latent error.

5 0x0

ERR5:

1'b1 -> Error_5_pulse[1:0] for Comparator Error from sys0_0.u_NV_gpcdma.u_regwrap.activity was equal to

2'b00 or 2'b11.

1'b0 -> Error_5_pulse[1:0] for Comparator Error from sys0_0.u_NV_gpcdma.u_regwrap.activity was equal to

2'b01 or 2'b10, but no latent error.

4 0x0

ERR4:

1'b1 -> Error_4_pulse[1:0] for Comparator Error from sys0_0.u_NV_gpcdma.u_regwrap.intbus was equal to

2'b00 or 2'b11.

1'b0 -> Error_4_pulse[1:0] for Comparator Error from sys0_0.u_NV_gpcdma.u_regwrap.intbus was equal to

2'b01 or 2'b10, but no latent error.

3 0x0

ERR3:

1'b1 -> Error_3_pulse[1:0] for Comparator Error from sys0_0.u_NV_gpcdma.u_regwrap was equal to 2'b00

or 2'b11.

1'b0 -> Error_3_pulse[1:0] for Comparator Error from sys0_0.u_NV_gpcdma.u_regwrap was equal to 2'b01

or 2'b10, but no latent error.

2 0x0

ERR2:

1'b1 -> Error_2_pulse[1:0] for Comparator Error from sys0_0.u_NV_gpcdma.u_io_axi was equal to 2'b00 or

2'b11.

1'b0 -> Error_2_pulse[1:0] for Comparator Error from sys0_0.u_NV_gpcdma.u_io_axi was equal to 2'b01 or

2'b10, but no latent error.

1 0x0

ERR1:

1'b1 -> Error_1_pulse[1:0] for Comparator Error from sys0_0.u_NV_gpcdma.u_mc_axi was equal to 2'b00 or

2'b11.

1'b0 -> Error_1_pulse[1:0] for Comparator Error from sys0_0.u_NV_gpcdma.u_mc_axi was equal to 2'b01 or

2'b10, but no latent error.

0 0x0

ERR0:

1'b1 -> Error_0_pulse[1:0] for Register Parity Error from NV_GPCDMA_err_collator was equal to 2'b00 or

2'b11.

1'b0 -> Error_0_pulse[1:0] for Register Parity Error from NV_GPCDMA_err_collator was equal to 2'b01 or

2'b10, but no latent error.

GPCDMA_ERRCOLLATOR_ERRSLICE0_COUNTER_RELOAD_0

Offset: 0xff50

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Read/Write: WO

Parity Protection: N

SCR Protection: EC_SCR_0

Reset: 0x00000000 (0bxxxx,xxxx,xxxx,xxxx,xxx0,0000,0000,0000)

Bit Reset Description

12 0x0

ERR12:

1'b1 -> Reload Error Counter for Comparator Error from sys0_0.u_NV_gpcdma.u_regwrap.clkdis

1'b0 -> Do Nothing

= NORELOAD0

= RELOAD1

11 0x0

ERR11:

1'b1 -> Reload Error Counter for Register Parity Error from sys0_0.u_NV_gpcdma.u_safety_plugins.

u_err_collator_scrwrap

1'b0 -> Do Nothing

= NORELOAD0

= RELOAD1

10 0x0

ERR10:

1'b1 -> Reload Error Counter for ECC DED Error from on-chip SRAM/FIFO from sys0_0.u_NV_gpcdma.

u_ramwrap

1'b0 -> Do Nothing

= NORELOAD0

= RELOAD1

9 0x0

ERR9:

1'b1 -> Reload Error Counter for ECC DED Error from on-chip SRAM/FIFO from sys0_0.u_NV_gpcdma.

u_ramwrap

1'b0 -> Do Nothing

= NORELOAD0

= RELOAD1

8 0x0

ERR8:

1'b1 -> Reload Error Counter for ECC SEC Error from on-chip SRAM/FIFO from sys0_0.u_NV_gpcdma.

u_ramwrap

1'b0 -> Do Nothing

= NORELOAD0

= RELOAD1

0x0

ERR7:

1'b1 -> Reload Error Counter for ECC SEC Error from on-chip SRAM/FIFO from sys0_0.u_NV_gpcdma.

u_ramwrap

1'b0 -> Do Nothing

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Bit Reset Description

= NORELOAD0

= RELOAD1

6 0x0

ERR6:

1'b1 -> Reload Error Counter for Comparator Error from sys0_0.u_NV_gpcdma.u_ramintf

1'b0 -> Do Nothing

= NORELOAD0

= RELOAD1

5 0x0

ERR5:

1'b1 -> Reload Error Counter for Comparator Error from sys0_0.u_NV_gpcdma.u_regwrap.activity

1'b0 -> Do Nothing

= NORELOAD0

= RELOAD1

4 0x0

ERR4:

1'b1 -> Reload Error Counter for Comparator Error from sys0_0.u_NV_gpcdma.u_regwrap.intbus

1'b0 -> Do Nothing

= NORELOAD0

= RELOAD1

3 0x0

ERR3:

1'b1 -> Reload Error Counter for Comparator Error from sys0_0.u_NV_gpcdma.u_regwrap

1'b0 -> Do Nothing

= NORELOAD0

= RELOAD1

2 0x0

ERR2:

1'b1 -> Reload Error Counter for Comparator Error from sys0_0.u_NV_gpcdma.u_io_axi

1'b0 -> Do Nothing

= NORELOAD0

= RELOAD1

1 0x0

ERR1:

1'b1 -> Reload Error Counter for Comparator Error from sys0_0.u_NV_gpcdma.u_mc_axi

1'b0 -> Do Nothing

= NORELOAD0

= RELOAD1

0 0x0

ERR0:

1'b1 -> Reload Error Counter for Register Parity Error from NV_GPCDMA_err_collator

1'b0 -> Do Nothing

= NORELOAD0

= RELOAD1

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CHANNEL

GPCDMA_CHANNEL_CH0_CSR_0

Offset: 0x10000

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH0_0

Reset: 0x08008400 (0b00xx,1x00,0000,0000,1x00,01xx,xxxx,xxxx)

Bit Reset Description

31 0x0

ENB:

= DISABLE0

= ENABLE1

30 0x0

IE_EOC:

= DISABLE0

= ENABLE1

27 0x1

ONCE:

= CYCLIC_MODE0

= SINGLE_BLOCK1

25:24 0x0

FC_MODE:

= NO_MMIO0

= ONE_MMIO1

= TWO_MMIO2

= FOUR_MMIO3

23:21 0x0

DMA_MODE:

= IO2MEM_NO_FC0

= IO2MEM_FC1

= MEM2IO_NO_FC2

= MEM2IO_FC3

= MEM2MEM4

= RSVD5

= FIXED_PAT6

20:16

0x0

REQ_SEL:

= I2C80

= I2C101

= UARTG2

= UARTC3

= QSPI05

= QSPI16

= UARTA8

= UARTB9

= UARTF12

= UARTH13

= SPI115

= SPI216

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Bit Reset Description

= SPI317

= UARTD19

= UARTE20

= I2C21

= I2C222

= I2C323

= I2C524

= I2C426

= I2C727

= I2C630

= I2C931

= RSVD29

15 0x1

IRQ_MASK:

= DISABLE0

= ENABLE1

13:10 0x1

WEIGHT

GPCDMA_CHANNEL_CH0_STA_0

Offset: 0x10004

Read/Write: See table below

Parity Protection: N

SCR Protection: SCR_CH0_0

Reset: 0x00000000 (0b00x0,0000,0x00,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit R/W Reset Description

31 RO 0x0

BSY:

= WAIT0

= ACTIVE1

30 RW 0x0

ISE_EOC:

= NO_INTR0

= INTR1

28 RO 0x0

PING_PONG_STA:

= PING_INTR_STA0

= PONG_INTR_STA1

27 RO 0x0

DMA_ACTIVITY:

= IDLE0

= BUSY1

26 RO 0x0

CHANNEL_PAUSE:

= RESUME0

= PAUSE1

25 RO 0x0

CHANNEL_RX:

= NOT_ACTIVE0

= ACTIVE1

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Bit R/W Reset Description

24 RO 0x0

CHANNEL_TX:

= NOT_ACTIVE0

= ACTIVE1

23 RO 0x0

IRQ_INTR_STA:

= DISABLE0

= ENABLE1

21 RO 0x0

TRIG_STA:

= NOT_ACTIVE0

= ACTIVE1

20 RO 0x0

INTR_STA:

= NOT_ACTIVE0

= ACTIVE1

GPCDMA_CHANNEL_CH0_CSRE_0

Offset: 0x10008

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH0_0

Reset: 0x00000000 (0b0xxx,xxxx,xxxx,0000,00xx,xxxx,xxxx,xxxx)

Bit Reset Description

31 0x0

DMA_ACTIVITY:

= RESUME0

= PAUSE1

19:14

0x0

TRIG_SEL:

= SMP_241

= SMP_252

= SMP_263

= SMP_274

= XRQ_A5

= XRQ_B6

= TMR17

= TMR28

= CH09

= CH110

= CH211

= CH312

= CH413

= CH514

= CH615

= CH716

= CH817

= CH918

= CH1019

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Bit Reset Description

= CH1120

= CH1221

= CH1322

= CH1423

= CH1524

= CH1625

= CH1726

= CH1827

= CH1928

= CH2029

= CH2130

= CH2231

= CH2332

= CH2433

= CH2534

= CH2635

= CH2736

= CH2837

= CH2938

= CH3039

= CH3140

= RSVD0

GPCDMA_CHANNEL_CH0_SRC_PTR_0

Offset: 0x1000c

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH0_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

SRC_PTR

GPCDMA_CHANNEL_CH0_DST_PTR_0

Offset: 0x10010

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH0_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

DST_PTR

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GPCDMA_CHANNEL_CH0_HI_ADR_PTR_0

Offset: 0x10014

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH0_0

Reset: 0x00000000 (0bxxxx,xxxx,0000,0000,xxxx,xxxx,0000,0000)

Bit Reset Description

23:16 0x0

HI_DST_PTR

7:0 0x0

HI_SRC_PTR

GPCDMA_CHANNEL_CH0_MC_SEQ_0

Offset: 0x10018

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH0_0

Reset: 0x03800000 (0b0000,0011,1000,0000,0000,0000,0000,0000)

Bit Reset Description

31 0x0

MC_DATA_SWAP:

= DISABLE0

= ENABLE1

30:25 0x1

MC_REQ_CNT

24:23 0x3

MC_BURST:

= DMA_BURST_2WORDS0

= DMA_BURST_16WORDS3

22:20 0x0

MC_ADDR_WRAP1:

= NO_WRAP0

= WRAP_0N_32WORDS1

= WRAP_ON_64WORDS2

= WRAP_ON_128WORDS3

= WRAP_ON_256WORDS4

= WRAP_ON_512WORDS5

= WRAP_ON_1024WORDS6

= WRAP_ON_2048WORDS7

19:17 0x0

MC_ADDR_WRAP0:

= NO_WRAP0

= WRAP_0N_32WORDS1

= WRAP_ON_64WORDS2

= WRAP_ON_128WORDS3

= WRAP_ON_256WORDS4

= WRAP_ON_512WORDS5

= WRAP_ON_1024WORDS6

= WRAP_ON_2048WORDS7

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Bit Reset Description

16 0x0

MC_AXIID

15:14 0x0

MC_PROT

13:7 0x0

STREAMID1

6:0 0x0

STREAMID0

GPCDMA_CHANNEL_CH0_MMIO_SEQ_0

Offset: 0x1001c

Read/Write: See table below

Parity Protection: N

SCR Protection: SCR_CH0_0

Reset: 0x2381007f (0b0010,0011,1000,0001,xxxx,xxx0,0111,1111)

Bit R/W Reset Description

31 RW 0x0

DBL_BUF:

= DISABLE0

= ENABLE1

30:28 RW 0x2

MMIO_BUS_WIDTH:

= BUS_WIDTH_80

= BUS_WIDTH_161

= BUS_WIDTH_322

27 RW 0x0

MMIO_DATA_SWAP:

= DISABLE0

= ENABLE1

26:23 RW 0x7

MMIO_BURST:

= DMA_BURST_1WORDS0

= DMA_BURST_2WORDS1

= DMA_BURST_4WORDS3

= DMA_BURST_8WORDS7

= DMA_BURST_16WORDS15

22:19 RO 0x0

MMIO_MASTER_ID:

= RSVD0

= CCPLEX1

= CCPLEX_DPMU2

= BPMP3

= SPE4

= SCE5

= DMA_PER6

= TSECA7

= TSECB8

= JTAGM9

= CSITE10

= APE11

18:16

0x1

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Bit R/W Reset Description

MMIO_ADDR_WRAP:

= NO_WRAP0

= WRAP_0N_1WORDS1

= WRAP_ON_2WORDS2

= WRAP_ON_4WORDS3

= WRAP_ON_8WORDS4

= WRAP_ON_16WORDS5

= WRAP_ON_32WORDS6

= WRAP_ON_64WORDS7

8:7 RW 0x0

MMIO_PROT

6:0 RO 0x7f

MMIO_CHANNEL_SECURITY

GPCDMA_CHANNEL_CH0_BCOUNT_0

Offset: 0x10020

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH0_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

BCOUNT

GPCDMA_CHANNEL_CH0_DMA_BYTE_TRA_0

Offset: 0x10024

Read/Write: RO

Parity Protection: N

SCR Protection: SCR_CH0_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

TRANSFER_COUNT

GPCDMA_CHANNEL_CH0_DMA_BYTE_STA_0

Offset: 0x10028

Read/Write: RO

Parity Protection: N

SCR Protection: SCR_CH0_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

DMA_COUNT

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GPCDMA_CHANNEL_CH0_ERR_STA_0

Offset: 0x10030

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH0_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

ERROR_STATUS

GPCDMA_CHANNEL_CH0_FIXED_PAT_0

Offset: 0x10034

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH0_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

FIXED_PATTERN

GPCDMA_CHANNEL_CH0_TZ_0

Offset: 0x10038

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_TZ_0

Reset: 0x00000003 (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xx11)

Bit Reset Description

1 0x1

MC_PROT_1

0 0x1

MMIO_PROT_1

GPCDMA_CHANNEL_CH1_CSR_0

Offset: 0x20000

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH1_0

Reset: 0x08008400 (0b00xx,1x00,0000,0000,1x00,01xx,xxxx,xxxx)

Bit Reset Description

31 0x0

ENB:

= DISABLE0

= ENABLE1

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Bit Reset Description

30 0x0

IE_EOC:

= DISABLE0

= ENABLE1

27 0x1

ONCE:

= CYCLIC_MODE0

= SINGLE_BLOCK1

25:24 0x0

FC_MODE:

= NO_MMIO0

= ONE_MMIO1

= TWO_MMIO2

= FOUR_MMIO3

23:21 0x0

DMA_MODE:

= IO2MEM_NO_FC0

= IO2MEM_FC1

= MEM2IO_NO_FC2

= MEM2IO_FC3

= MEM2MEM4

= RSVD5

= FIXED_PAT6

20:16 0x0

REQ_SEL:

= I2C80

= I2C101

= UARTG2

= UARTC3

= QSPI05

= QSPI16

= UARTA8

= UARTB9

= UARTF12

= UARTH13

= SPI115

= SPI216

= SPI317

= UARTD19

= UARTE20

= I2C21

= I2C222

= I2C323

= I2C524

= I2C426

= I2C727

= I2C630

= I2C931

= RSVD29

0x1

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Bit Reset Description

IRQ_MASK:

= DISABLE0

= ENABLE1

13:10 0x1

WEIGHT

GPCDMA_CHANNEL_CH1_STA_0

Offset: 0x20004

Read/Write: See table below

Parity Protection: N

SCR Protection: SCR_CH1_0

Reset: 0x00000000 (0b00x0,0000,0x00,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit R/W Reset Description

31 RO 0x0

BSY:

= WAIT0

= ACTIVE1

30 RW 0x0

ISE_EOC:

= NO_INTR0

= INTR1

28 RO 0x0

PING_PONG_STA:

= PING_INTR_STA0

= PONG_INTR_STA1

27 RO 0x0

DMA_ACTIVITY:

= IDLE0

= BUSY1

26 RO 0x0

CHANNEL_PAUSE:

= RESUME0

= PAUSE1

25 RO 0x0

CHANNEL_RX:

= NOT_ACTIVE0

= ACTIVE1

24 RO 0x0

CHANNEL_TX:

= NOT_ACTIVE0

= ACTIVE1

23 RO 0x0

IRQ_INTR_STA:

= DISABLE0

= ENABLE1

21 RO 0x0

TRIG_STA:

= NOT_ACTIVE0

= ACTIVE1

0x0

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Bit R/W Reset Description

INTR_STA:

= NOT_ACTIVE0

= ACTIVE1

GPCDMA_CHANNEL_CH1_CSRE_0

Offset: 0x20008

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH1_0

Reset: 0x00000000 (0b0xxx,xxxx,xxxx,0000,00xx,xxxx,xxxx,xxxx)

Bit Reset Description

31 0x0

DMA_ACTIVITY:

= RESUME0

= PAUSE1

19:14

0x0

TRIG_SEL:

= SMP_241

= SMP_252

= SMP_263

= SMP_274

= XRQ_A5

= XRQ_B6

= TMR17

= TMR28

= CH09

= CH110

= CH211

= CH312

= CH413

= CH514

= CH615

= CH716

= CH817

= CH918

= CH1019

= CH1120

= CH1221

= CH1322

= CH1423

= CH1524

= CH1625

= CH1726

= CH1827

= CH1928

= CH2029

= CH2130

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Bit Reset Description

= CH2231

= CH2332

= CH2433

= CH2534

= CH2635

= CH2736

= CH2837

= CH2938

= CH3039

= CH3140

= RSVD0

GPCDMA_CHANNEL_CH1_SRC_PTR_0

Offset: 0x2000c

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH1_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

SRC_PTR

GPCDMA_CHANNEL_CH1_DST_PTR_0

Offset: 0x20010

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH1_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

DST_PTR

GPCDMA_CHANNEL_CH1_HI_ADR_PTR_0

Offset: 0x20014

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH1_0

Reset: 0x00000000 (0bxxxx,xxxx,0000,0000,xxxx,xxxx,0000,0000)

Bit Reset Description

23:16 0x0

HI_DST_PTR

7:0 0x0

HI_SRC_PTR

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GPCDMA_CHANNEL_CH1_MC_SEQ_0

Offset: 0x20018

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH1_0

Reset: 0x03800000 (0b0000,0011,1000,0000,0000,0000,0000,0000)

Bit Reset Description

31 0x0

MC_DATA_SWAP:

= DISABLE0

= ENABLE1

30:25 0x1

MC_REQ_CNT

24:23 0x3

MC_BURST:

= DMA_BURST_2WORDS0

= DMA_BURST_16WORDS3

22:20 0x0

MC_ADDR_WRAP1:

= NO_WRAP0

= WRAP_0N_32WORDS1

= WRAP_ON_64WORDS2

= WRAP_ON_128WORDS3

= WRAP_ON_256WORDS4

= WRAP_ON_512WORDS5

= WRAP_ON_1024WORDS6

= WRAP_ON_2048WORDS7

19:17 0x0

MC_ADDR_WRAP0:

= NO_WRAP0

= WRAP_0N_32WORDS1

= WRAP_ON_64WORDS2

= WRAP_ON_128WORDS3

= WRAP_ON_256WORDS4

= WRAP_ON_512WORDS5

= WRAP_ON_1024WORDS6

= WRAP_ON_2048WORDS7

16 0x0

MC_AXIID

15:14 0x0

MC_PROT

13:7 0x0

STREAMID1

6:0 0x0

STREAMID0

GPCDMA_CHANNEL_CH1_MMIO_SEQ_0

Offset: 0x2001c

Read/Write: See table below

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Parity Protection: N

SCR Protection: SCR_CH1_0

Reset: 0x2381007f (0b0010,0011,1000,0001,xxxx,xxx0,0111,1111)

Bit R/W Reset Description

31 RW 0x0

DBL_BUF:

= DISABLE0

= ENABLE1

30:28 RW 0x2

MMIO_BUS_WIDTH:

= BUS_WIDTH_80

= BUS_WIDTH_161

= BUS_WIDTH_322

27 RW 0x0

MMIO_DATA_SWAP:

= DISABLE0

= ENABLE1

26:23 RW 0x7

MMIO_BURST:

= DMA_BURST_1WORDS0

= DMA_BURST_2WORDS1

= DMA_BURST_4WORDS3

= DMA_BURST_8WORDS7

= DMA_BURST_16WORDS15

22:19 RO 0x0

MMIO_MASTER_ID:

= RSVD0

= CCPLEX1

= CCPLEX_DPMU2

= BPMP3

= SPE4

= SCE5

= DMA_PER6

= TSECA7

= TSECB8

= JTAGM9

= CSITE10

= APE11

18:16 RW 0x1

MMIO_ADDR_WRAP:

= NO_WRAP0

= WRAP_0N_1WORDS1

= WRAP_ON_2WORDS2

= WRAP_ON_4WORDS3

= WRAP_ON_8WORDS4

= WRAP_ON_16WORDS5

= WRAP_ON_32WORDS6

= WRAP_ON_64WORDS7

8:7 RW 0x0

MMIO_PROT

6:0 RO 0x7f

MMIO_CHANNEL_SECURITY

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GPCDMA_CHANNEL_CH1_BCOUNT_0

Offset: 0x20020

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH1_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

BCOUNT

GPCDMA_CHANNEL_CH1_DMA_BYTE_TRA_0

Offset: 0x20024

Read/Write: RO

Parity Protection: N

SCR Protection: SCR_CH1_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

TRANSFER_COUNT

GPCDMA_CHANNEL_CH1_DMA_BYTE_STA_0

Offset: 0x20028

Read/Write: RO

Parity Protection: N

SCR Protection: SCR_CH1_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

DMA_COUNT

GPCDMA_CHANNEL_CH1_ERR_STA_0

Offset: 0x20030

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH1_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

ERROR_STATUS

GPCDMA_CHANNEL_CH1_FIXED_PAT_0

Offset: 0x20034

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Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH1_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

FIXED_PATTERN

GPCDMA_CHANNEL_CH1_TZ_0

Offset: 0x20038

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_TZ_0

Reset: 0x00000003 (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xx11)

Bit Reset Description

1 0x1

MC_PROT_1

0 0x1

MMIO_PROT_1

GPCDMA_CHANNEL_CH2_CSR_0

Offset: 0x30000

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH2_0

Reset: 0x08008400 (0b00xx,1x00,0000,0000,1x00,01xx,xxxx,xxxx)

Bit Reset Description

31 0x0

ENB:

= DISABLE0

= ENABLE1

30 0x0

IE_EOC:

= DISABLE0

= ENABLE1

27 0x1

ONCE:

= CYCLIC_MODE0

= SINGLE_BLOCK1

25:24 0x0

FC_MODE:

= NO_MMIO0

= ONE_MMIO1

= TWO_MMIO2

= FOUR_MMIO3

23:21

0x0

DMA_MODE:

= IO2MEM_NO_FC0

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Bit Reset Description

= IO2MEM_FC1

= MEM2IO_NO_FC2

= MEM2IO_FC3

= MEM2MEM4

= RSVD5

= FIXED_PAT6

20:16 0x0

REQ_SEL:

= I2C80

= I2C101

= UARTG2

= UARTC3

= QSPI05

= QSPI16

= UARTA8

= UARTB9

= UARTF12

= UARTH13

= SPI115

= SPI216

= SPI317

= UARTD19

= UARTE20

= I2C21

= I2C222

= I2C323

= I2C524

= I2C426

= I2C727

= I2C630

= I2C931

= RSVD29

15 0x1

IRQ_MASK:

= DISABLE0

= ENABLE1

13:10 0x1

WEIGHT

GPCDMA_CHANNEL_CH2_STA_0

Offset: 0x30004

Read/Write: See table below

Parity Protection: N

SCR Protection: SCR_CH2_0

Reset: 0x00000000 (0b00x0,0000,0x00,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit R/W Reset Description

0x0

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Bit R/W Reset Description

BSY:

= WAIT0

= ACTIVE1

30 RW 0x0

ISE_EOC:

= NO_INTR0

= INTR1

28 RO 0x0

PING_PONG_STA:

= PING_INTR_STA0

= PONG_INTR_STA1

27 RO 0x0

DMA_ACTIVITY:

= IDLE0

= BUSY1

26 RO 0x0

CHANNEL_PAUSE:

= RESUME0

= PAUSE1

25 RO 0x0

CHANNEL_RX:

= NOT_ACTIVE0

= ACTIVE1

24 RO 0x0

CHANNEL_TX:

= NOT_ACTIVE0

= ACTIVE1

23 RO 0x0

IRQ_INTR_STA:

= DISABLE0

= ENABLE1

21 RO 0x0

TRIG_STA:

= NOT_ACTIVE0

= ACTIVE1

20 RO 0x0

INTR_STA:

= NOT_ACTIVE0

= ACTIVE1

GPCDMA_CHANNEL_CH2_CSRE_0

Offset: 0x30008

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH2_0

Reset: 0x00000000 (0b0xxx,xxxx,xxxx,0000,00xx,xxxx,xxxx,xxxx)

Bit Reset Description

31 0x0

DMA_ACTIVITY:

= RESUME0

= PAUSE1

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Bit Reset Description

19:14 0x0

TRIG_SEL:

= SMP_241

= SMP_252

= SMP_263

= SMP_274

= XRQ_A5

= XRQ_B6

= TMR17

= TMR28

= CH09

= CH110

= CH211

= CH312

= CH413

= CH514

= CH615

= CH716

= CH817

= CH918

= CH1019

= CH1120

= CH1221

= CH1322

= CH1423

= CH1524

= CH1625

= CH1726

= CH1827

= CH1928

= CH2029

= CH2130

= CH2231

= CH2332

= CH2433

= CH2534

= CH2635

= CH2736

= CH2837

= CH2938

= CH3039

= CH3140

= RSVD0

GPCDMA_CHANNEL_CH2_SRC_PTR_0

Offset: 0x3000c

Read/Write: R/W

Parity Protection: N

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SCR Protection: SCR_CH2_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

SRC_PTR

GPCDMA_CHANNEL_CH2_DST_PTR_0

Offset: 0x30010

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH2_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

DST_PTR

GPCDMA_CHANNEL_CH2_HI_ADR_PTR_0

Offset: 0x30014

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH2_0

Reset: 0x00000000 (0bxxxx,xxxx,0000,0000,xxxx,xxxx,0000,0000)

Bit Reset Description

23:16 0x0

HI_DST_PTR

7:0 0x0

HI_SRC_PTR

GPCDMA_CHANNEL_CH2_MC_SEQ_0

Offset: 0x30018

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH2_0

Reset: 0x03800000 (0b0000,0011,1000,0000,0000,0000,0000,0000)

Bit Reset Description

31 0x0

MC_DATA_SWAP:

= DISABLE0

= ENABLE1

30:25 0x1

MC_REQ_CNT

24:23 0x3

MC_BURST:

= DMA_BURST_2WORDS0

= DMA_BURST_16WORDS3

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Bit Reset Description

22:20 0x0

MC_ADDR_WRAP1:

= NO_WRAP0

= WRAP_0N_32WORDS1

= WRAP_ON_64WORDS2

= WRAP_ON_128WORDS3

= WRAP_ON_256WORDS4

= WRAP_ON_512WORDS5

= WRAP_ON_1024WORDS6

= WRAP_ON_2048WORDS7

19:17 0x0

MC_ADDR_WRAP0:

= NO_WRAP0

= WRAP_0N_32WORDS1

= WRAP_ON_64WORDS2

= WRAP_ON_128WORDS3

= WRAP_ON_256WORDS4

= WRAP_ON_512WORDS5

= WRAP_ON_1024WORDS6

= WRAP_ON_2048WORDS7

16 0x0

MC_AXIID

15:14 0x0

MC_PROT

13:7 0x0

STREAMID1

6:0 0x0

STREAMID0

GPCDMA_CHANNEL_CH2_MMIO_SEQ_0

Offset: 0x3001c

Read/Write: See table below

Parity Protection: N

SCR Protection: SCR_CH2_0

Reset: 0x2381007f (0b0010,0011,1000,0001,xxxx,xxx0,0111,1111)

Bit R/W Reset Description

31 RW 0x0

DBL_BUF:

= DISABLE0

= ENABLE1

30:28 RW 0x2

MMIO_BUS_WIDTH:

= BUS_WIDTH_80

= BUS_WIDTH_161

= BUS_WIDTH_322

27 RW 0x0

MMIO_DATA_SWAP:

= DISABLE0

= ENABLE1

26:23

0x7

MMIO_BURST:

= DMA_BURST_1WORDS0

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Bit R/W Reset Description

= DMA_BURST_2WORDS1

= DMA_BURST_4WORDS3

= DMA_BURST_8WORDS7

= DMA_BURST_16WORDS15

22:19 RO 0x0

MMIO_MASTER_ID:

= RSVD0

= CCPLEX1

= CCPLEX_DPMU2

= BPMP3

= SPE4

= SCE5

= DMA_PER6

= TSECA7

= TSECB8

= JTAGM9

= CSITE10

= APE11

18:16 RW 0x1

MMIO_ADDR_WRAP:

= NO_WRAP0

= WRAP_0N_1WORDS1

= WRAP_ON_2WORDS2

= WRAP_ON_4WORDS3

= WRAP_ON_8WORDS4

= WRAP_ON_16WORDS5

= WRAP_ON_32WORDS6

= WRAP_ON_64WORDS7

8:7 RW 0x0

MMIO_PROT

6:0 RO 0x7f

MMIO_CHANNEL_SECURITY

GPCDMA_CHANNEL_CH2_BCOUNT_0

Offset: 0x30020

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH2_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

BCOUNT

GPCDMA_CHANNEL_CH2_DMA_BYTE_TRA_0

Offset: 0x30024

Read/Write: RO

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Parity Protection: N

SCR Protection: SCR_CH2_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

TRANSFER_COUNT

GPCDMA_CHANNEL_CH2_DMA_BYTE_STA_0

Offset: 0x30028

Read/Write: RO

Parity Protection: N

SCR Protection: SCR_CH2_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

DMA_COUNT

GPCDMA_CHANNEL_CH2_ERR_STA_0

Offset: 0x30030

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH2_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

ERROR_STATUS

GPCDMA_CHANNEL_CH2_FIXED_PAT_0

Offset: 0x30034

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH2_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

FIXED_PATTERN

GPCDMA_CHANNEL_CH2_TZ_0

Offset: 0x30038

Read/Write: R/W

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Parity Protection: N

SCR Protection: SCR_TZ_0

Reset: 0x00000003 (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xx11)

Bit Reset Description

1 0x1

MC_PROT_1

0 0x1

MMIO_PROT_1

GPCDMA_CHANNEL_CH3_CSR_0

Offset: 0x40000

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH3_0

Reset: 0x08008400 (0b00xx,1x00,0000,0000,1x00,01xx,xxxx,xxxx)

Bit Reset Description

31 0x0

ENB:

= DISABLE0

= ENABLE1

30 0x0

IE_EOC:

= DISABLE0

= ENABLE1

27 0x1

ONCE:

= CYCLIC_MODE0

= SINGLE_BLOCK1

25:24 0x0

FC_MODE:

= NO_MMIO0

= ONE_MMIO1

= TWO_MMIO2

= FOUR_MMIO3

23:21 0x0

DMA_MODE:

= IO2MEM_NO_FC0

= IO2MEM_FC1

= MEM2IO_NO_FC2

= MEM2IO_FC3

= MEM2MEM4

= RSVD5

= FIXED_PAT6

20:16

0x0

REQ_SEL:

= I2C80

= I2C101

= UARTG2

= UARTC3

= QSPI05

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Bit Reset Description

= QSPI16

= UARTA8

= UARTB9

= UARTF12

= UARTH13

= SPI115

= SPI216

= SPI317

= UARTD19

= UARTE20

= I2C21

= I2C222

= I2C323

= I2C524

= I2C426

= I2C727

= I2C630

= I2C931

= RSVD29

15 0x1

IRQ_MASK:

= DISABLE0

= ENABLE1

13:10 0x1

WEIGHT

GPCDMA_CHANNEL_CH3_STA_0

Offset: 0x40004

Read/Write: See table below

Parity Protection: N

SCR Protection: SCR_CH3_0

Reset: 0x00000000 (0b00x0,0000,0x00,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit R/W Reset Description

31 RO 0x0

BSY:

= WAIT0

= ACTIVE1

30 RW 0x0

ISE_EOC:

= NO_INTR0

= INTR1

28 RO 0x0

PING_PONG_STA:

= PING_INTR_STA0

= PONG_INTR_STA1

27 RO 0x0

DMA_ACTIVITY:

= IDLE0

= BUSY1

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Bit R/W Reset Description

26 RO 0x0

CHANNEL_PAUSE:

= RESUME0

= PAUSE1

25 RO 0x0

CHANNEL_RX:

= NOT_ACTIVE0

= ACTIVE1

24 RO 0x0

CHANNEL_TX:

= NOT_ACTIVE0

= ACTIVE1

23 RO 0x0

IRQ_INTR_STA:

= DISABLE0

= ENABLE1

21 RO 0x0

TRIG_STA:

= NOT_ACTIVE0

= ACTIVE1

20 RO 0x0

INTR_STA:

= NOT_ACTIVE0

= ACTIVE1

GPCDMA_CHANNEL_CH3_CSRE_0

Offset: 0x40008

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH3_0

Reset: 0x00000000 (0b0xxx,xxxx,xxxx,0000,00xx,xxxx,xxxx,xxxx)

Bit Reset Description

31 0x0

DMA_ACTIVITY:

= RESUME0

= PAUSE1

19:14

0x0

TRIG_SEL:

= SMP_241

= SMP_252

= SMP_263

= SMP_274

= XRQ_A5

= XRQ_B6

= TMR17

= TMR28

= CH09

= CH110

= CH211

= CH312

= CH413

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Bit Reset Description

= CH514

= CH615

= CH716

= CH817

= CH918

= CH1019

= CH1120

= CH1221

= CH1322

= CH1423

= CH1524

= CH1625

= CH1726

= CH1827

= CH1928

= CH2029

= CH2130

= CH2231

= CH2332

= CH2433

= CH2534

= CH2635

= CH2736

= CH2837

= CH2938

= CH3039

= CH3140

= RSVD0

GPCDMA_CHANNEL_CH3_SRC_PTR_0

Offset: 0x4000c

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH3_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

SRC_PTR

GPCDMA_CHANNEL_CH3_DST_PTR_0

Offset: 0x40010

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH3_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

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Bit Reset Description

31:0 0x0

DST_PTR

GPCDMA_CHANNEL_CH3_HI_ADR_PTR_0

Offset: 0x40014

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH3_0

Reset: 0x00000000 (0bxxxx,xxxx,0000,0000,xxxx,xxxx,0000,0000)

Bit Reset Description

23:16 0x0

HI_DST_PTR

7:0 0x0

HI_SRC_PTR

GPCDMA_CHANNEL_CH3_MC_SEQ_0

Offset: 0x40018

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH3_0

Reset: 0x03800000 (0b0000,0011,1000,0000,0000,0000,0000,0000)

Bit Reset Description

31 0x0

MC_DATA_SWAP:

= DISABLE0

= ENABLE1

30:25 0x1

MC_REQ_CNT

24:23 0x3

MC_BURST:

= DMA_BURST_2WORDS0

= DMA_BURST_16WORDS3

22:20 0x0

MC_ADDR_WRAP1:

= NO_WRAP0

= WRAP_0N_32WORDS1

= WRAP_ON_64WORDS2

= WRAP_ON_128WORDS3

= WRAP_ON_256WORDS4

= WRAP_ON_512WORDS5

= WRAP_ON_1024WORDS6

= WRAP_ON_2048WORDS7

19:17

0x0

MC_ADDR_WRAP0:

= NO_WRAP0

= WRAP_0N_32WORDS1

= WRAP_ON_64WORDS2

= WRAP_ON_128WORDS3

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Bit Reset Description

= WRAP_ON_256WORDS4

= WRAP_ON_512WORDS5

= WRAP_ON_1024WORDS6

= WRAP_ON_2048WORDS7

16 0x0

MC_AXIID

15:14 0x0

MC_PROT

13:7 0x0

STREAMID1

6:0 0x0

STREAMID0

GPCDMA_CHANNEL_CH3_MMIO_SEQ_0

Offset: 0x4001c

Read/Write: See table below

Parity Protection: N

SCR Protection: SCR_CH3_0

Reset: 0x2381007f (0b0010,0011,1000,0001,xxxx,xxx0,0111,1111)

Bit R/W Reset Description

31 RW 0x0

DBL_BUF:

= DISABLE0

= ENABLE1

30:28 RW 0x2

MMIO_BUS_WIDTH:

= BUS_WIDTH_80

= BUS_WIDTH_161

= BUS_WIDTH_322

27 RW 0x0

MMIO_DATA_SWAP:

= DISABLE0

= ENABLE1

26:23 RW 0x7

MMIO_BURST:

= DMA_BURST_1WORDS0

= DMA_BURST_2WORDS1

= DMA_BURST_4WORDS3

= DMA_BURST_8WORDS7

= DMA_BURST_16WORDS15

22:19

0x0

MMIO_MASTER_ID:

= RSVD0

= CCPLEX1

= CCPLEX_DPMU2

= BPMP3

= SPE4

= SCE5

= DMA_PER6

= TSECA7

= TSECB8

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Bit R/W Reset Description

= JTAGM9

= CSITE10

= APE11

18:16 RW 0x1

MMIO_ADDR_WRAP:

= NO_WRAP0

= WRAP_0N_1WORDS1

= WRAP_ON_2WORDS2

= WRAP_ON_4WORDS3

= WRAP_ON_8WORDS4

= WRAP_ON_16WORDS5

= WRAP_ON_32WORDS6

= WRAP_ON_64WORDS7

8:7 RW 0x0

MMIO_PROT

6:0 RO 0x7f

MMIO_CHANNEL_SECURITY

GPCDMA_CHANNEL_CH3_BCOUNT_0

Offset: 0x40020

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH3_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

BCOUNT

GPCDMA_CHANNEL_CH3_DMA_BYTE_TRA_0

Offset: 0x40024

Read/Write: RO

Parity Protection: N

SCR Protection: SCR_CH3_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

TRANSFER_COUNT

GPCDMA_CHANNEL_CH3_DMA_BYTE_STA_0

Offset: 0x40028

Read/Write: RO

Parity Protection: N

SCR Protection: SCR_CH3_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

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Bit Reset Description

31:0 0x0

DMA_COUNT

GPCDMA_CHANNEL_CH3_ERR_STA_0

Offset: 0x40030

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH3_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

ERROR_STATUS

GPCDMA_CHANNEL_CH3_FIXED_PAT_0

Offset: 0x40034

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH3_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

FIXED_PATTERN

GPCDMA_CHANNEL_CH3_TZ_0

Offset: 0x40038

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_TZ_0

Reset: 0x00000003 (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xx11)

Bit Reset Description

1 0x1

MC_PROT_1

0 0x1

MMIO_PROT_1

GPCDMA_CHANNEL_CH4_CSR_0

Offset: 0x50000

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH4_0

Reset: 0x08008400 (0b00xx,1x00,0000,0000,1x00,01xx,xxxx,xxxx)

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Bit Reset Description

31 0x0

ENB:

= DISABLE0

= ENABLE1

30 0x0

IE_EOC:

= DISABLE0

= ENABLE1

27 0x1

ONCE:

= CYCLIC_MODE0

= SINGLE_BLOCK1

25:24 0x0

FC_MODE:

= NO_MMIO0

= ONE_MMIO1

= TWO_MMIO2

= FOUR_MMIO3

23:21 0x0

DMA_MODE:

= IO2MEM_NO_FC0

= IO2MEM_FC1

= MEM2IO_NO_FC2

= MEM2IO_FC3

= MEM2MEM4

= RSVD5

= FIXED_PAT6

20:16

0x0

REQ_SEL:

= I2C80

= I2C101

= UARTG2

= UARTC3

= QSPI05

= QSPI16

= UARTA8

= UARTB9

= UARTF12

= UARTH13

= SPI115

= SPI216

= SPI317

= UARTD19

= UARTE20

= I2C21

= I2C222

= I2C323

= I2C524

= I2C426

= I2C727

= I2C630

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Bit Reset Description

= I2C931

= RSVD29

15 0x1

IRQ_MASK:

= DISABLE0

= ENABLE1

13:10 0x1

WEIGHT

GPCDMA_CHANNEL_CH4_STA_0

Offset: 0x50004

Read/Write: See table below

Parity Protection: N

SCR Protection: SCR_CH4_0

Reset: 0x00000000 (0b00x0,0000,0x00,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit R/W Reset Description

31 RO 0x0

BSY:

= WAIT0

= ACTIVE1

30 RW 0x0

ISE_EOC:

= NO_INTR0

= INTR1

28 RO 0x0

PING_PONG_STA:

= PING_INTR_STA0

= PONG_INTR_STA1

27 RO 0x0

DMA_ACTIVITY:

= IDLE0

= BUSY1

26 RO 0x0

CHANNEL_PAUSE:

= RESUME0

= PAUSE1

25 RO 0x0

CHANNEL_RX:

= NOT_ACTIVE0

= ACTIVE1

24 RO 0x0

CHANNEL_TX:

= NOT_ACTIVE0

= ACTIVE1

23 RO 0x0

IRQ_INTR_STA:

= DISABLE0

= ENABLE1

0x0

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Bit R/W Reset Description

TRIG_STA:

= NOT_ACTIVE0

= ACTIVE1

20 RO 0x0

INTR_STA:

= NOT_ACTIVE0

= ACTIVE1

GPCDMA_CHANNEL_CH4_CSRE_0

Offset: 0x50008

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH4_0

Reset: 0x00000000 (0b0xxx,xxxx,xxxx,0000,00xx,xxxx,xxxx,xxxx)

Bit Reset Description

31 0x0

DMA_ACTIVITY:

= RESUME0

= PAUSE1

19:14

0x0

TRIG_SEL:

= SMP_241

= SMP_252

= SMP_263

= SMP_274

= XRQ_A5

= XRQ_B6

= TMR17

= TMR28

= CH09

= CH110

= CH211

= CH312

= CH413

= CH514

= CH615

= CH716

= CH817

= CH918

= CH1019

= CH1120

= CH1221

= CH1322

= CH1423

= CH1524

= CH1625

= CH1726

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Bit Reset Description

= CH1827

= CH1928

= CH2029

= CH2130

= CH2231

= CH2332

= CH2433

= CH2534

= CH2635

= CH2736

= CH2837

= CH2938

= CH3039

= CH3140

= RSVD0

GPCDMA_CHANNEL_CH4_SRC_PTR_0

Offset: 0x5000c

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH4_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

SRC_PTR

GPCDMA_CHANNEL_CH4_DST_PTR_0

Offset: 0x50010

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH4_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

DST_PTR

GPCDMA_CHANNEL_CH4_HI_ADR_PTR_0

Offset: 0x50014

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH4_0

Reset: 0x00000000 (0bxxxx,xxxx,0000,0000,xxxx,xxxx,0000,0000)

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Bit Reset Description

23:16 0x0

HI_DST_PTR

7:0 0x0

HI_SRC_PTR

GPCDMA_CHANNEL_CH4_MC_SEQ_0

Offset: 0x50018

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH4_0

Reset: 0x03800000 (0b0000,0011,1000,0000,0000,0000,0000,0000)

Bit Reset Description

31 0x0

MC_DATA_SWAP:

= DISABLE0

= ENABLE1

30:25 0x1

MC_REQ_CNT

24:23 0x3

MC_BURST:

= DMA_BURST_2WORDS0

= DMA_BURST_16WORDS3

22:20 0x0

MC_ADDR_WRAP1:

= NO_WRAP0

= WRAP_0N_32WORDS1

= WRAP_ON_64WORDS2

= WRAP_ON_128WORDS3

= WRAP_ON_256WORDS4

= WRAP_ON_512WORDS5

= WRAP_ON_1024WORDS6

= WRAP_ON_2048WORDS7

19:17 0x0

MC_ADDR_WRAP0:

= NO_WRAP0

= WRAP_0N_32WORDS1

= WRAP_ON_64WORDS2

= WRAP_ON_128WORDS3

= WRAP_ON_256WORDS4

= WRAP_ON_512WORDS5

= WRAP_ON_1024WORDS6

= WRAP_ON_2048WORDS7

16 0x0

MC_AXIID

15:14 0x0

MC_PROT

13:7 0x0

STREAMID1

6:0 0x0

STREAMID0

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GPCDMA_CHANNEL_CH4_MMIO_SEQ_0

Offset: 0x5001c

Read/Write: See table below

Parity Protection: N

SCR Protection: SCR_CH4_0

Reset: 0x2381007f (0b0010,0011,1000,0001,xxxx,xxx0,0111,1111)

Bit R/W Reset Description

31 RW 0x0

DBL_BUF:

= DISABLE0

= ENABLE1

30:28 RW 0x2

MMIO_BUS_WIDTH:

= BUS_WIDTH_80

= BUS_WIDTH_161

= BUS_WIDTH_322

27 RW 0x0

MMIO_DATA_SWAP:

= DISABLE0

= ENABLE1

26:23 RW 0x7

MMIO_BURST:

= DMA_BURST_1WORDS0

= DMA_BURST_2WORDS1

= DMA_BURST_4WORDS3

= DMA_BURST_8WORDS7

= DMA_BURST_16WORDS15

22:19 RO 0x0

MMIO_MASTER_ID:

= RSVD0

= CCPLEX1

= CCPLEX_DPMU2

= BPMP3

= SPE4

= SCE5

= DMA_PER6

= TSECA7

= TSECB8

= JTAGM9

= CSITE10

= APE11

18:16 RW 0x1

MMIO_ADDR_WRAP:

= NO_WRAP0

= WRAP_0N_1WORDS1

= WRAP_ON_2WORDS2

= WRAP_ON_4WORDS3

= WRAP_ON_8WORDS4

= WRAP_ON_16WORDS5

= WRAP_ON_32WORDS6

= WRAP_ON_64WORDS7

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Bit R/W Reset Description

8:7 RW 0x0

MMIO_PROT

6:0 RO 0x7f

MMIO_CHANNEL_SECURITY

GPCDMA_CHANNEL_CH4_BCOUNT_0

Offset: 0x50020

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH4_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

BCOUNT

GPCDMA_CHANNEL_CH4_DMA_BYTE_TRA_0

Offset: 0x50024

Read/Write: RO

Parity Protection: N

SCR Protection: SCR_CH4_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

TRANSFER_COUNT

GPCDMA_CHANNEL_CH4_DMA_BYTE_STA_0

Offset: 0x50028

Read/Write: RO

Parity Protection: N

SCR Protection: SCR_CH4_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

DMA_COUNT

GPCDMA_CHANNEL_CH4_ERR_STA_0

Offset: 0x50030

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH4_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

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Bit Reset Description

31:0 0x0

ERROR_STATUS

GPCDMA_CHANNEL_CH4_FIXED_PAT_0

Offset: 0x50034

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH4_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

FIXED_PATTERN

GPCDMA_CHANNEL_CH4_TZ_0

Offset: 0x50038

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_TZ_0

Reset: 0x00000003 (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xx11)

Bit Reset Description

1 0x1

MC_PROT_1

0 0x1

MMIO_PROT_1

GPCDMA_CHANNEL_CH5_CSR_0

Offset: 0x60000

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH5_0

Reset: 0x08008400 (0b00xx,1x00,0000,0000,1x00,01xx,xxxx,xxxx)

Bit Reset Description

31 0x0

ENB:

= DISABLE0

= ENABLE1

30 0x0

IE_EOC:

= DISABLE0

= ENABLE1

27 0x1

ONCE:

= CYCLIC_MODE0

= SINGLE_BLOCK1

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Bit Reset Description

25:24 0x0

FC_MODE:

= NO_MMIO0

= ONE_MMIO1

= TWO_MMIO2

= FOUR_MMIO3

23:21 0x0

DMA_MODE:

= IO2MEM_NO_FC0

= IO2MEM_FC1

= MEM2IO_NO_FC2

= MEM2IO_FC3

= MEM2MEM4

= RSVD5

= FIXED_PAT6

20:16 0x0

REQ_SEL:

= I2C80

= I2C101

= UARTG2

= UARTC3

= QSPI05

= QSPI16

= UARTA8

= UARTB9

= UARTF12

= UARTH13

= SPI115

= SPI216

= SPI317

= UARTD19

= UARTE20

= I2C21

= I2C222

= I2C323

= I2C524

= I2C426

= I2C727

= I2C630

= I2C931

= RSVD29

15 0x1

IRQ_MASK:

= DISABLE0

= ENABLE1

13:10 0x1

WEIGHT

GPCDMA_CHANNEL_CH5_STA_0

Offset: 0x60004

Read/Write: See table below

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Parity Protection: N

SCR Protection: SCR_CH5_0

Reset: 0x00000000 (0b00x0,0000,0x00,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit R/W Reset Description

31 RO 0x0

BSY:

= WAIT0

= ACTIVE1

30 RW 0x0

ISE_EOC:

= NO_INTR0

= INTR1

28 RO 0x0

PING_PONG_STA:

= PING_INTR_STA0

= PONG_INTR_STA1

27 RO 0x0

DMA_ACTIVITY:

= IDLE0

= BUSY1

26 RO 0x0

CHANNEL_PAUSE:

= RESUME0

= PAUSE1

25 RO 0x0

CHANNEL_RX:

= NOT_ACTIVE0

= ACTIVE1

24 RO 0x0

CHANNEL_TX:

= NOT_ACTIVE0

= ACTIVE1

23 RO 0x0

IRQ_INTR_STA:

= DISABLE0

= ENABLE1

21 RO 0x0

TRIG_STA:

= NOT_ACTIVE0

= ACTIVE1

20 RO 0x0

INTR_STA:

= NOT_ACTIVE0

= ACTIVE1

GPCDMA_CHANNEL_CH5_CSRE_0

Offset: 0x60008

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH5_0

Reset: 0x00000000 (0b0xxx,xxxx,xxxx,0000,00xx,xxxx,xxxx,xxxx)

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Bit Reset Description

31 0x0

DMA_ACTIVITY:

= RESUME0

= PAUSE1

19:14 0x0

TRIG_SEL:

= SMP_241

= SMP_252

= SMP_263

= SMP_274

= XRQ_A5

= XRQ_B6

= TMR17

= TMR28

= CH09

= CH110

= CH211

= CH312

= CH413

= CH514

= CH615

= CH716

= CH817

= CH918

= CH1019

= CH1120

= CH1221

= CH1322

= CH1423

= CH1524

= CH1625

= CH1726

= CH1827

= CH1928

= CH2029

= CH2130

= CH2231

= CH2332

= CH2433

= CH2534

= CH2635

= CH2736

= CH2837

= CH2938

= CH3039

= CH3140

= RSVD0

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GPCDMA_CHANNEL_CH5_SRC_PTR_0

Offset: 0x6000c

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH5_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

SRC_PTR

GPCDMA_CHANNEL_CH5_DST_PTR_0

Offset: 0x60010

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH5_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

DST_PTR

GPCDMA_CHANNEL_CH5_HI_ADR_PTR_0

Offset: 0x60014

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH5_0

Reset: 0x00000000 (0bxxxx,xxxx,0000,0000,xxxx,xxxx,0000,0000)

Bit Reset Description

23:16 0x0

HI_DST_PTR

7:0 0x0

HI_SRC_PTR

GPCDMA_CHANNEL_CH5_MC_SEQ_0

Offset: 0x60018

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH5_0

Reset: 0x03800000 (0b0000,0011,1000,0000,0000,0000,0000,0000)

Bit Reset Description

31 0x0

MC_DATA_SWAP:

= DISABLE0

= ENABLE1

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Bit Reset Description

30:25 0x1

MC_REQ_CNT

24:23 0x3

MC_BURST:

= DMA_BURST_2WORDS0

= DMA_BURST_16WORDS3

22:20 0x0

MC_ADDR_WRAP1:

= NO_WRAP0

= WRAP_0N_32WORDS1

= WRAP_ON_64WORDS2

= WRAP_ON_128WORDS3

= WRAP_ON_256WORDS4

= WRAP_ON_512WORDS5

= WRAP_ON_1024WORDS6

= WRAP_ON_2048WORDS7

19:17 0x0

MC_ADDR_WRAP0:

= NO_WRAP0

= WRAP_0N_32WORDS1

= WRAP_ON_64WORDS2

= WRAP_ON_128WORDS3

= WRAP_ON_256WORDS4

= WRAP_ON_512WORDS5

= WRAP_ON_1024WORDS6

= WRAP_ON_2048WORDS7

16 0x0

MC_AXIID

15:14 0x0

MC_PROT

13:7 0x0

STREAMID1

6:0 0x0

STREAMID0

GPCDMA_CHANNEL_CH5_MMIO_SEQ_0

Offset: 0x6001c

Read/Write: See table below

Parity Protection: N

SCR Protection: SCR_CH5_0

Reset: 0x2381007f (0b0010,0011,1000,0001,xxxx,xxx0,0111,1111)

Bit R/W Reset Description

31 RW 0x0

DBL_BUF:

= DISABLE0

= ENABLE1

30:28 RW 0x2

MMIO_BUS_WIDTH:

= BUS_WIDTH_80

= BUS_WIDTH_161

= BUS_WIDTH_322

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Bit R/W Reset Description

27 RW 0x0

MMIO_DATA_SWAP:

= DISABLE0

= ENABLE1

26:23 RW 0x7

MMIO_BURST:

= DMA_BURST_1WORDS0

= DMA_BURST_2WORDS1

= DMA_BURST_4WORDS3

= DMA_BURST_8WORDS7

= DMA_BURST_16WORDS15

22:19 RO 0x0

MMIO_MASTER_ID:

= RSVD0

= CCPLEX1

= CCPLEX_DPMU2

= BPMP3

= SPE4

= SCE5

= DMA_PER6

= TSECA7

= TSECB8

= JTAGM9

= CSITE10

= APE11

18:16 RW 0x1

MMIO_ADDR_WRAP:

= NO_WRAP0

= WRAP_0N_1WORDS1

= WRAP_ON_2WORDS2

= WRAP_ON_4WORDS3

= WRAP_ON_8WORDS4

= WRAP_ON_16WORDS5

= WRAP_ON_32WORDS6

= WRAP_ON_64WORDS7

8:7 RW 0x0

MMIO_PROT

6:0 RO 0x7f

MMIO_CHANNEL_SECURITY

GPCDMA_CHANNEL_CH5_BCOUNT_0

Offset: 0x60020

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH5_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

BCOUNT

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GPCDMA_CHANNEL_CH5_DMA_BYTE_TRA_0

Offset: 0x60024

Read/Write: RO

Parity Protection: N

SCR Protection: SCR_CH5_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

TRANSFER_COUNT

GPCDMA_CHANNEL_CH5_DMA_BYTE_STA_0

Offset: 0x60028

Read/Write: RO

Parity Protection: N

SCR Protection: SCR_CH5_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

DMA_COUNT

GPCDMA_CHANNEL_CH5_ERR_STA_0

Offset: 0x60030

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH5_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

ERROR_STATUS

GPCDMA_CHANNEL_CH5_FIXED_PAT_0

Offset: 0x60034

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH5_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

FIXED_PATTERN

GPCDMA_CHANNEL_CH5_TZ_0

Offset: 0x60038

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Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_TZ_0

Reset: 0x00000003 (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xx11)

Bit Reset Description

1 0x1

MC_PROT_1

0 0x1

MMIO_PROT_1

GPCDMA_CHANNEL_CH6_CSR_0

Offset: 0x70000

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH6_0

Reset: 0x08008400 (0b00xx,1x00,0000,0000,1x00,01xx,xxxx,xxxx)

Bit Reset Description

31 0x0

ENB:

= DISABLE0

= ENABLE1

30 0x0

IE_EOC:

= DISABLE0

= ENABLE1

27 0x1

ONCE:

= CYCLIC_MODE0

= SINGLE_BLOCK1

25:24 0x0

FC_MODE:

= NO_MMIO0

= ONE_MMIO1

= TWO_MMIO2

= FOUR_MMIO3

23:21 0x0

DMA_MODE:

= IO2MEM_NO_FC0

= IO2MEM_FC1

= MEM2IO_NO_FC2

= MEM2IO_FC3

= MEM2MEM4

= RSVD5

= FIXED_PAT6

20:16

0x0

REQ_SEL:

= I2C80

= I2C101

= UARTG2

= UARTC3

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Bit Reset Description

= QSPI05

= QSPI16

= UARTA8

= UARTB9

= UARTF12

= UARTH13

= SPI115

= SPI216

= SPI317

= UARTD19

= UARTE20

= I2C21

= I2C222

= I2C323

= I2C524

= I2C426

= I2C727

= I2C630

= I2C931

= RSVD29

15 0x1

IRQ_MASK:

= DISABLE0

= ENABLE1

13:10 0x1

WEIGHT

GPCDMA_CHANNEL_CH6_STA_0

Offset: 0x70004

Read/Write: See table below

Parity Protection: N

SCR Protection: SCR_CH6_0

Reset: 0x00000000 (0b00x0,0000,0x00,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit R/W Reset Description

31 RO 0x0

BSY:

= WAIT0

= ACTIVE1

30 RW 0x0

ISE_EOC:

= NO_INTR0

= INTR1

28 RO 0x0

PING_PONG_STA:

= PING_INTR_STA0

= PONG_INTR_STA1

0x0

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Bit R/W Reset Description

DMA_ACTIVITY:

= IDLE0

= BUSY1

26 RO 0x0

CHANNEL_PAUSE:

= RESUME0

= PAUSE1

25 RO 0x0

CHANNEL_RX:

= NOT_ACTIVE0

= ACTIVE1

24 RO 0x0

CHANNEL_TX:

= NOT_ACTIVE0

= ACTIVE1

23 RO 0x0

IRQ_INTR_STA:

= DISABLE0

= ENABLE1

21 RO 0x0

TRIG_STA:

= NOT_ACTIVE0

= ACTIVE1

20 RO 0x0

INTR_STA:

= NOT_ACTIVE0

= ACTIVE1

GPCDMA_CHANNEL_CH6_CSRE_0

Offset: 0x70008

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH6_0

Reset: 0x00000000 (0b0xxx,xxxx,xxxx,0000,00xx,xxxx,xxxx,xxxx)

Bit Reset Description

31 0x0

DMA_ACTIVITY:

= RESUME0

= PAUSE1

19:14

0x0

TRIG_SEL:

= SMP_241

= SMP_252

= SMP_263

= SMP_274

= XRQ_A5

= XRQ_B6

= TMR17

= TMR28

= CH09

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Bit Reset Description

= CH110

= CH211

= CH312

= CH413

= CH514

= CH615

= CH716

= CH817

= CH918

= CH1019

= CH1120

= CH1221

= CH1322

= CH1423

= CH1524

= CH1625

= CH1726

= CH1827

= CH1928

= CH2029

= CH2130

= CH2231

= CH2332

= CH2433

= CH2534

= CH2635

= CH2736

= CH2837

= CH2938

= CH3039

= CH3140

= RSVD0

GPCDMA_CHANNEL_CH6_SRC_PTR_0

Offset: 0x7000c

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH6_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

SRC_PTR

GPCDMA_CHANNEL_CH6_DST_PTR_0

Offset: 0x70010

Read/Write: R/W

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Parity Protection: N

SCR Protection: SCR_CH6_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

DST_PTR

GPCDMA_CHANNEL_CH6_HI_ADR_PTR_0

Offset: 0x70014

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH6_0

Reset: 0x00000000 (0bxxxx,xxxx,0000,0000,xxxx,xxxx,0000,0000)

Bit Reset Description

23:16 0x0

HI_DST_PTR

7:0 0x0

HI_SRC_PTR

GPCDMA_CHANNEL_CH6_MC_SEQ_0

Offset: 0x70018

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH6_0

Reset: 0x03800000 (0b0000,0011,1000,0000,0000,0000,0000,0000)

Bit Reset Description

31 0x0

MC_DATA_SWAP:

= DISABLE0

= ENABLE1

30:25 0x1

MC_REQ_CNT

24:23 0x3

MC_BURST:

= DMA_BURST_2WORDS0

= DMA_BURST_16WORDS3

22:20 0x0

MC_ADDR_WRAP1:

= NO_WRAP0

= WRAP_0N_32WORDS1

= WRAP_ON_64WORDS2

= WRAP_ON_128WORDS3

= WRAP_ON_256WORDS4

= WRAP_ON_512WORDS5

= WRAP_ON_1024WORDS6

= WRAP_ON_2048WORDS7

19:17

0x0

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Bit Reset Description

MC_ADDR_WRAP0:

= NO_WRAP0

= WRAP_0N_32WORDS1

= WRAP_ON_64WORDS2

= WRAP_ON_128WORDS3

= WRAP_ON_256WORDS4

= WRAP_ON_512WORDS5

= WRAP_ON_1024WORDS6

= WRAP_ON_2048WORDS7

16 0x0

MC_AXIID

15:14 0x0

MC_PROT

13:7 0x0

STREAMID1

6:0 0x0

STREAMID0

GPCDMA_CHANNEL_CH6_MMIO_SEQ_0

Offset: 0x7001c

Read/Write: See table below

Parity Protection: N

SCR Protection: SCR_CH6_0

Reset: 0x2381007f (0b0010,0011,1000,0001,xxxx,xxx0,0111,1111)

Bit R/W Reset Description

31 RW 0x0

DBL_BUF:

= DISABLE0

= ENABLE1

30:28 RW 0x2

MMIO_BUS_WIDTH:

= BUS_WIDTH_80

= BUS_WIDTH_161

= BUS_WIDTH_322

27 RW 0x0

MMIO_DATA_SWAP:

= DISABLE0

= ENABLE1

26:23 RW 0x7

MMIO_BURST:

= DMA_BURST_1WORDS0

= DMA_BURST_2WORDS1

= DMA_BURST_4WORDS3

= DMA_BURST_8WORDS7

= DMA_BURST_16WORDS15

22:19

0x0

MMIO_MASTER_ID:

= RSVD0

= CCPLEX1

= CCPLEX_DPMU2

= BPMP3

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Bit R/W Reset Description

= SPE4

= SCE5

= DMA_PER6

= TSECA7

= TSECB8

= JTAGM9

= CSITE10

= APE11

18:16 RW 0x1

MMIO_ADDR_WRAP:

= NO_WRAP0

= WRAP_0N_1WORDS1

= WRAP_ON_2WORDS2

= WRAP_ON_4WORDS3

= WRAP_ON_8WORDS4

= WRAP_ON_16WORDS5

= WRAP_ON_32WORDS6

= WRAP_ON_64WORDS7

8:7 RW 0x0

MMIO_PROT

6:0 RO 0x7f

MMIO_CHANNEL_SECURITY

GPCDMA_CHANNEL_CH6_BCOUNT_0

Offset: 0x70020

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH6_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

BCOUNT

GPCDMA_CHANNEL_CH6_DMA_BYTE_TRA_0

Offset: 0x70024

Read/Write: RO

Parity Protection: N

SCR Protection: SCR_CH6_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

TRANSFER_COUNT

GPCDMA_CHANNEL_CH6_DMA_BYTE_STA_0

Offset: 0x70028

Read/Write: RO

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Parity Protection: N

SCR Protection: SCR_CH6_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

DMA_COUNT

GPCDMA_CHANNEL_CH6_ERR_STA_0

Offset: 0x70030

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH6_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

ERROR_STATUS

GPCDMA_CHANNEL_CH6_FIXED_PAT_0

Offset: 0x70034

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH6_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

FIXED_PATTERN

GPCDMA_CHANNEL_CH6_TZ_0

Offset: 0x70038

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_TZ_0

Reset: 0x00000003 (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xx11)

Bit Reset Description

1 0x1

MC_PROT_1

0 0x1

MMIO_PROT_1

GPCDMA_CHANNEL_CH7_CSR_0

Offset: 0x80000

Read/Write: R/W

Parity Protection: N

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SCR Protection: SCR_CH7_0

Reset: 0x08008400 (0b00xx,1x00,0000,0000,1x00,01xx,xxxx,xxxx)

Bit Reset Description

31 0x0

ENB:

= DISABLE0

= ENABLE1

30 0x0

IE_EOC:

= DISABLE0

= ENABLE1

27 0x1

ONCE:

= CYCLIC_MODE0

= SINGLE_BLOCK1

25:24 0x0

FC_MODE:

= NO_MMIO0

= ONE_MMIO1

= TWO_MMIO2

= FOUR_MMIO3

23:21 0x0

DMA_MODE:

= IO2MEM_NO_FC0

= IO2MEM_FC1

= MEM2IO_NO_FC2

= MEM2IO_FC3

= MEM2MEM4

= RSVD5

= FIXED_PAT6

20:16

0x0

REQ_SEL:

= I2C80

= I2C101

= UARTG2

= UARTC3

= QSPI05

= QSPI16

= UARTA8

= UARTB9

= UARTF12

= UARTH13

= SPI115

= SPI216

= SPI317

= UARTD19

= UARTE20

= I2C21

= I2C222

= I2C323

= I2C524

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Bit Reset Description

= I2C426

= I2C727

= I2C630

= I2C931

= RSVD29

15 0x1

IRQ_MASK:

= DISABLE0

= ENABLE1

13:10 0x1

WEIGHT

GPCDMA_CHANNEL_CH7_STA_0

Offset: 0x80004

Read/Write: See table below

Parity Protection: N

SCR Protection: SCR_CH7_0

Reset: 0x00000000 (0b00x0,0000,0x00,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit R/W Reset Description

31 RO 0x0

BSY:

= WAIT0

= ACTIVE1

30 RW 0x0

ISE_EOC:

= NO_INTR0

= INTR1

28 RO 0x0

PING_PONG_STA:

= PING_INTR_STA0

= PONG_INTR_STA1

27 RO 0x0

DMA_ACTIVITY:

= IDLE0

= BUSY1

26 RO 0x0

CHANNEL_PAUSE:

= RESUME0

= PAUSE1

25 RO 0x0

CHANNEL_RX:

= NOT_ACTIVE0

= ACTIVE1

24 RO 0x0

CHANNEL_TX:

= NOT_ACTIVE0

= ACTIVE1

23 RO 0x0

IRQ_INTR_STA:

= DISABLE0

= ENABLE1

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Bit R/W Reset Description

21 RO 0x0

TRIG_STA:

= NOT_ACTIVE0

= ACTIVE1

20 RO 0x0

INTR_STA:

= NOT_ACTIVE0

= ACTIVE1

GPCDMA_CHANNEL_CH7_CSRE_0

Offset: 0x80008

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH7_0

Reset: 0x00000000 (0b0xxx,xxxx,xxxx,0000,00xx,xxxx,xxxx,xxxx)

Bit Reset Description

31 0x0

DMA_ACTIVITY:

= RESUME0

= PAUSE1

19:14

0x0

TRIG_SEL:

= SMP_241

= SMP_252

= SMP_263

= SMP_274

= XRQ_A5

= XRQ_B6

= TMR17

= TMR28

= CH09

= CH110

= CH211

= CH312

= CH413

= CH514

= CH615

= CH716

= CH817

= CH918

= CH1019

= CH1120

= CH1221

= CH1322

= CH1423

= CH1524

= CH1625

= CH1726

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Bit Reset Description

= CH1827

= CH1928

= CH2029

= CH2130

= CH2231

= CH2332

= CH2433

= CH2534

= CH2635

= CH2736

= CH2837

= CH2938

= CH3039

= CH3140

= RSVD0

GPCDMA_CHANNEL_CH7_SRC_PTR_0

Offset: 0x8000c

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH7_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

SRC_PTR

GPCDMA_CHANNEL_CH7_DST_PTR_0

Offset: 0x80010

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH7_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

DST_PTR

GPCDMA_CHANNEL_CH7_HI_ADR_PTR_0

Offset: 0x80014

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH7_0

Reset: 0x00000000 (0bxxxx,xxxx,0000,0000,xxxx,xxxx,0000,0000)

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Bit Reset Description

23:16 0x0

HI_DST_PTR

7:0 0x0

HI_SRC_PTR

GPCDMA_CHANNEL_CH7_MC_SEQ_0

Offset: 0x80018

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH7_0

Reset: 0x03800000 (0b0000,0011,1000,0000,0000,0000,0000,0000)

Bit Reset Description

31 0x0

MC_DATA_SWAP:

= DISABLE0

= ENABLE1

30:25 0x1

MC_REQ_CNT

24:23 0x3

MC_BURST:

= DMA_BURST_2WORDS0

= DMA_BURST_16WORDS3

22:20 0x0

MC_ADDR_WRAP1:

= NO_WRAP0

= WRAP_0N_32WORDS1

= WRAP_ON_64WORDS2

= WRAP_ON_128WORDS3

= WRAP_ON_256WORDS4

= WRAP_ON_512WORDS5

= WRAP_ON_1024WORDS6

= WRAP_ON_2048WORDS7

19:17 0x0

MC_ADDR_WRAP0:

= NO_WRAP0

= WRAP_0N_32WORDS1

= WRAP_ON_64WORDS2

= WRAP_ON_128WORDS3

= WRAP_ON_256WORDS4

= WRAP_ON_512WORDS5

= WRAP_ON_1024WORDS6

= WRAP_ON_2048WORDS7

16 0x0

MC_AXIID

15:14 0x0

MC_PROT

13:7 0x0

STREAMID1

6:0 0x0

STREAMID0

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GPCDMA_CHANNEL_CH7_MMIO_SEQ_0

Offset: 0x8001c

Read/Write: See table below

Parity Protection: N

SCR Protection: SCR_CH7_0

Reset: 0x2381007f (0b0010,0011,1000,0001,xxxx,xxx0,0111,1111)

Bit R/W Reset Description

31 RW 0x0

DBL_BUF:

= DISABLE0

= ENABLE1

30:28 RW 0x2

MMIO_BUS_WIDTH:

= BUS_WIDTH_80

= BUS_WIDTH_161

= BUS_WIDTH_322

27 RW 0x0

MMIO_DATA_SWAP:

= DISABLE0

= ENABLE1

26:23 RW 0x7

MMIO_BURST:

= DMA_BURST_1WORDS0

= DMA_BURST_2WORDS1

= DMA_BURST_4WORDS3

= DMA_BURST_8WORDS7

= DMA_BURST_16WORDS15

22:19 RO 0x0

MMIO_MASTER_ID:

= RSVD0

= CCPLEX1

= CCPLEX_DPMU2

= BPMP3

= SPE4

= SCE5

= DMA_PER6

= TSECA7

= TSECB8

= JTAGM9

= CSITE10

= APE11

18:16 RW 0x1

MMIO_ADDR_WRAP:

= NO_WRAP0

= WRAP_0N_1WORDS1

= WRAP_ON_2WORDS2

= WRAP_ON_4WORDS3

= WRAP_ON_8WORDS4

= WRAP_ON_16WORDS5

= WRAP_ON_32WORDS6

= WRAP_ON_64WORDS7

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Bit R/W Reset Description

8:7 RW 0x0

MMIO_PROT

6:0 RO 0x7f

MMIO_CHANNEL_SECURITY

GPCDMA_CHANNEL_CH7_BCOUNT_0

Offset: 0x80020

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH7_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

BCOUNT

GPCDMA_CHANNEL_CH7_DMA_BYTE_TRA_0

Offset: 0x80024

Read/Write: RO

Parity Protection: N

SCR Protection: SCR_CH7_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

TRANSFER_COUNT

GPCDMA_CHANNEL_CH7_DMA_BYTE_STA_0

Offset: 0x80028

Read/Write: RO

Parity Protection: N

SCR Protection: SCR_CH7_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

DMA_COUNT

GPCDMA_CHANNEL_CH7_ERR_STA_0

Offset: 0x80030

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH7_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

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Bit Reset Description

31:0 0x0

ERROR_STATUS

GPCDMA_CHANNEL_CH7_FIXED_PAT_0

Offset: 0x80034

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH7_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

FIXED_PATTERN

GPCDMA_CHANNEL_CH7_TZ_0

Offset: 0x80038

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_TZ_0

Reset: 0x00000003 (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xx11)

Bit Reset Description

1 0x1

MC_PROT_1

0 0x1

MMIO_PROT_1

GPCDMA_CHANNEL_CH8_CSR_0

Offset: 0x90000

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH8_0

Reset: 0x08008400 (0b00xx,1x00,0000,0000,1x00,01xx,xxxx,xxxx)

Bit Reset Description

31 0x0

ENB:

= DISABLE0

= ENABLE1

30 0x0

IE_EOC:

= DISABLE0

= ENABLE1

27 0x1

ONCE:

= CYCLIC_MODE0

= SINGLE_BLOCK1

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Bit Reset Description

25:24 0x0

FC_MODE:

= NO_MMIO0

= ONE_MMIO1

= TWO_MMIO2

= FOUR_MMIO3

23:21 0x0

DMA_MODE:

= IO2MEM_NO_FC0

= IO2MEM_FC1

= MEM2IO_NO_FC2

= MEM2IO_FC3

= MEM2MEM4

= RSVD5

= FIXED_PAT6

20:16 0x0

REQ_SEL:

= I2C80

= I2C101

= UARTG2

= UARTC3

= QSPI05

= QSPI16

= UARTA8

= UARTB9

= UARTF12

= UARTH13

= SPI115

= SPI216

= SPI317

= UARTD19

= UARTE20

= I2C21

= I2C222

= I2C323

= I2C524

= I2C426

= I2C727

= I2C630

= I2C931

= RSVD29

15 0x1

IRQ_MASK:

= DISABLE0

= ENABLE1

13:10 0x1

WEIGHT

GPCDMA_CHANNEL_CH8_STA_0

Offset: 0x90004

Read/Write: See table below

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Parity Protection: N

SCR Protection: SCR_CH8_0

Reset: 0x00000000 (0b00x0,0000,0x00,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit R/W Reset Description

31 RO 0x0

BSY:

= WAIT0

= ACTIVE1

30 RW 0x0

ISE_EOC:

= NO_INTR0

= INTR1

28 RO 0x0

PING_PONG_STA:

= PING_INTR_STA0

= PONG_INTR_STA1

27 RO 0x0

DMA_ACTIVITY:

= IDLE0

= BUSY1

26 RO 0x0

CHANNEL_PAUSE:

= RESUME0

= PAUSE1

25 RO 0x0

CHANNEL_RX:

= NOT_ACTIVE0

= ACTIVE1

24 RO 0x0

CHANNEL_TX:

= NOT_ACTIVE0

= ACTIVE1

23 RO 0x0

IRQ_INTR_STA:

= DISABLE0

= ENABLE1

21 RO 0x0

TRIG_STA:

= NOT_ACTIVE0

= ACTIVE1

20 RO 0x0

INTR_STA:

= NOT_ACTIVE0

= ACTIVE1

GPCDMA_CHANNEL_CH8_CSRE_0

Offset: 0x90008

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH8_0

Reset: 0x00000000 (0b0xxx,xxxx,xxxx,0000,00xx,xxxx,xxxx,xxxx)

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Bit Reset Description

31 0x0

DMA_ACTIVITY:

= RESUME0

= PAUSE1

19:14 0x0

TRIG_SEL:

= SMP_241

= SMP_252

= SMP_263

= SMP_274

= XRQ_A5

= XRQ_B6

= TMR17

= TMR28

= CH09

= CH110

= CH211

= CH312

= CH413

= CH514

= CH615

= CH716

= CH817

= CH918

= CH1019

= CH1120

= CH1221

= CH1322

= CH1423

= CH1524

= CH1625

= CH1726

= CH1827

= CH1928

= CH2029

= CH2130

= CH2231

= CH2332

= CH2433

= CH2534

= CH2635

= CH2736

= CH2837

= CH2938

= CH3039

= CH3140

= RSVD0

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GPCDMA_CHANNEL_CH8_SRC_PTR_0

Offset: 0x9000c

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH8_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

SRC_PTR

GPCDMA_CHANNEL_CH8_DST_PTR_0

Offset: 0x90010

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH8_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

DST_PTR

GPCDMA_CHANNEL_CH8_HI_ADR_PTR_0

Offset: 0x90014

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH8_0

Reset: 0x00000000 (0bxxxx,xxxx,0000,0000,xxxx,xxxx,0000,0000)

Bit Reset Description

23:16 0x0

HI_DST_PTR

7:0 0x0

HI_SRC_PTR

GPCDMA_CHANNEL_CH8_MC_SEQ_0

Offset: 0x90018

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH8_0

Reset: 0x03800000 (0b0000,0011,1000,0000,0000,0000,0000,0000)

Bit Reset Description

31 0x0

MC_DATA_SWAP:

= DISABLE0

= ENABLE1

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Bit Reset Description

30:25 0x1

MC_REQ_CNT

24:23 0x3

MC_BURST:

= DMA_BURST_2WORDS0

= DMA_BURST_16WORDS3

22:20 0x0

MC_ADDR_WRAP1:

= NO_WRAP0

= WRAP_0N_32WORDS1

= WRAP_ON_64WORDS2

= WRAP_ON_128WORDS3

= WRAP_ON_256WORDS4

= WRAP_ON_512WORDS5

= WRAP_ON_1024WORDS6

= WRAP_ON_2048WORDS7

19:17 0x0

MC_ADDR_WRAP0:

= NO_WRAP0

= WRAP_0N_32WORDS1

= WRAP_ON_64WORDS2

= WRAP_ON_128WORDS3

= WRAP_ON_256WORDS4

= WRAP_ON_512WORDS5

= WRAP_ON_1024WORDS6

= WRAP_ON_2048WORDS7

16 0x0

MC_AXIID

15:14 0x0

MC_PROT

13:7 0x0

STREAMID1

6:0 0x0

STREAMID0

GPCDMA_CHANNEL_CH8_MMIO_SEQ_0

Offset: 0x9001c

Read/Write: See table below

Parity Protection: N

SCR Protection: SCR_CH8_0

Reset: 0x2381007f (0b0010,0011,1000,0001,xxxx,xxx0,0111,1111)

Bit R/W Reset Description

31 RW 0x0

DBL_BUF:

= DISABLE0

= ENABLE1

30:28 RW 0x2

MMIO_BUS_WIDTH:

= BUS_WIDTH_80

= BUS_WIDTH_161

= BUS_WIDTH_322

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Bit R/W Reset Description

27 RW 0x0

MMIO_DATA_SWAP:

= DISABLE0

= ENABLE1

26:23 RW 0x7

MMIO_BURST:

= DMA_BURST_1WORDS0

= DMA_BURST_2WORDS1

= DMA_BURST_4WORDS3

= DMA_BURST_8WORDS7

= DMA_BURST_16WORDS15

22:19 RO 0x0

MMIO_MASTER_ID:

= RSVD0

= CCPLEX1

= CCPLEX_DPMU2

= BPMP3

= SPE4

= SCE5

= DMA_PER6

= TSECA7

= TSECB8

= JTAGM9

= CSITE10

= APE11

18:16 RW 0x1

MMIO_ADDR_WRAP:

= NO_WRAP0

= WRAP_0N_1WORDS1

= WRAP_ON_2WORDS2

= WRAP_ON_4WORDS3

= WRAP_ON_8WORDS4

= WRAP_ON_16WORDS5

= WRAP_ON_32WORDS6

= WRAP_ON_64WORDS7

8:7 RW 0x0

MMIO_PROT

6:0 RO 0x7f

MMIO_CHANNEL_SECURITY

GPCDMA_CHANNEL_CH8_BCOUNT_0

Offset: 0x90020

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH8_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

BCOUNT

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GPCDMA_CHANNEL_CH8_DMA_BYTE_TRA_0

Offset: 0x90024

Read/Write: RO

Parity Protection: N

SCR Protection: SCR_CH8_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

TRANSFER_COUNT

GPCDMA_CHANNEL_CH8_DMA_BYTE_STA_0

Offset: 0x90028

Read/Write: RO

Parity Protection: N

SCR Protection: SCR_CH8_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

DMA_COUNT

GPCDMA_CHANNEL_CH8_ERR_STA_0

Offset: 0x90030

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH8_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

ERROR_STATUS

GPCDMA_CHANNEL_CH8_FIXED_PAT_0

Offset: 0x90034

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH8_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

FIXED_PATTERN

GPCDMA_CHANNEL_CH8_TZ_0

Offset: 0x90038

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Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_TZ_0

Reset: 0x00000003 (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xx11)

Bit Reset Description

1 0x1

MC_PROT_1

0 0x1

MMIO_PROT_1

GPCDMA_CHANNEL_CH9_CSR_0

Offset: 0xa0000

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH9_0

Reset: 0x08008400 (0b00xx,1x00,0000,0000,1x00,01xx,xxxx,xxxx)

Bit Reset Description

31 0x0

ENB:

= DISABLE0

= ENABLE1

30 0x0

IE_EOC:

= DISABLE0

= ENABLE1

27 0x1

ONCE:

= CYCLIC_MODE0

= SINGLE_BLOCK1

25:24 0x0

FC_MODE:

= NO_MMIO0

= ONE_MMIO1

= TWO_MMIO2

= FOUR_MMIO3

23:21 0x0

DMA_MODE:

= IO2MEM_NO_FC0

= IO2MEM_FC1

= MEM2IO_NO_FC2

= MEM2IO_FC3

= MEM2MEM4

= RSVD5

= FIXED_PAT6

20:16

0x0

REQ_SEL:

= I2C80

= I2C101

= UARTG2

= UARTC3

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Bit Reset Description

= QSPI05

= QSPI16

= UARTA8

= UARTB9

= UARTF12

= UARTH13

= SPI115

= SPI216

= SPI317

= UARTD19

= UARTE20

= I2C21

= I2C222

= I2C323

= I2C524

= I2C426

= I2C727

= I2C630

= I2C931

= RSVD29

15 0x1

IRQ_MASK:

= DISABLE0

= ENABLE1

13:10 0x1

WEIGHT

GPCDMA_CHANNEL_CH9_STA_0

Offset: 0xa0004

Read/Write: See table below

Parity Protection: N

SCR Protection: SCR_CH9_0

Reset: 0x00000000 (0b00x0,0000,0x00,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit R/W Reset Description

31 RO 0x0

BSY:

= WAIT0

= ACTIVE1

30 RW 0x0

ISE_EOC:

= NO_INTR0

= INTR1

28 RO 0x0

PING_PONG_STA:

= PING_INTR_STA0

= PONG_INTR_STA1

0x0

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Bit R/W Reset Description

DMA_ACTIVITY:

= IDLE0

= BUSY1

26 RO 0x0

CHANNEL_PAUSE:

= RESUME0

= PAUSE1

25 RO 0x0

CHANNEL_RX:

= NOT_ACTIVE0

= ACTIVE1

24 RO 0x0

CHANNEL_TX:

= NOT_ACTIVE0

= ACTIVE1

23 RO 0x0

IRQ_INTR_STA:

= DISABLE0

= ENABLE1

21 RO 0x0

TRIG_STA:

= NOT_ACTIVE0

= ACTIVE1

20 RO 0x0

INTR_STA:

= NOT_ACTIVE0

= ACTIVE1

GPCDMA_CHANNEL_CH9_CSRE_0

Offset: 0xa0008

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH9_0

Reset: 0x00000000 (0b0xxx,xxxx,xxxx,0000,00xx,xxxx,xxxx,xxxx)

Bit Reset Description

31 0x0

DMA_ACTIVITY:

= RESUME0

= PAUSE1

19:14

0x0

TRIG_SEL:

= SMP_241

= SMP_252

= SMP_263

= SMP_274

= XRQ_A5

= XRQ_B6

= TMR17

= TMR28

= CH09

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Bit Reset Description

= CH110

= CH211

= CH312

= CH413

= CH514

= CH615

= CH716

= CH817

= CH918

= CH1019

= CH1120

= CH1221

= CH1322

= CH1423

= CH1524

= CH1625

= CH1726

= CH1827

= CH1928

= CH2029

= CH2130

= CH2231

= CH2332

= CH2433

= CH2534

= CH2635

= CH2736

= CH2837

= CH2938

= CH3039

= CH3140

= RSVD0

GPCDMA_CHANNEL_CH9_SRC_PTR_0

Offset: 0xa000c

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH9_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

SRC_PTR

GPCDMA_CHANNEL_CH9_DST_PTR_0

Offset: 0xa0010

Read/Write: R/W

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Parity Protection: N

SCR Protection: SCR_CH9_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

DST_PTR

GPCDMA_CHANNEL_CH9_HI_ADR_PTR_0

Offset: 0xa0014

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH9_0

Reset: 0x00000000 (0bxxxx,xxxx,0000,0000,xxxx,xxxx,0000,0000)

Bit Reset Description

23:16 0x0

HI_DST_PTR

7:0 0x0

HI_SRC_PTR

GPCDMA_CHANNEL_CH9_MC_SEQ_0

Offset: 0xa0018

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH9_0

Reset: 0x03800000 (0b0000,0011,1000,0000,0000,0000,0000,0000)

Bit Reset Description

31 0x0

MC_DATA_SWAP:

= DISABLE0

= ENABLE1

30:25 0x1

MC_REQ_CNT

24:23 0x3

MC_BURST:

= DMA_BURST_2WORDS0

= DMA_BURST_16WORDS3

22:20 0x0

MC_ADDR_WRAP1:

= NO_WRAP0

= WRAP_0N_32WORDS1

= WRAP_ON_64WORDS2

= WRAP_ON_128WORDS3

= WRAP_ON_256WORDS4

= WRAP_ON_512WORDS5

= WRAP_ON_1024WORDS6

= WRAP_ON_2048WORDS7

19:17

0x0

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Bit Reset Description

MC_ADDR_WRAP0:

= NO_WRAP0

= WRAP_0N_32WORDS1

= WRAP_ON_64WORDS2

= WRAP_ON_128WORDS3

= WRAP_ON_256WORDS4

= WRAP_ON_512WORDS5

= WRAP_ON_1024WORDS6

= WRAP_ON_2048WORDS7

16 0x0

MC_AXIID

15:14 0x0

MC_PROT

13:7 0x0

STREAMID1

6:0 0x0

STREAMID0

GPCDMA_CHANNEL_CH9_MMIO_SEQ_0

Offset: 0xa001c

Read/Write: See table below

Parity Protection: N

SCR Protection: SCR_CH9_0

Reset: 0x2381007f (0b0010,0011,1000,0001,xxxx,xxx0,0111,1111)

Bit R/W Reset Description

31 RW 0x0

DBL_BUF:

= DISABLE0

= ENABLE1

30:28 RW 0x2

MMIO_BUS_WIDTH:

= BUS_WIDTH_80

= BUS_WIDTH_161

= BUS_WIDTH_322

27 RW 0x0

MMIO_DATA_SWAP:

= DISABLE0

= ENABLE1

26:23 RW 0x7

MMIO_BURST:

= DMA_BURST_1WORDS0

= DMA_BURST_2WORDS1

= DMA_BURST_4WORDS3

= DMA_BURST_8WORDS7

= DMA_BURST_16WORDS15

22:19

0x0

MMIO_MASTER_ID:

= RSVD0

= CCPLEX1

= CCPLEX_DPMU2

= BPMP3

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Bit R/W Reset Description

= SPE4

= SCE5

= DMA_PER6

= TSECA7

= TSECB8

= JTAGM9

= CSITE10

= APE11

18:16 RW 0x1

MMIO_ADDR_WRAP:

= NO_WRAP0

= WRAP_0N_1WORDS1

= WRAP_ON_2WORDS2

= WRAP_ON_4WORDS3

= WRAP_ON_8WORDS4

= WRAP_ON_16WORDS5

= WRAP_ON_32WORDS6

= WRAP_ON_64WORDS7

8:7 RW 0x0

MMIO_PROT

6:0 RO 0x7f

MMIO_CHANNEL_SECURITY

GPCDMA_CHANNEL_CH9_BCOUNT_0

Offset: 0xa0020

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH9_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

BCOUNT

GPCDMA_CHANNEL_CH9_DMA_BYTE_TRA_0

Offset: 0xa0024

Read/Write: RO

Parity Protection: N

SCR Protection: SCR_CH9_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

TRANSFER_COUNT

GPCDMA_CHANNEL_CH9_DMA_BYTE_STA_0

Offset: 0xa0028

Read/Write: RO

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Parity Protection: N

SCR Protection: SCR_CH9_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

DMA_COUNT

GPCDMA_CHANNEL_CH9_ERR_STA_0

Offset: 0xa0030

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH9_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

ERROR_STATUS

GPCDMA_CHANNEL_CH9_FIXED_PAT_0

Offset: 0xa0034

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH9_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

FIXED_PATTERN

GPCDMA_CHANNEL_CH9_TZ_0

Offset: 0xa0038

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_TZ_0

Reset: 0x00000003 (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xx11)

Bit Reset Description

1 0x1

MC_PROT_1

0 0x1

MMIO_PROT_1

GPCDMA_CHANNEL_CH10_CSR_0

Offset: 0xb0000

Read/Write: R/W

Parity Protection: N

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SCR Protection: SCR_CH10_0

Reset: 0x08008400 (0b00xx,1x00,0000,0000,1x00,01xx,xxxx,xxxx)

Bit Reset Description

31 0x0

ENB:

= DISABLE0

= ENABLE1

30 0x0

IE_EOC:

= DISABLE0

= ENABLE1

27 0x1

ONCE:

= CYCLIC_MODE0

= SINGLE_BLOCK1

25:24 0x0

FC_MODE:

= NO_MMIO0

= ONE_MMIO1

= TWO_MMIO2

= FOUR_MMIO3

23:21 0x0

DMA_MODE:

= IO2MEM_NO_FC0

= IO2MEM_FC1

= MEM2IO_NO_FC2

= MEM2IO_FC3

= MEM2MEM4

= RSVD5

= FIXED_PAT6

20:16

0x0

REQ_SEL:

= I2C80

= I2C101

= UARTG2

= UARTC3

= QSPI05

= QSPI16

= UARTA8

= UARTB9

= UARTF12

= UARTH13

= SPI115

= SPI216

= SPI317

= UARTD19

= UARTE20

= I2C21

= I2C222

= I2C323

= I2C524

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Bit Reset Description

= I2C426

= I2C727

= I2C630

= I2C931

= RSVD29

15 0x1

IRQ_MASK:

= DISABLE0

= ENABLE1

13:10 0x1

WEIGHT

GPCDMA_CHANNEL_CH10_STA_0

Offset: 0xb0004

Read/Write: See table below

Parity Protection: N

SCR Protection: SCR_CH10_0

Reset: 0x00000000 (0b00x0,0000,0x00,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit R/W Reset Description

31 RO 0x0

BSY:

= WAIT0

= ACTIVE1

30 RW 0x0

ISE_EOC:

= NO_INTR0

= INTR1

28 RO 0x0

PING_PONG_STA:

= PING_INTR_STA0

= PONG_INTR_STA1

27 RO 0x0

DMA_ACTIVITY:

= IDLE0

= BUSY1

26 RO 0x0

CHANNEL_PAUSE:

= RESUME0

= PAUSE1

25 RO 0x0

CHANNEL_RX:

= NOT_ACTIVE0

= ACTIVE1

24 RO 0x0

CHANNEL_TX:

= NOT_ACTIVE0

= ACTIVE1

23 RO 0x0

IRQ_INTR_STA:

= DISABLE0

= ENABLE1

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Bit R/W Reset Description

21 RO 0x0

TRIG_STA:

= NOT_ACTIVE0

= ACTIVE1

20 RO 0x0

INTR_STA:

= NOT_ACTIVE0

= ACTIVE1

GPCDMA_CHANNEL_CH10_CSRE_0

Offset: 0xb0008

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH10_0

Reset: 0x00000000 (0b0xxx,xxxx,xxxx,0000,00xx,xxxx,xxxx,xxxx)

Bit Reset Description

31 0x0

DMA_ACTIVITY:

= RESUME0

= PAUSE1

19:14

0x0

TRIG_SEL:

= SMP_241

= SMP_252

= SMP_263

= SMP_274

= XRQ_A5

= XRQ_B6

= TMR17

= TMR28

= CH09

= CH110

= CH211

= CH312

= CH413

= CH514

= CH615

= CH716

= CH817

= CH918

= CH1019

= CH1120

= CH1221

= CH1322

= CH1423

= CH1524

= CH1625

= CH1726

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Bit Reset Description

= CH1827

= CH1928

= CH2029

= CH2130

= CH2231

= CH2332

= CH2433

= CH2534

= CH2635

= CH2736

= CH2837

= CH2938

= CH3039

= CH3140

= RSVD0

GPCDMA_CHANNEL_CH10_SRC_PTR_0

Offset: 0xb000c

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH10_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

SRC_PTR

GPCDMA_CHANNEL_CH10_DST_PTR_0

Offset: 0xb0010

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH10_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

DST_PTR

GPCDMA_CHANNEL_CH10_HI_ADR_PTR_0

Offset: 0xb0014

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH10_0

Reset: 0x00000000 (0bxxxx,xxxx,0000,0000,xxxx,xxxx,0000,0000)

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Bit Reset Description

23:16 0x0

HI_DST_PTR

7:0 0x0

HI_SRC_PTR

GPCDMA_CHANNEL_CH10_MC_SEQ_0

Offset: 0xb0018

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH10_0

Reset: 0x03800000 (0b0000,0011,1000,0000,0000,0000,0000,0000)

Bit Reset Description

31 0x0

MC_DATA_SWAP:

= DISABLE0

= ENABLE1

30:25 0x1

MC_REQ_CNT

24:23 0x3

MC_BURST:

= DMA_BURST_2WORDS0

= DMA_BURST_16WORDS3

22:20 0x0

MC_ADDR_WRAP1:

= NO_WRAP0

= WRAP_0N_32WORDS1

= WRAP_ON_64WORDS2

= WRAP_ON_128WORDS3

= WRAP_ON_256WORDS4

= WRAP_ON_512WORDS5

= WRAP_ON_1024WORDS6

= WRAP_ON_2048WORDS7

19:17 0x0

MC_ADDR_WRAP0:

= NO_WRAP0

= WRAP_0N_32WORDS1

= WRAP_ON_64WORDS2

= WRAP_ON_128WORDS3

= WRAP_ON_256WORDS4

= WRAP_ON_512WORDS5

= WRAP_ON_1024WORDS6

= WRAP_ON_2048WORDS7

16 0x0

MC_AXIID

15:14 0x0

MC_PROT

13:7 0x0

STREAMID1

6:0 0x0

STREAMID0

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GPCDMA_CHANNEL_CH10_MMIO_SEQ_0

Offset: 0xb001c

Read/Write: See table below

Parity Protection: N

SCR Protection: SCR_CH10_0

Reset: 0x2381007f (0b0010,0011,1000,0001,xxxx,xxx0,0111,1111)

Bit R/W Reset Description

31 RW 0x0

DBL_BUF:

= DISABLE0

= ENABLE1

30:28 RW 0x2

MMIO_BUS_WIDTH:

= BUS_WIDTH_80

= BUS_WIDTH_161

= BUS_WIDTH_322

27 RW 0x0

MMIO_DATA_SWAP:

= DISABLE0

= ENABLE1

26:23 RW 0x7

MMIO_BURST:

= DMA_BURST_1WORDS0

= DMA_BURST_2WORDS1

= DMA_BURST_4WORDS3

= DMA_BURST_8WORDS7

= DMA_BURST_16WORDS15

22:19 RO 0x0

MMIO_MASTER_ID:

= RSVD0

= CCPLEX1

= CCPLEX_DPMU2

= BPMP3

= SPE4

= SCE5

= DMA_PER6

= TSECA7

= TSECB8

= JTAGM9

= CSITE10

= APE11

18:16 RW 0x1

MMIO_ADDR_WRAP:

= NO_WRAP0

= WRAP_0N_1WORDS1

= WRAP_ON_2WORDS2

= WRAP_ON_4WORDS3

= WRAP_ON_8WORDS4

= WRAP_ON_16WORDS5

= WRAP_ON_32WORDS6

= WRAP_ON_64WORDS7

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Bit R/W Reset Description

8:7 RW 0x0

MMIO_PROT

6:0 RO 0x7f

MMIO_CHANNEL_SECURITY

GPCDMA_CHANNEL_CH10_BCOUNT_0

Offset: 0xb0020

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH10_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

BCOUNT

GPCDMA_CHANNEL_CH10_DMA_BYTE_TRA_0

Offset: 0xb0024

Read/Write: RO

Parity Protection: N

SCR Protection: SCR_CH10_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

TRANSFER_COUNT

GPCDMA_CHANNEL_CH10_DMA_BYTE_STA_0

Offset: 0xb0028

Read/Write: RO

Parity Protection: N

SCR Protection: SCR_CH10_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

DMA_COUNT

GPCDMA_CHANNEL_CH10_ERR_STA_0

Offset: 0xb0030

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH10_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

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Bit Reset Description

31:0 0x0

ERROR_STATUS

GPCDMA_CHANNEL_CH10_FIXED_PAT_0

Offset: 0xb0034

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH10_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

FIXED_PATTERN

GPCDMA_CHANNEL_CH10_TZ_0

Offset: 0xb0038

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_TZ_0

Reset: 0x00000003 (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xx11)

Bit Reset Description

1 0x1

MC_PROT_1

0 0x1

MMIO_PROT_1

GPCDMA_CHANNEL_CH11_CSR_0

Offset: 0xc0000

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH11_0

Reset: 0x08008400 (0b00xx,1x00,0000,0000,1x00,01xx,xxxx,xxxx)

Bit Reset Description

31 0x0

ENB:

= DISABLE0

= ENABLE1

30 0x0

IE_EOC:

= DISABLE0

= ENABLE1

27 0x1

ONCE:

= CYCLIC_MODE0

= SINGLE_BLOCK1

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Bit Reset Description

25:24 0x0

FC_MODE:

= NO_MMIO0

= ONE_MMIO1

= TWO_MMIO2

= FOUR_MMIO3

23:21 0x0

DMA_MODE:

= IO2MEM_NO_FC0

= IO2MEM_FC1

= MEM2IO_NO_FC2

= MEM2IO_FC3

= MEM2MEM4

= RSVD5

= FIXED_PAT6

20:16 0x0

REQ_SEL:

= I2C80

= I2C101

= UARTG2

= UARTC3

= QSPI05

= QSPI16

= UARTA8

= UARTB9

= UARTF12

= UARTH13

= SPI115

= SPI216

= SPI317

= UARTD19

= UARTE20

= I2C21

= I2C222

= I2C323

= I2C524

= I2C426

= I2C727

= I2C630

= I2C931

= RSVD29

15 0x1

IRQ_MASK:

= DISABLE0

= ENABLE1

13:10 0x1

WEIGHT

GPCDMA_CHANNEL_CH11_STA_0

Offset: 0xc0004

Read/Write: See table below

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Parity Protection: N

SCR Protection: SCR_CH11_0

Reset: 0x00000000 (0b00x0,0000,0x00,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit R/W Reset Description

31 RO 0x0

BSY:

= WAIT0

= ACTIVE1

30 RW 0x0

ISE_EOC:

= NO_INTR0

= INTR1

28 RO 0x0

PING_PONG_STA:

= PING_INTR_STA0

= PONG_INTR_STA1

27 RO 0x0

DMA_ACTIVITY:

= IDLE0

= BUSY1

26 RO 0x0

CHANNEL_PAUSE:

= RESUME0

= PAUSE1

25 RO 0x0

CHANNEL_RX:

= NOT_ACTIVE0

= ACTIVE1

24 RO 0x0

CHANNEL_TX:

= NOT_ACTIVE0

= ACTIVE1

23 RO 0x0

IRQ_INTR_STA:

= DISABLE0

= ENABLE1

21 RO 0x0

TRIG_STA:

= NOT_ACTIVE0

= ACTIVE1

20 RO 0x0

INTR_STA:

= NOT_ACTIVE0

= ACTIVE1

GPCDMA_CHANNEL_CH11_CSRE_0

Offset: 0xc0008

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH11_0

Reset: 0x00000000 (0b0xxx,xxxx,xxxx,0000,00xx,xxxx,xxxx,xxxx)

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Bit Reset Description

31 0x0

DMA_ACTIVITY:

= RESUME0

= PAUSE1

19:14 0x0

TRIG_SEL:

= SMP_241

= SMP_252

= SMP_263

= SMP_274

= XRQ_A5

= XRQ_B6

= TMR17

= TMR28

= CH09

= CH110

= CH211

= CH312

= CH413

= CH514

= CH615

= CH716

= CH817

= CH918

= CH1019

= CH1120

= CH1221

= CH1322

= CH1423

= CH1524

= CH1625

= CH1726

= CH1827

= CH1928

= CH2029

= CH2130

= CH2231

= CH2332

= CH2433

= CH2534

= CH2635

= CH2736

= CH2837

= CH2938

= CH3039

= CH3140

= RSVD0

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GPCDMA_CHANNEL_CH11_SRC_PTR_0

Offset: 0xc000c

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH11_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

SRC_PTR

GPCDMA_CHANNEL_CH11_DST_PTR_0

Offset: 0xc0010

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH11_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

DST_PTR

GPCDMA_CHANNEL_CH11_HI_ADR_PTR_0

Offset: 0xc0014

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH11_0

Reset: 0x00000000 (0bxxxx,xxxx,0000,0000,xxxx,xxxx,0000,0000)

Bit Reset Description

23:16 0x0

HI_DST_PTR

7:0 0x0

HI_SRC_PTR

GPCDMA_CHANNEL_CH11_MC_SEQ_0

Offset: 0xc0018

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH11_0

Reset: 0x03800000 (0b0000,0011,1000,0000,0000,0000,0000,0000)

Bit Reset Description

31 0x0

MC_DATA_SWAP:

= DISABLE0

= ENABLE1

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Bit Reset Description

30:25 0x1

MC_REQ_CNT

24:23 0x3

MC_BURST:

= DMA_BURST_2WORDS0

= DMA_BURST_16WORDS3

22:20 0x0

MC_ADDR_WRAP1:

= NO_WRAP0

= WRAP_0N_32WORDS1

= WRAP_ON_64WORDS2

= WRAP_ON_128WORDS3

= WRAP_ON_256WORDS4

= WRAP_ON_512WORDS5

= WRAP_ON_1024WORDS6

= WRAP_ON_2048WORDS7

19:17 0x0

MC_ADDR_WRAP0:

= NO_WRAP0

= WRAP_0N_32WORDS1

= WRAP_ON_64WORDS2

= WRAP_ON_128WORDS3

= WRAP_ON_256WORDS4

= WRAP_ON_512WORDS5

= WRAP_ON_1024WORDS6

= WRAP_ON_2048WORDS7

16 0x0

MC_AXIID

15:14 0x0

MC_PROT

13:7 0x0

STREAMID1

6:0 0x0

STREAMID0

GPCDMA_CHANNEL_CH11_MMIO_SEQ_0

Offset: 0xc001c

Read/Write: See table below

Parity Protection: N

SCR Protection: SCR_CH11_0

Reset: 0x2381007f (0b0010,0011,1000,0001,xxxx,xxx0,0111,1111)

Bit R/W Reset Description

31 RW 0x0

DBL_BUF:

= DISABLE0

= ENABLE1

30:28 RW 0x2

MMIO_BUS_WIDTH:

= BUS_WIDTH_80

= BUS_WIDTH_161

= BUS_WIDTH_322

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Bit R/W Reset Description

27 RW 0x0

MMIO_DATA_SWAP:

= DISABLE0

= ENABLE1

26:23 RW 0x7

MMIO_BURST:

= DMA_BURST_1WORDS0

= DMA_BURST_2WORDS1

= DMA_BURST_4WORDS3

= DMA_BURST_8WORDS7

= DMA_BURST_16WORDS15

22:19 RO 0x0

MMIO_MASTER_ID:

= RSVD0

= CCPLEX1

= CCPLEX_DPMU2

= BPMP3

= SPE4

= SCE5

= DMA_PER6

= TSECA7

= TSECB8

= JTAGM9

= CSITE10

= APE11

18:16 RW 0x1

MMIO_ADDR_WRAP:

= NO_WRAP0

= WRAP_0N_1WORDS1

= WRAP_ON_2WORDS2

= WRAP_ON_4WORDS3

= WRAP_ON_8WORDS4

= WRAP_ON_16WORDS5

= WRAP_ON_32WORDS6

= WRAP_ON_64WORDS7

8:7 RW 0x0

MMIO_PROT

6:0 RO 0x7f

MMIO_CHANNEL_SECURITY

GPCDMA_CHANNEL_CH11_BCOUNT_0

Offset: 0xc0020

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH11_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

BCOUNT

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GPCDMA_CHANNEL_CH11_DMA_BYTE_TRA_0

Offset: 0xc0024

Read/Write: RO

Parity Protection: N

SCR Protection: SCR_CH11_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

TRANSFER_COUNT

GPCDMA_CHANNEL_CH11_DMA_BYTE_STA_0

Offset: 0xc0028

Read/Write: RO

Parity Protection: N

SCR Protection: SCR_CH11_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

DMA_COUNT

GPCDMA_CHANNEL_CH11_ERR_STA_0

Offset: 0xc0030

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH11_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

ERROR_STATUS

GPCDMA_CHANNEL_CH11_FIXED_PAT_0

Offset: 0xc0034

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH11_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

FIXED_PATTERN

GPCDMA_CHANNEL_CH11_TZ_0

Offset: 0xc0038

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Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_TZ_0

Reset: 0x00000003 (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xx11)

Bit Reset Description

1 0x1

MC_PROT_1

0 0x1

MMIO_PROT_1

GPCDMA_CHANNEL_CH12_CSR_0

Offset: 0xd0000

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH12_0

Reset: 0x08008400 (0b00xx,1x00,0000,0000,1x00,01xx,xxxx,xxxx)

Bit Reset Description

31 0x0

ENB:

= DISABLE0

= ENABLE1

30 0x0

IE_EOC:

= DISABLE0

= ENABLE1

27 0x1

ONCE:

= CYCLIC_MODE0

= SINGLE_BLOCK1

25:24 0x0

FC_MODE:

= NO_MMIO0

= ONE_MMIO1

= TWO_MMIO2

= FOUR_MMIO3

23:21 0x0

DMA_MODE:

= IO2MEM_NO_FC0

= IO2MEM_FC1

= MEM2IO_NO_FC2

= MEM2IO_FC3

= MEM2MEM4

= RSVD5

= FIXED_PAT6

20:16

0x0

REQ_SEL:

= I2C80

= I2C101

= UARTG2

= UARTC3

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Bit Reset Description

= QSPI05

= QSPI16

= UARTA8

= UARTB9

= UARTF12

= UARTH13

= SPI115

= SPI216

= SPI317

= UARTD19

= UARTE20

= I2C21

= I2C222

= I2C323

= I2C524

= I2C426

= I2C727

= I2C630

= I2C931

= RSVD29

15 0x1

IRQ_MASK:

= DISABLE0

= ENABLE1

13:10 0x1

WEIGHT

GPCDMA_CHANNEL_CH12_STA_0

Offset: 0xd0004

Read/Write: See table below

Parity Protection: N

SCR Protection: SCR_CH12_0

Reset: 0x00000000 (0b00x0,0000,0x00,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit R/W Reset Description

31 RO 0x0

BSY:

= WAIT0

= ACTIVE1

30 RW 0x0

ISE_EOC:

= NO_INTR0

= INTR1

28 RO 0x0

PING_PONG_STA:

= PING_INTR_STA0

= PONG_INTR_STA1

0x0

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Bit R/W Reset Description

DMA_ACTIVITY:

= IDLE0

= BUSY1

26 RO 0x0

CHANNEL_PAUSE:

= RESUME0

= PAUSE1

25 RO 0x0

CHANNEL_RX:

= NOT_ACTIVE0

= ACTIVE1

24 RO 0x0

CHANNEL_TX:

= NOT_ACTIVE0

= ACTIVE1

23 RO 0x0

IRQ_INTR_STA:

= DISABLE0

= ENABLE1

21 RO 0x0

TRIG_STA:

= NOT_ACTIVE0

= ACTIVE1

20 RO 0x0

INTR_STA:

= NOT_ACTIVE0

= ACTIVE1

GPCDMA_CHANNEL_CH12_CSRE_0

Offset: 0xd0008

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH12_0

Reset: 0x00000000 (0b0xxx,xxxx,xxxx,0000,00xx,xxxx,xxxx,xxxx)

Bit Reset Description

31 0x0

DMA_ACTIVITY:

= RESUME0

= PAUSE1

19:14

0x0

TRIG_SEL:

= SMP_241

= SMP_252

= SMP_263

= SMP_274

= XRQ_A5

= XRQ_B6

= TMR17

= TMR28

= CH09

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Bit Reset Description

= CH110

= CH211

= CH312

= CH413

= CH514

= CH615

= CH716

= CH817

= CH918

= CH1019

= CH1120

= CH1221

= CH1322

= CH1423

= CH1524

= CH1625

= CH1726

= CH1827

= CH1928

= CH2029

= CH2130

= CH2231

= CH2332

= CH2433

= CH2534

= CH2635

= CH2736

= CH2837

= CH2938

= CH3039

= CH3140

= RSVD0

GPCDMA_CHANNEL_CH12_SRC_PTR_0

Offset: 0xd000c

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH12_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

SRC_PTR

GPCDMA_CHANNEL_CH12_DST_PTR_0

Offset: 0xd0010

Read/Write: R/W

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Parity Protection: N

SCR Protection: SCR_CH12_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

DST_PTR

GPCDMA_CHANNEL_CH12_HI_ADR_PTR_0

Offset: 0xd0014

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH12_0

Reset: 0x00000000 (0bxxxx,xxxx,0000,0000,xxxx,xxxx,0000,0000)

Bit Reset Description

23:16 0x0

HI_DST_PTR

7:0 0x0

HI_SRC_PTR

GPCDMA_CHANNEL_CH12_MC_SEQ_0

Offset: 0xd0018

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH12_0

Reset: 0x03800000 (0b0000,0011,1000,0000,0000,0000,0000,0000)

Bit Reset Description

31 0x0

MC_DATA_SWAP:

= DISABLE0

= ENABLE1

30:25 0x1

MC_REQ_CNT

24:23 0x3

MC_BURST:

= DMA_BURST_2WORDS0

= DMA_BURST_16WORDS3

22:20 0x0

MC_ADDR_WRAP1:

= NO_WRAP0

= WRAP_0N_32WORDS1

= WRAP_ON_64WORDS2

= WRAP_ON_128WORDS3

= WRAP_ON_256WORDS4

= WRAP_ON_512WORDS5

= WRAP_ON_1024WORDS6

= WRAP_ON_2048WORDS7

19:17

0x0

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Bit Reset Description

MC_ADDR_WRAP0:

= NO_WRAP0

= WRAP_0N_32WORDS1

= WRAP_ON_64WORDS2

= WRAP_ON_128WORDS3

= WRAP_ON_256WORDS4

= WRAP_ON_512WORDS5

= WRAP_ON_1024WORDS6

= WRAP_ON_2048WORDS7

16 0x0

MC_AXIID

15:14 0x0

MC_PROT

13:7 0x0

STREAMID1

6:0 0x0

STREAMID0

GPCDMA_CHANNEL_CH12_MMIO_SEQ_0

Offset: 0xd001c

Read/Write: See table below

Parity Protection: N

SCR Protection: SCR_CH12_0

Reset: 0x2381007f (0b0010,0011,1000,0001,xxxx,xxx0,0111,1111)

Bit R/W Reset Description

31 RW 0x0

DBL_BUF:

= DISABLE0

= ENABLE1

30:28 RW 0x2

MMIO_BUS_WIDTH:

= BUS_WIDTH_80

= BUS_WIDTH_161

= BUS_WIDTH_322

27 RW 0x0

MMIO_DATA_SWAP:

= DISABLE0

= ENABLE1

26:23 RW 0x7

MMIO_BURST:

= DMA_BURST_1WORDS0

= DMA_BURST_2WORDS1

= DMA_BURST_4WORDS3

= DMA_BURST_8WORDS7

= DMA_BURST_16WORDS15

22:19

0x0

MMIO_MASTER_ID:

= RSVD0

= CCPLEX1

= CCPLEX_DPMU2

= BPMP3

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Bit R/W Reset Description

= SPE4

= SCE5

= DMA_PER6

= TSECA7

= TSECB8

= JTAGM9

= CSITE10

= APE11

18:16 RW 0x1

MMIO_ADDR_WRAP:

= NO_WRAP0

= WRAP_0N_1WORDS1

= WRAP_ON_2WORDS2

= WRAP_ON_4WORDS3

= WRAP_ON_8WORDS4

= WRAP_ON_16WORDS5

= WRAP_ON_32WORDS6

= WRAP_ON_64WORDS7

8:7 RW 0x0

MMIO_PROT

6:0 RO 0x7f

MMIO_CHANNEL_SECURITY

GPCDMA_CHANNEL_CH12_BCOUNT_0

Offset: 0xd0020

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH12_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

BCOUNT

GPCDMA_CHANNEL_CH12_DMA_BYTE_TRA_0

Offset: 0xd0024

Read/Write: RO

Parity Protection: N

SCR Protection: SCR_CH12_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

TRANSFER_COUNT

GPCDMA_CHANNEL_CH12_DMA_BYTE_STA_0

Offset: 0xd0028

Read/Write: RO

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Parity Protection: N

SCR Protection: SCR_CH12_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

DMA_COUNT

GPCDMA_CHANNEL_CH12_ERR_STA_0

Offset: 0xd0030

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH12_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

ERROR_STATUS

GPCDMA_CHANNEL_CH12_FIXED_PAT_0

Offset: 0xd0034

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH12_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

FIXED_PATTERN

GPCDMA_CHANNEL_CH12_TZ_0

Offset: 0xd0038

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_TZ_0

Reset: 0x00000003 (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xx11)

Bit Reset Description

1 0x1

MC_PROT_1

0 0x1

MMIO_PROT_1

GPCDMA_CHANNEL_CH13_CSR_0

Offset: 0xe0000

Read/Write: R/W

Parity Protection: N

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SCR Protection: SCR_CH13_0

Reset: 0x08008400 (0b00xx,1x00,0000,0000,1x00,01xx,xxxx,xxxx)

Bit Reset Description

31 0x0

ENB:

= DISABLE0

= ENABLE1

30 0x0

IE_EOC:

= DISABLE0

= ENABLE1

27 0x1

ONCE:

= CYCLIC_MODE0

= SINGLE_BLOCK1

25:24 0x0

FC_MODE:

= NO_MMIO0

= ONE_MMIO1

= TWO_MMIO2

= FOUR_MMIO3

23:21 0x0

DMA_MODE:

= IO2MEM_NO_FC0

= IO2MEM_FC1

= MEM2IO_NO_FC2

= MEM2IO_FC3

= MEM2MEM4

= RSVD5

= FIXED_PAT6

20:16

0x0

REQ_SEL:

= I2C80

= I2C101

= UARTG2

= UARTC3

= QSPI05

= QSPI16

= UARTA8

= UARTB9

= UARTF12

= UARTH13

= SPI115

= SPI216

= SPI317

= UARTD19

= UARTE20

= I2C21

= I2C222

= I2C323

= I2C524

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Bit Reset Description

= I2C426

= I2C727

= I2C630

= I2C931

= RSVD29

15 0x1

IRQ_MASK:

= DISABLE0

= ENABLE1

13:10 0x1

WEIGHT

GPCDMA_CHANNEL_CH13_STA_0

Offset: 0xe0004

Read/Write: See table below

Parity Protection: N

SCR Protection: SCR_CH13_0

Reset: 0x00000000 (0b00x0,0000,0x00,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit R/W Reset Description

31 RO 0x0

BSY:

= WAIT0

= ACTIVE1

30 RW 0x0

ISE_EOC:

= NO_INTR0

= INTR1

28 RO 0x0

PING_PONG_STA:

= PING_INTR_STA0

= PONG_INTR_STA1

27 RO 0x0

DMA_ACTIVITY:

= IDLE0

= BUSY1

26 RO 0x0

CHANNEL_PAUSE:

= RESUME0

= PAUSE1

25 RO 0x0

CHANNEL_RX:

= NOT_ACTIVE0

= ACTIVE1

24 RO 0x0

CHANNEL_TX:

= NOT_ACTIVE0

= ACTIVE1

23 RO 0x0

IRQ_INTR_STA:

= DISABLE0

= ENABLE1

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Bit R/W Reset Description

21 RO 0x0

TRIG_STA:

= NOT_ACTIVE0

= ACTIVE1

20 RO 0x0

INTR_STA:

= NOT_ACTIVE0

= ACTIVE1

GPCDMA_CHANNEL_CH13_CSRE_0

Offset: 0xe0008

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH13_0

Reset: 0x00000000 (0b0xxx,xxxx,xxxx,0000,00xx,xxxx,xxxx,xxxx)

Bit Reset Description

31 0x0

DMA_ACTIVITY:

= RESUME0

= PAUSE1

19:14

0x0

TRIG_SEL:

= SMP_241

= SMP_252

= SMP_263

= SMP_274

= XRQ_A5

= XRQ_B6

= TMR17

= TMR28

= CH09

= CH110

= CH211

= CH312

= CH413

= CH514

= CH615

= CH716

= CH817

= CH918

= CH1019

= CH1120

= CH1221

= CH1322

= CH1423

= CH1524

= CH1625

= CH1726

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Bit Reset Description

= CH1827

= CH1928

= CH2029

= CH2130

= CH2231

= CH2332

= CH2433

= CH2534

= CH2635

= CH2736

= CH2837

= CH2938

= CH3039

= CH3140

= RSVD0

GPCDMA_CHANNEL_CH13_SRC_PTR_0

Offset: 0xe000c

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH13_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

SRC_PTR

GPCDMA_CHANNEL_CH13_DST_PTR_0

Offset: 0xe0010

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH13_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

DST_PTR

GPCDMA_CHANNEL_CH13_HI_ADR_PTR_0

Offset: 0xe0014

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH13_0

Reset: 0x00000000 (0bxxxx,xxxx,0000,0000,xxxx,xxxx,0000,0000)

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Bit Reset Description

23:16 0x0

HI_DST_PTR

7:0 0x0

HI_SRC_PTR

GPCDMA_CHANNEL_CH13_MC_SEQ_0

Offset: 0xe0018

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH13_0

Reset: 0x03800000 (0b0000,0011,1000,0000,0000,0000,0000,0000)

Bit Reset Description

31 0x0

MC_DATA_SWAP:

= DISABLE0

= ENABLE1

30:25 0x1

MC_REQ_CNT

24:23 0x3

MC_BURST:

= DMA_BURST_2WORDS0

= DMA_BURST_16WORDS3

22:20 0x0

MC_ADDR_WRAP1:

= NO_WRAP0

= WRAP_0N_32WORDS1

= WRAP_ON_64WORDS2

= WRAP_ON_128WORDS3

= WRAP_ON_256WORDS4

= WRAP_ON_512WORDS5

= WRAP_ON_1024WORDS6

= WRAP_ON_2048WORDS7

19:17 0x0

MC_ADDR_WRAP0:

= NO_WRAP0

= WRAP_0N_32WORDS1

= WRAP_ON_64WORDS2

= WRAP_ON_128WORDS3

= WRAP_ON_256WORDS4

= WRAP_ON_512WORDS5

= WRAP_ON_1024WORDS6

= WRAP_ON_2048WORDS7

16 0x0

MC_AXIID

15:14 0x0

MC_PROT

13:7 0x0

STREAMID1

6:0 0x0

STREAMID0

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GPCDMA_CHANNEL_CH13_MMIO_SEQ_0

Offset: 0xe001c

Read/Write: See table below

Parity Protection: N

SCR Protection: SCR_CH13_0

Reset: 0x2381007f (0b0010,0011,1000,0001,xxxx,xxx0,0111,1111)

Bit R/W Reset Description

31 RW 0x0

DBL_BUF:

= DISABLE0

= ENABLE1

30:28 RW 0x2

MMIO_BUS_WIDTH:

= BUS_WIDTH_80

= BUS_WIDTH_161

= BUS_WIDTH_322

27 RW 0x0

MMIO_DATA_SWAP:

= DISABLE0

= ENABLE1

26:23 RW 0x7

MMIO_BURST:

= DMA_BURST_1WORDS0

= DMA_BURST_2WORDS1

= DMA_BURST_4WORDS3

= DMA_BURST_8WORDS7

= DMA_BURST_16WORDS15

22:19 RO 0x0

MMIO_MASTER_ID:

= RSVD0

= CCPLEX1

= CCPLEX_DPMU2

= BPMP3

= SPE4

= SCE5

= DMA_PER6

= TSECA7

= TSECB8

= JTAGM9

= CSITE10

= APE11

18:16 RW 0x1

MMIO_ADDR_WRAP:

= NO_WRAP0

= WRAP_0N_1WORDS1

= WRAP_ON_2WORDS2

= WRAP_ON_4WORDS3

= WRAP_ON_8WORDS4

= WRAP_ON_16WORDS5

= WRAP_ON_32WORDS6

= WRAP_ON_64WORDS7

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Bit R/W Reset Description

8:7 RW 0x0

MMIO_PROT

6:0 RO 0x7f

MMIO_CHANNEL_SECURITY

GPCDMA_CHANNEL_CH13_BCOUNT_0

Offset: 0xe0020

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH13_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

BCOUNT

GPCDMA_CHANNEL_CH13_DMA_BYTE_TRA_0

Offset: 0xe0024

Read/Write: RO

Parity Protection: N

SCR Protection: SCR_CH13_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

TRANSFER_COUNT

GPCDMA_CHANNEL_CH13_DMA_BYTE_STA_0

Offset: 0xe0028

Read/Write: RO

Parity Protection: N

SCR Protection: SCR_CH13_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

DMA_COUNT

GPCDMA_CHANNEL_CH13_ERR_STA_0

Offset: 0xe0030

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH13_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

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Bit Reset Description

31:0 0x0

ERROR_STATUS

GPCDMA_CHANNEL_CH13_FIXED_PAT_0

Offset: 0xe0034

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH13_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

FIXED_PATTERN

GPCDMA_CHANNEL_CH13_TZ_0

Offset: 0xe0038

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_TZ_0

Reset: 0x00000003 (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xx11)

Bit Reset Description

1 0x1

MC_PROT_1

0 0x1

MMIO_PROT_1

GPCDMA_CHANNEL_CH14_CSR_0

Offset: 0xf0000

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH14_0

Reset: 0x08008400 (0b00xx,1x00,0000,0000,1x00,01xx,xxxx,xxxx)

Bit Reset Description

31 0x0

ENB:

= DISABLE0

= ENABLE1

30 0x0

IE_EOC:

= DISABLE0

= ENABLE1

27 0x1

ONCE:

= CYCLIC_MODE0

= SINGLE_BLOCK1

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Bit Reset Description

25:24 0x0

FC_MODE:

= NO_MMIO0

= ONE_MMIO1

= TWO_MMIO2

= FOUR_MMIO3

23:21 0x0

DMA_MODE:

= IO2MEM_NO_FC0

= IO2MEM_FC1

= MEM2IO_NO_FC2

= MEM2IO_FC3

= MEM2MEM4

= RSVD5

= FIXED_PAT6

20:16 0x0

REQ_SEL:

= I2C80

= I2C101

= UARTG2

= UARTC3

= QSPI05

= QSPI16

= UARTA8

= UARTB9

= UARTF12

= UARTH13

= SPI115

= SPI216

= SPI317

= UARTD19

= UARTE20

= I2C21

= I2C222

= I2C323

= I2C524

= I2C426

= I2C727

= I2C630

= I2C931

= RSVD29

15 0x1

IRQ_MASK:

= DISABLE0

= ENABLE1

13:10 0x1

WEIGHT

GPCDMA_CHANNEL_CH14_STA_0

Offset: 0xf0004

Read/Write: See table below

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Parity Protection: N

SCR Protection: SCR_CH14_0

Reset: 0x00000000 (0b00x0,0000,0x00,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit R/W Reset Description

31 RO 0x0

BSY:

= WAIT0

= ACTIVE1

30 RW 0x0

ISE_EOC:

= NO_INTR0

= INTR1

28 RO 0x0

PING_PONG_STA:

= PING_INTR_STA0

= PONG_INTR_STA1

27 RO 0x0

DMA_ACTIVITY:

= IDLE0

= BUSY1

26 RO 0x0

CHANNEL_PAUSE:

= RESUME0

= PAUSE1

25 RO 0x0

CHANNEL_RX:

= NOT_ACTIVE0

= ACTIVE1

24 RO 0x0

CHANNEL_TX:

= NOT_ACTIVE0

= ACTIVE1

23 RO 0x0

IRQ_INTR_STA:

= DISABLE0

= ENABLE1

21 RO 0x0

TRIG_STA:

= NOT_ACTIVE0

= ACTIVE1

20 RO 0x0

INTR_STA:

= NOT_ACTIVE0

= ACTIVE1

GPCDMA_CHANNEL_CH14_CSRE_0

Offset: 0xf0008

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH14_0

Reset: 0x00000000 (0b0xxx,xxxx,xxxx,0000,00xx,xxxx,xxxx,xxxx)

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Bit Reset Description

31 0x0

DMA_ACTIVITY:

= RESUME0

= PAUSE1

19:14 0x0

TRIG_SEL:

= SMP_241

= SMP_252

= SMP_263

= SMP_274

= XRQ_A5

= XRQ_B6

= TMR17

= TMR28

= CH09

= CH110

= CH211

= CH312

= CH413

= CH514

= CH615

= CH716

= CH817

= CH918

= CH1019

= CH1120

= CH1221

= CH1322

= CH1423

= CH1524

= CH1625

= CH1726

= CH1827

= CH1928

= CH2029

= CH2130

= CH2231

= CH2332

= CH2433

= CH2534

= CH2635

= CH2736

= CH2837

= CH2938

= CH3039

= CH3140

= RSVD0

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GPCDMA_CHANNEL_CH14_SRC_PTR_0

Offset: 0xf000c

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH14_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

SRC_PTR

GPCDMA_CHANNEL_CH14_DST_PTR_0

Offset: 0xf0010

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH14_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

DST_PTR

GPCDMA_CHANNEL_CH14_HI_ADR_PTR_0

Offset: 0xf0014

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH14_0

Reset: 0x00000000 (0bxxxx,xxxx,0000,0000,xxxx,xxxx,0000,0000)

Bit Reset Description

23:16 0x0

HI_DST_PTR

7:0 0x0

HI_SRC_PTR

GPCDMA_CHANNEL_CH14_MC_SEQ_0

Offset: 0xf0018

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH14_0

Reset: 0x03800000 (0b0000,0011,1000,0000,0000,0000,0000,0000)

Bit Reset Description

31 0x0

MC_DATA_SWAP:

= DISABLE0

= ENABLE1

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Bit Reset Description

30:25 0x1

MC_REQ_CNT

24:23 0x3

MC_BURST:

= DMA_BURST_2WORDS0

= DMA_BURST_16WORDS3

22:20 0x0

MC_ADDR_WRAP1:

= NO_WRAP0

= WRAP_0N_32WORDS1

= WRAP_ON_64WORDS2

= WRAP_ON_128WORDS3

= WRAP_ON_256WORDS4

= WRAP_ON_512WORDS5

= WRAP_ON_1024WORDS6

= WRAP_ON_2048WORDS7

19:17 0x0

MC_ADDR_WRAP0:

= NO_WRAP0

= WRAP_0N_32WORDS1

= WRAP_ON_64WORDS2

= WRAP_ON_128WORDS3

= WRAP_ON_256WORDS4

= WRAP_ON_512WORDS5

= WRAP_ON_1024WORDS6

= WRAP_ON_2048WORDS7

16 0x0

MC_AXIID

15:14 0x0

MC_PROT

13:7 0x0

STREAMID1

6:0 0x0

STREAMID0

GPCDMA_CHANNEL_CH14_MMIO_SEQ_0

Offset: 0xf001c

Read/Write: See table below

Parity Protection: N

SCR Protection: SCR_CH14_0

Reset: 0x2381007f (0b0010,0011,1000,0001,xxxx,xxx0,0111,1111)

Bit R/W Reset Description

31 RW 0x0

DBL_BUF:

= DISABLE0

= ENABLE1

30:28 RW 0x2

MMIO_BUS_WIDTH:

= BUS_WIDTH_80

= BUS_WIDTH_161

= BUS_WIDTH_322

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Bit R/W Reset Description

27 RW 0x0

MMIO_DATA_SWAP:

= DISABLE0

= ENABLE1

26:23 RW 0x7

MMIO_BURST:

= DMA_BURST_1WORDS0

= DMA_BURST_2WORDS1

= DMA_BURST_4WORDS3

= DMA_BURST_8WORDS7

= DMA_BURST_16WORDS15

22:19 RO 0x0

MMIO_MASTER_ID:

= RSVD0

= CCPLEX1

= CCPLEX_DPMU2

= BPMP3

= SPE4

= SCE5

= DMA_PER6

= TSECA7

= TSECB8

= JTAGM9

= CSITE10

= APE11

18:16 RW 0x1

MMIO_ADDR_WRAP:

= NO_WRAP0

= WRAP_0N_1WORDS1

= WRAP_ON_2WORDS2

= WRAP_ON_4WORDS3

= WRAP_ON_8WORDS4

= WRAP_ON_16WORDS5

= WRAP_ON_32WORDS6

= WRAP_ON_64WORDS7

8:7 RW 0x0

MMIO_PROT

6:0 RO 0x7f

MMIO_CHANNEL_SECURITY

GPCDMA_CHANNEL_CH14_BCOUNT_0

Offset: 0xf0020

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH14_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

BCOUNT

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GPCDMA_CHANNEL_CH14_DMA_BYTE_TRA_0

Offset: 0xf0024

Read/Write: RO

Parity Protection: N

SCR Protection: SCR_CH14_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

TRANSFER_COUNT

GPCDMA_CHANNEL_CH14_DMA_BYTE_STA_0

Offset: 0xf0028

Read/Write: RO

Parity Protection: N

SCR Protection: SCR_CH14_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

DMA_COUNT

GPCDMA_CHANNEL_CH14_ERR_STA_0

Offset: 0xf0030

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH14_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

ERROR_STATUS

GPCDMA_CHANNEL_CH14_FIXED_PAT_0

Offset: 0xf0034

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH14_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

FIXED_PATTERN

GPCDMA_CHANNEL_CH14_TZ_0

Offset: 0xf0038

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Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_TZ_0

Reset: 0x00000003 (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xx11)

Bit Reset Description

1 0x1

MC_PROT_1

0 0x1

MMIO_PROT_1

GPCDMA_CHANNEL_CH15_CSR_0

Offset: 0x100000

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH15_0

Reset: 0x08008400 (0b00xx,1x00,0000,0000,1x00,01xx,xxxx,xxxx)

Bit Reset Description

31 0x0

ENB:

= DISABLE0

= ENABLE1

30 0x0

IE_EOC:

= DISABLE0

= ENABLE1

27 0x1

ONCE:

= CYCLIC_MODE0

= SINGLE_BLOCK1

25:24 0x0

FC_MODE:

= NO_MMIO0

= ONE_MMIO1

= TWO_MMIO2

= FOUR_MMIO3

23:21 0x0

DMA_MODE:

= IO2MEM_NO_FC0

= IO2MEM_FC1

= MEM2IO_NO_FC2

= MEM2IO_FC3

= MEM2MEM4

= RSVD5

= FIXED_PAT6

20:16

0x0

REQ_SEL:

= I2C80

= I2C101

= UARTG2

= UARTC3

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Bit Reset Description

= QSPI05

= QSPI16

= UARTA8

= UARTB9

= UARTF12

= UARTH13

= SPI115

= SPI216

= SPI317

= UARTD19

= UARTE20

= I2C21

= I2C222

= I2C323

= I2C524

= I2C426

= I2C727

= I2C630

= I2C931

= RSVD29

15 0x1

IRQ_MASK:

= DISABLE0

= ENABLE1

13:10 0x1

WEIGHT

GPCDMA_CHANNEL_CH15_STA_0

Offset: 0x100004

Read/Write: See table below

Parity Protection: N

SCR Protection: SCR_CH15_0

Reset: 0x00000000 (0b00x0,0000,0x00,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit R/W Reset Description

31 RO 0x0

BSY:

= WAIT0

= ACTIVE1

30 RW 0x0

ISE_EOC:

= NO_INTR0

= INTR1

28 RO 0x0

PING_PONG_STA:

= PING_INTR_STA0

= PONG_INTR_STA1

0x0

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Bit R/W Reset Description

DMA_ACTIVITY:

= IDLE0

= BUSY1

26 RO 0x0

CHANNEL_PAUSE:

= RESUME0

= PAUSE1

25 RO 0x0

CHANNEL_RX:

= NOT_ACTIVE0

= ACTIVE1

24 RO 0x0

CHANNEL_TX:

= NOT_ACTIVE0

= ACTIVE1

23 RO 0x0

IRQ_INTR_STA:

= DISABLE0

= ENABLE1

21 RO 0x0

TRIG_STA:

= NOT_ACTIVE0

= ACTIVE1

20 RO 0x0

INTR_STA:

= NOT_ACTIVE0

= ACTIVE1

GPCDMA_CHANNEL_CH15_CSRE_0

Offset: 0x100008

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH15_0

Reset: 0x00000000 (0b0xxx,xxxx,xxxx,0000,00xx,xxxx,xxxx,xxxx)

Bit Reset Description

31 0x0

DMA_ACTIVITY:

= RESUME0

= PAUSE1

19:14

0x0

TRIG_SEL:

= SMP_241

= SMP_252

= SMP_263

= SMP_274

= XRQ_A5

= XRQ_B6

= TMR17

= TMR28

= CH09

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Bit Reset Description

= CH110

= CH211

= CH312

= CH413

= CH514

= CH615

= CH716

= CH817

= CH918

= CH1019

= CH1120

= CH1221

= CH1322

= CH1423

= CH1524

= CH1625

= CH1726

= CH1827

= CH1928

= CH2029

= CH2130

= CH2231

= CH2332

= CH2433

= CH2534

= CH2635

= CH2736

= CH2837

= CH2938

= CH3039

= CH3140

= RSVD0

GPCDMA_CHANNEL_CH15_SRC_PTR_0

Offset: 0x10000c

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH15_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

SRC_PTR

GPCDMA_CHANNEL_CH15_DST_PTR_0

Offset: 0x100010

Read/Write: R/W

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Parity Protection: N

SCR Protection: SCR_CH15_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

DST_PTR

GPCDMA_CHANNEL_CH15_HI_ADR_PTR_0

Offset: 0x100014

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH15_0

Reset: 0x00000000 (0bxxxx,xxxx,0000,0000,xxxx,xxxx,0000,0000)

Bit Reset Description

23:16 0x0

HI_DST_PTR

7:0 0x0

HI_SRC_PTR

GPCDMA_CHANNEL_CH15_MC_SEQ_0

Offset: 0x100018

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH15_0

Reset: 0x03800000 (0b0000,0011,1000,0000,0000,0000,0000,0000)

Bit Reset Description

31 0x0

MC_DATA_SWAP:

= DISABLE0

= ENABLE1

30:25 0x1

MC_REQ_CNT

24:23 0x3

MC_BURST:

= DMA_BURST_2WORDS0

= DMA_BURST_16WORDS3

22:20 0x0

MC_ADDR_WRAP1:

= NO_WRAP0

= WRAP_0N_32WORDS1

= WRAP_ON_64WORDS2

= WRAP_ON_128WORDS3

= WRAP_ON_256WORDS4

= WRAP_ON_512WORDS5

= WRAP_ON_1024WORDS6

= WRAP_ON_2048WORDS7

19:17

0x0

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Bit Reset Description

MC_ADDR_WRAP0:

= NO_WRAP0

= WRAP_0N_32WORDS1

= WRAP_ON_64WORDS2

= WRAP_ON_128WORDS3

= WRAP_ON_256WORDS4

= WRAP_ON_512WORDS5

= WRAP_ON_1024WORDS6

= WRAP_ON_2048WORDS7

16 0x0

MC_AXIID

15:14 0x0

MC_PROT

13:7 0x0

STREAMID1

6:0 0x0

STREAMID0

GPCDMA_CHANNEL_CH15_MMIO_SEQ_0

Offset: 0x10001c

Read/Write: See table below

Parity Protection: N

SCR Protection: SCR_CH15_0

Reset: 0x2381007f (0b0010,0011,1000,0001,xxxx,xxx0,0111,1111)

Bit R/W Reset Description

31 RW 0x0

DBL_BUF:

= DISABLE0

= ENABLE1

30:28 RW 0x2

MMIO_BUS_WIDTH:

= BUS_WIDTH_80

= BUS_WIDTH_161

= BUS_WIDTH_322

27 RW 0x0

MMIO_DATA_SWAP:

= DISABLE0

= ENABLE1

26:23 RW 0x7

MMIO_BURST:

= DMA_BURST_1WORDS0

= DMA_BURST_2WORDS1

= DMA_BURST_4WORDS3

= DMA_BURST_8WORDS7

= DMA_BURST_16WORDS15

22:19

0x0

MMIO_MASTER_ID:

= RSVD0

= CCPLEX1

= CCPLEX_DPMU2

= BPMP3

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Bit R/W Reset Description

= SPE4

= SCE5

= DMA_PER6

= TSECA7

= TSECB8

= JTAGM9

= CSITE10

= APE11

18:16 RW 0x1

MMIO_ADDR_WRAP:

= NO_WRAP0

= WRAP_0N_1WORDS1

= WRAP_ON_2WORDS2

= WRAP_ON_4WORDS3

= WRAP_ON_8WORDS4

= WRAP_ON_16WORDS5

= WRAP_ON_32WORDS6

= WRAP_ON_64WORDS7

8:7 RW 0x0

MMIO_PROT

6:0 RO 0x7f

MMIO_CHANNEL_SECURITY

GPCDMA_CHANNEL_CH15_BCOUNT_0

Offset: 0x100020

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH15_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

BCOUNT

GPCDMA_CHANNEL_CH15_DMA_BYTE_TRA_0

Offset: 0x100024

Read/Write: RO

Parity Protection: N

SCR Protection: SCR_CH15_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

TRANSFER_COUNT

GPCDMA_CHANNEL_CH15_DMA_BYTE_STA_0

Offset: 0x100028

Read/Write: RO

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Parity Protection: N

SCR Protection: SCR_CH15_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

DMA_COUNT

GPCDMA_CHANNEL_CH15_ERR_STA_0

Offset: 0x100030

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH15_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

ERROR_STATUS

GPCDMA_CHANNEL_CH15_FIXED_PAT_0

Offset: 0x100034

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH15_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

FIXED_PATTERN

GPCDMA_CHANNEL_CH15_TZ_0

Offset: 0x100038

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_TZ_0

Reset: 0x00000003 (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xx11)

Bit Reset Description

1 0x1

MC_PROT_1

0 0x1

MMIO_PROT_1

GPCDMA_CHANNEL_CH16_CSR_0

Offset: 0x110000

Read/Write: R/W

Parity Protection: N

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SCR Protection: SCR_CH16_0

Reset: 0x08008400 (0b00xx,1x00,0000,0000,1x00,01xx,xxxx,xxxx)

Bit Reset Description

31 0x0

ENB:

= DISABLE0

= ENABLE1

30 0x0

IE_EOC:

= DISABLE0

= ENABLE1

27 0x1

ONCE:

= CYCLIC_MODE0

= SINGLE_BLOCK1

25:24 0x0

FC_MODE:

= NO_MMIO0

= ONE_MMIO1

= TWO_MMIO2

= FOUR_MMIO3

23:21 0x0

DMA_MODE:

= IO2MEM_NO_FC0

= IO2MEM_FC1

= MEM2IO_NO_FC2

= MEM2IO_FC3

= MEM2MEM4

= RSVD5

= FIXED_PAT6

20:16

0x0

REQ_SEL:

= I2C80

= I2C101

= UARTG2

= UARTC3

= QSPI05

= QSPI16

= UARTA8

= UARTB9

= UARTF12

= UARTH13

= SPI115

= SPI216

= SPI317

= UARTD19

= UARTE20

= I2C21

= I2C222

= I2C323

= I2C524

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Bit Reset Description

= I2C426

= I2C727

= I2C630

= I2C931

= RSVD29

15 0x1

IRQ_MASK:

= DISABLE0

= ENABLE1

13:10 0x1

WEIGHT

GPCDMA_CHANNEL_CH16_STA_0

Offset: 0x110004

Read/Write: See table below

Parity Protection: N

SCR Protection: SCR_CH16_0

Reset: 0x00000000 (0b00x0,0000,0x00,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit R/W Reset Description

31 RO 0x0

BSY:

= WAIT0

= ACTIVE1

30 RW 0x0

ISE_EOC:

= NO_INTR0

= INTR1

28 RO 0x0

PING_PONG_STA:

= PING_INTR_STA0

= PONG_INTR_STA1

27 RO 0x0

DMA_ACTIVITY:

= IDLE0

= BUSY1

26 RO 0x0

CHANNEL_PAUSE:

= RESUME0

= PAUSE1

25 RO 0x0

CHANNEL_RX:

= NOT_ACTIVE0

= ACTIVE1

24 RO 0x0

CHANNEL_TX:

= NOT_ACTIVE0

= ACTIVE1

23 RO 0x0

IRQ_INTR_STA:

= DISABLE0

= ENABLE1

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Bit R/W Reset Description

21 RO 0x0

TRIG_STA:

= NOT_ACTIVE0

= ACTIVE1

20 RO 0x0

INTR_STA:

= NOT_ACTIVE0

= ACTIVE1

GPCDMA_CHANNEL_CH16_CSRE_0

Offset: 0x110008

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH16_0

Reset: 0x00000000 (0b0xxx,xxxx,xxxx,0000,00xx,xxxx,xxxx,xxxx)

Bit Reset Description

31 0x0

DMA_ACTIVITY:

= RESUME0

= PAUSE1

19:14

0x0

TRIG_SEL:

= SMP_241

= SMP_252

= SMP_263

= SMP_274

= XRQ_A5

= XRQ_B6

= TMR17

= TMR28

= CH09

= CH110

= CH211

= CH312

= CH413

= CH514

= CH615

= CH716

= CH817

= CH918

= CH1019

= CH1120

= CH1221

= CH1322

= CH1423

= CH1524

= CH1625

= CH1726

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Bit Reset Description

= CH1827

= CH1928

= CH2029

= CH2130

= CH2231

= CH2332

= CH2433

= CH2534

= CH2635

= CH2736

= CH2837

= CH2938

= CH3039

= CH3140

= RSVD0

GPCDMA_CHANNEL_CH16_SRC_PTR_0

Offset: 0x11000c

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH16_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

SRC_PTR

GPCDMA_CHANNEL_CH16_DST_PTR_0

Offset: 0x110010

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH16_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

DST_PTR

GPCDMA_CHANNEL_CH16_HI_ADR_PTR_0

Offset: 0x110014

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH16_0

Reset: 0x00000000 (0bxxxx,xxxx,0000,0000,xxxx,xxxx,0000,0000)

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Bit Reset Description

23:16 0x0

HI_DST_PTR

7:0 0x0

HI_SRC_PTR

GPCDMA_CHANNEL_CH16_MC_SEQ_0

Offset: 0x110018

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH16_0

Reset: 0x03800000 (0b0000,0011,1000,0000,0000,0000,0000,0000)

Bit Reset Description

31 0x0

MC_DATA_SWAP:

= DISABLE0

= ENABLE1

30:25 0x1

MC_REQ_CNT

24:23 0x3

MC_BURST:

= DMA_BURST_2WORDS0

= DMA_BURST_16WORDS3

22:20 0x0

MC_ADDR_WRAP1:

= NO_WRAP0

= WRAP_0N_32WORDS1

= WRAP_ON_64WORDS2

= WRAP_ON_128WORDS3

= WRAP_ON_256WORDS4

= WRAP_ON_512WORDS5

= WRAP_ON_1024WORDS6

= WRAP_ON_2048WORDS7

19:17 0x0

MC_ADDR_WRAP0:

= NO_WRAP0

= WRAP_0N_32WORDS1

= WRAP_ON_64WORDS2

= WRAP_ON_128WORDS3

= WRAP_ON_256WORDS4

= WRAP_ON_512WORDS5

= WRAP_ON_1024WORDS6

= WRAP_ON_2048WORDS7

16 0x0

MC_AXIID

15:14 0x0

MC_PROT

13:7 0x0

STREAMID1

6:0 0x0

STREAMID0

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GPCDMA_CHANNEL_CH16_MMIO_SEQ_0

Offset: 0x11001c

Read/Write: See table below

Parity Protection: N

SCR Protection: SCR_CH16_0

Reset: 0x2381007f (0b0010,0011,1000,0001,xxxx,xxx0,0111,1111)

Bit R/W Reset Description

31 RW 0x0

DBL_BUF:

= DISABLE0

= ENABLE1

30:28 RW 0x2

MMIO_BUS_WIDTH:

= BUS_WIDTH_80

= BUS_WIDTH_161

= BUS_WIDTH_322

27 RW 0x0

MMIO_DATA_SWAP:

= DISABLE0

= ENABLE1

26:23 RW 0x7

MMIO_BURST:

= DMA_BURST_1WORDS0

= DMA_BURST_2WORDS1

= DMA_BURST_4WORDS3

= DMA_BURST_8WORDS7

= DMA_BURST_16WORDS15

22:19 RO 0x0

MMIO_MASTER_ID:

= RSVD0

= CCPLEX1

= CCPLEX_DPMU2

= BPMP3

= SPE4

= SCE5

= DMA_PER6

= TSECA7

= TSECB8

= JTAGM9

= CSITE10

= APE11

18:16 RW 0x1

MMIO_ADDR_WRAP:

= NO_WRAP0

= WRAP_0N_1WORDS1

= WRAP_ON_2WORDS2

= WRAP_ON_4WORDS3

= WRAP_ON_8WORDS4

= WRAP_ON_16WORDS5

= WRAP_ON_32WORDS6

= WRAP_ON_64WORDS7

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Bit R/W Reset Description

8:7 RW 0x0

MMIO_PROT

6:0 RO 0x7f

MMIO_CHANNEL_SECURITY

GPCDMA_CHANNEL_CH16_BCOUNT_0

Offset: 0x110020

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH16_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

BCOUNT

GPCDMA_CHANNEL_CH16_DMA_BYTE_TRA_0

Offset: 0x110024

Read/Write: RO

Parity Protection: N

SCR Protection: SCR_CH16_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

TRANSFER_COUNT

GPCDMA_CHANNEL_CH16_DMA_BYTE_STA_0

Offset: 0x110028

Read/Write: RO

Parity Protection: N

SCR Protection: SCR_CH16_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

DMA_COUNT

GPCDMA_CHANNEL_CH16_ERR_STA_0

Offset: 0x110030

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH16_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

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Bit Reset Description

31:0 0x0

ERROR_STATUS

GPCDMA_CHANNEL_CH16_FIXED_PAT_0

Offset: 0x110034

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH16_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

FIXED_PATTERN

GPCDMA_CHANNEL_CH16_TZ_0

Offset: 0x110038

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_TZ_0

Reset: 0x00000003 (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xx11)

Bit Reset Description

1 0x1

MC_PROT_1

0 0x1

MMIO_PROT_1

GPCDMA_CHANNEL_CH17_CSR_0

Offset: 0x120000

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH17_0

Reset: 0x08008400 (0b00xx,1x00,0000,0000,1x00,01xx,xxxx,xxxx)

Bit Reset Description

31 0x0

ENB:

= DISABLE0

= ENABLE1

30 0x0

IE_EOC:

= DISABLE0

= ENABLE1

27 0x1

ONCE:

= CYCLIC_MODE0

= SINGLE_BLOCK1

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Bit Reset Description

25:24 0x0

FC_MODE:

= NO_MMIO0

= ONE_MMIO1

= TWO_MMIO2

= FOUR_MMIO3

23:21 0x0

DMA_MODE:

= IO2MEM_NO_FC0

= IO2MEM_FC1

= MEM2IO_NO_FC2

= MEM2IO_FC3

= MEM2MEM4

= RSVD5

= FIXED_PAT6

20:16 0x0

REQ_SEL:

= I2C80

= I2C101

= UARTG2

= UARTC3

= QSPI05

= QSPI16

= UARTA8

= UARTB9

= UARTF12

= UARTH13

= SPI115

= SPI216

= SPI317

= UARTD19

= UARTE20

= I2C21

= I2C222

= I2C323

= I2C524

= I2C426

= I2C727

= I2C630

= I2C931

= RSVD29

15 0x1

IRQ_MASK:

= DISABLE0

= ENABLE1

13:10 0x1

WEIGHT

GPCDMA_CHANNEL_CH17_STA_0

Offset: 0x120004

Read/Write: See table below

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Parity Protection: N

SCR Protection: SCR_CH17_0

Reset: 0x00000000 (0b00x0,0000,0x00,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit R/W Reset Description

31 RO 0x0

BSY:

= WAIT0

= ACTIVE1

30 RW 0x0

ISE_EOC:

= NO_INTR0

= INTR1

28 RO 0x0

PING_PONG_STA:

= PING_INTR_STA0

= PONG_INTR_STA1

27 RO 0x0

DMA_ACTIVITY:

= IDLE0

= BUSY1

26 RO 0x0

CHANNEL_PAUSE:

= RESUME0

= PAUSE1

25 RO 0x0

CHANNEL_RX:

= NOT_ACTIVE0

= ACTIVE1

24 RO 0x0

CHANNEL_TX:

= NOT_ACTIVE0

= ACTIVE1

23 RO 0x0

IRQ_INTR_STA:

= DISABLE0

= ENABLE1

21 RO 0x0

TRIG_STA:

= NOT_ACTIVE0

= ACTIVE1

20 RO 0x0

INTR_STA:

= NOT_ACTIVE0

= ACTIVE1

GPCDMA_CHANNEL_CH17_CSRE_0

Offset: 0x120008

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH17_0

Reset: 0x00000000 (0b0xxx,xxxx,xxxx,0000,00xx,xxxx,xxxx,xxxx)

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Bit Reset Description

31 0x0

DMA_ACTIVITY:

= RESUME0

= PAUSE1

19:14 0x0

TRIG_SEL:

= SMP_241

= SMP_252

= SMP_263

= SMP_274

= XRQ_A5

= XRQ_B6

= TMR17

= TMR28

= CH09

= CH110

= CH211

= CH312

= CH413

= CH514

= CH615

= CH716

= CH817

= CH918

= CH1019

= CH1120

= CH1221

= CH1322

= CH1423

= CH1524

= CH1625

= CH1726

= CH1827

= CH1928

= CH2029

= CH2130

= CH2231

= CH2332

= CH2433

= CH2534

= CH2635

= CH2736

= CH2837

= CH2938

= CH3039

= CH3140

= RSVD0

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GPCDMA_CHANNEL_CH17_SRC_PTR_0

Offset: 0x12000c

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH17_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

SRC_PTR

GPCDMA_CHANNEL_CH17_DST_PTR_0

Offset: 0x120010

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH17_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

DST_PTR

GPCDMA_CHANNEL_CH17_HI_ADR_PTR_0

Offset: 0x120014

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH17_0

Reset: 0x00000000 (0bxxxx,xxxx,0000,0000,xxxx,xxxx,0000,0000)

Bit Reset Description

23:16 0x0

HI_DST_PTR

7:0 0x0

HI_SRC_PTR

GPCDMA_CHANNEL_CH17_MC_SEQ_0

Offset: 0x120018

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH17_0

Reset: 0x03800000 (0b0000,0011,1000,0000,0000,0000,0000,0000)

Bit Reset Description

31 0x0

MC_DATA_SWAP:

= DISABLE0

= ENABLE1

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Bit Reset Description

30:25 0x1

MC_REQ_CNT

24:23 0x3

MC_BURST:

= DMA_BURST_2WORDS0

= DMA_BURST_16WORDS3

22:20 0x0

MC_ADDR_WRAP1:

= NO_WRAP0

= WRAP_0N_32WORDS1

= WRAP_ON_64WORDS2

= WRAP_ON_128WORDS3

= WRAP_ON_256WORDS4

= WRAP_ON_512WORDS5

= WRAP_ON_1024WORDS6

= WRAP_ON_2048WORDS7

19:17 0x0

MC_ADDR_WRAP0:

= NO_WRAP0

= WRAP_0N_32WORDS1

= WRAP_ON_64WORDS2

= WRAP_ON_128WORDS3

= WRAP_ON_256WORDS4

= WRAP_ON_512WORDS5

= WRAP_ON_1024WORDS6

= WRAP_ON_2048WORDS7

16 0x0

MC_AXIID

15:14 0x0

MC_PROT

13:7 0x0

STREAMID1

6:0 0x0

STREAMID0

GPCDMA_CHANNEL_CH17_MMIO_SEQ_0

Offset: 0x12001c

Read/Write: See table below

Parity Protection: N

SCR Protection: SCR_CH17_0

Reset: 0x2381007f (0b0010,0011,1000,0001,xxxx,xxx0,0111,1111)

Bit R/W Reset Description

31 RW 0x0

DBL_BUF:

= DISABLE0

= ENABLE1

30:28 RW 0x2

MMIO_BUS_WIDTH:

= BUS_WIDTH_80

= BUS_WIDTH_161

= BUS_WIDTH_322

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Bit R/W Reset Description

27 RW 0x0

MMIO_DATA_SWAP:

= DISABLE0

= ENABLE1

26:23 RW 0x7

MMIO_BURST:

= DMA_BURST_1WORDS0

= DMA_BURST_2WORDS1

= DMA_BURST_4WORDS3

= DMA_BURST_8WORDS7

= DMA_BURST_16WORDS15

22:19 RO 0x0

MMIO_MASTER_ID:

= RSVD0

= CCPLEX1

= CCPLEX_DPMU2

= BPMP3

= SPE4

= SCE5

= DMA_PER6

= TSECA7

= TSECB8

= JTAGM9

= CSITE10

= APE11

18:16 RW 0x1

MMIO_ADDR_WRAP:

= NO_WRAP0

= WRAP_0N_1WORDS1

= WRAP_ON_2WORDS2

= WRAP_ON_4WORDS3

= WRAP_ON_8WORDS4

= WRAP_ON_16WORDS5

= WRAP_ON_32WORDS6

= WRAP_ON_64WORDS7

8:7 RW 0x0

MMIO_PROT

6:0 RO 0x7f

MMIO_CHANNEL_SECURITY

GPCDMA_CHANNEL_CH17_BCOUNT_0

Offset: 0x120020

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH17_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

BCOUNT

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GPCDMA_CHANNEL_CH17_DMA_BYTE_TRA_0

Offset: 0x120024

Read/Write: RO

Parity Protection: N

SCR Protection: SCR_CH17_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

TRANSFER_COUNT

GPCDMA_CHANNEL_CH17_DMA_BYTE_STA_0

Offset: 0x120028

Read/Write: RO

Parity Protection: N

SCR Protection: SCR_CH17_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

DMA_COUNT

GPCDMA_CHANNEL_CH17_ERR_STA_0

Offset: 0x120030

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH17_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

ERROR_STATUS

GPCDMA_CHANNEL_CH17_FIXED_PAT_0

Offset: 0x120034

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH17_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

FIXED_PATTERN

GPCDMA_CHANNEL_CH17_TZ_0

Offset: 0x120038

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Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_TZ_0

Reset: 0x00000003 (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xx11)

Bit Reset Description

1 0x1

MC_PROT_1

0 0x1

MMIO_PROT_1

GPCDMA_CHANNEL_CH18_CSR_0

Offset: 0x130000

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH18_0

Reset: 0x08008400 (0b00xx,1x00,0000,0000,1x00,01xx,xxxx,xxxx)

Bit Reset Description

31 0x0

ENB:

= DISABLE0

= ENABLE1

30 0x0

IE_EOC:

= DISABLE0

= ENABLE1

27 0x1

ONCE:

= CYCLIC_MODE0

= SINGLE_BLOCK1

25:24 0x0

FC_MODE:

= NO_MMIO0

= ONE_MMIO1

= TWO_MMIO2

= FOUR_MMIO3

23:21 0x0

DMA_MODE:

= IO2MEM_NO_FC0

= IO2MEM_FC1

= MEM2IO_NO_FC2

= MEM2IO_FC3

= MEM2MEM4

= RSVD5

= FIXED_PAT6

20:16

0x0

REQ_SEL:

= I2C80

= I2C101

= UARTG2

= UARTC3

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Bit Reset Description

= QSPI05

= QSPI16

= UARTA8

= UARTB9

= UARTF12

= UARTH13

= SPI115

= SPI216

= SPI317

= UARTD19

= UARTE20

= I2C21

= I2C222

= I2C323

= I2C524

= I2C426

= I2C727

= I2C630

= I2C931

= RSVD29

15 0x1

IRQ_MASK:

= DISABLE0

= ENABLE1

13:10 0x1

WEIGHT

GPCDMA_CHANNEL_CH18_STA_0

Offset: 0x130004

Read/Write: See table below

Parity Protection: N

SCR Protection: SCR_CH18_0

Reset: 0x00000000 (0b00x0,0000,0x00,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit R/W Reset Description

31 RO 0x0

BSY:

= WAIT0

= ACTIVE1

30 RW 0x0

ISE_EOC:

= NO_INTR0

= INTR1

28 RO 0x0

PING_PONG_STA:

= PING_INTR_STA0

= PONG_INTR_STA1

0x0

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Bit R/W Reset Description

DMA_ACTIVITY:

= IDLE0

= BUSY1

26 RO 0x0

CHANNEL_PAUSE:

= RESUME0

= PAUSE1

25 RO 0x0

CHANNEL_RX:

= NOT_ACTIVE0

= ACTIVE1

24 RO 0x0

CHANNEL_TX:

= NOT_ACTIVE0

= ACTIVE1

23 RO 0x0

IRQ_INTR_STA:

= DISABLE0

= ENABLE1

21 RO 0x0

TRIG_STA:

= NOT_ACTIVE0

= ACTIVE1

20 RO 0x0

INTR_STA:

= NOT_ACTIVE0

= ACTIVE1

GPCDMA_CHANNEL_CH18_CSRE_0

Offset: 0x130008

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH18_0

Reset: 0x00000000 (0b0xxx,xxxx,xxxx,0000,00xx,xxxx,xxxx,xxxx)

Bit Reset Description

31 0x0

DMA_ACTIVITY:

= RESUME0

= PAUSE1

19:14

0x0

TRIG_SEL:

= SMP_241

= SMP_252

= SMP_263

= SMP_274

= XRQ_A5

= XRQ_B6

= TMR17

= TMR28

= CH09

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Bit Reset Description

= CH110

= CH211

= CH312

= CH413

= CH514

= CH615

= CH716

= CH817

= CH918

= CH1019

= CH1120

= CH1221

= CH1322

= CH1423

= CH1524

= CH1625

= CH1726

= CH1827

= CH1928

= CH2029

= CH2130

= CH2231

= CH2332

= CH2433

= CH2534

= CH2635

= CH2736

= CH2837

= CH2938

= CH3039

= CH3140

= RSVD0

GPCDMA_CHANNEL_CH18_SRC_PTR_0

Offset: 0x13000c

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH18_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

SRC_PTR

GPCDMA_CHANNEL_CH18_DST_PTR_0

Offset: 0x130010

Read/Write: R/W

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Parity Protection: N

SCR Protection: SCR_CH18_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

DST_PTR

GPCDMA_CHANNEL_CH18_HI_ADR_PTR_0

Offset: 0x130014

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH18_0

Reset: 0x00000000 (0bxxxx,xxxx,0000,0000,xxxx,xxxx,0000,0000)

Bit Reset Description

23:16 0x0

HI_DST_PTR

7:0 0x0

HI_SRC_PTR

GPCDMA_CHANNEL_CH18_MC_SEQ_0

Offset: 0x130018

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH18_0

Reset: 0x03800000 (0b0000,0011,1000,0000,0000,0000,0000,0000)

Bit Reset Description

31 0x0

MC_DATA_SWAP:

= DISABLE0

= ENABLE1

30:25 0x1

MC_REQ_CNT

24:23 0x3

MC_BURST:

= DMA_BURST_2WORDS0

= DMA_BURST_16WORDS3

22:20 0x0

MC_ADDR_WRAP1:

= NO_WRAP0

= WRAP_0N_32WORDS1

= WRAP_ON_64WORDS2

= WRAP_ON_128WORDS3

= WRAP_ON_256WORDS4

= WRAP_ON_512WORDS5

= WRAP_ON_1024WORDS6

= WRAP_ON_2048WORDS7

19:17

0x0

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Bit Reset Description

MC_ADDR_WRAP0:

= NO_WRAP0

= WRAP_0N_32WORDS1

= WRAP_ON_64WORDS2

= WRAP_ON_128WORDS3

= WRAP_ON_256WORDS4

= WRAP_ON_512WORDS5

= WRAP_ON_1024WORDS6

= WRAP_ON_2048WORDS7

16 0x0

MC_AXIID

15:14 0x0

MC_PROT

13:7 0x0

STREAMID1

6:0 0x0

STREAMID0

GPCDMA_CHANNEL_CH18_MMIO_SEQ_0

Offset: 0x13001c

Read/Write: See table below

Parity Protection: N

SCR Protection: SCR_CH18_0

Reset: 0x2381007f (0b0010,0011,1000,0001,xxxx,xxx0,0111,1111)

Bit R/W Reset Description

31 RW 0x0

DBL_BUF:

= DISABLE0

= ENABLE1

30:28 RW 0x2

MMIO_BUS_WIDTH:

= BUS_WIDTH_80

= BUS_WIDTH_161

= BUS_WIDTH_322

27 RW 0x0

MMIO_DATA_SWAP:

= DISABLE0

= ENABLE1

26:23 RW 0x7

MMIO_BURST:

= DMA_BURST_1WORDS0

= DMA_BURST_2WORDS1

= DMA_BURST_4WORDS3

= DMA_BURST_8WORDS7

= DMA_BURST_16WORDS15

22:19

0x0

MMIO_MASTER_ID:

= RSVD0

= CCPLEX1

= CCPLEX_DPMU2

= BPMP3

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Bit R/W Reset Description

= SPE4

= SCE5

= DMA_PER6

= TSECA7

= TSECB8

= JTAGM9

= CSITE10

= APE11

18:16 RW 0x1

MMIO_ADDR_WRAP:

= NO_WRAP0

= WRAP_0N_1WORDS1

= WRAP_ON_2WORDS2

= WRAP_ON_4WORDS3

= WRAP_ON_8WORDS4

= WRAP_ON_16WORDS5

= WRAP_ON_32WORDS6

= WRAP_ON_64WORDS7

8:7 RW 0x0

MMIO_PROT

6:0 RO 0x7f

MMIO_CHANNEL_SECURITY

GPCDMA_CHANNEL_CH18_BCOUNT_0

Offset: 0x130020

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH18_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

BCOUNT

GPCDMA_CHANNEL_CH18_DMA_BYTE_TRA_0

Offset: 0x130024

Read/Write: RO

Parity Protection: N

SCR Protection: SCR_CH18_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

TRANSFER_COUNT

GPCDMA_CHANNEL_CH18_DMA_BYTE_STA_0

Offset: 0x130028

Read/Write: RO

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Parity Protection: N

SCR Protection: SCR_CH18_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

DMA_COUNT

GPCDMA_CHANNEL_CH18_ERR_STA_0

Offset: 0x130030

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH18_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

ERROR_STATUS

GPCDMA_CHANNEL_CH18_FIXED_PAT_0

Offset: 0x130034

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH18_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

FIXED_PATTERN

GPCDMA_CHANNEL_CH18_TZ_0

Offset: 0x130038

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_TZ_0

Reset: 0x00000003 (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xx11)

Bit Reset Description

1 0x1

MC_PROT_1

0 0x1

MMIO_PROT_1

GPCDMA_CHANNEL_CH19_CSR_0

Offset: 0x140000

Read/Write: R/W

Parity Protection: N

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SCR Protection: SCR_CH19_0

Reset: 0x08008400 (0b00xx,1x00,0000,0000,1x00,01xx,xxxx,xxxx)

Bit Reset Description

31 0x0

ENB:

= DISABLE0

= ENABLE1

30 0x0

IE_EOC:

= DISABLE0

= ENABLE1

27 0x1

ONCE:

= CYCLIC_MODE0

= SINGLE_BLOCK1

25:24 0x0

FC_MODE:

= NO_MMIO0

= ONE_MMIO1

= TWO_MMIO2

= FOUR_MMIO3

23:21 0x0

DMA_MODE:

= IO2MEM_NO_FC0

= IO2MEM_FC1

= MEM2IO_NO_FC2

= MEM2IO_FC3

= MEM2MEM4

= RSVD5

= FIXED_PAT6

20:16

0x0

REQ_SEL:

= I2C80

= I2C101

= UARTG2

= UARTC3

= QSPI05

= QSPI16

= UARTA8

= UARTB9

= UARTF12

= UARTH13

= SPI115

= SPI216

= SPI317

= UARTD19

= UARTE20

= I2C21

= I2C222

= I2C323

= I2C524

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Bit Reset Description

= I2C426

= I2C727

= I2C630

= I2C931

= RSVD29

15 0x1

IRQ_MASK:

= DISABLE0

= ENABLE1

13:10 0x1

WEIGHT

GPCDMA_CHANNEL_CH19_STA_0

Offset: 0x140004

Read/Write: See table below

Parity Protection: N

SCR Protection: SCR_CH19_0

Reset: 0x00000000 (0b00x0,0000,0x00,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit R/W Reset Description

31 RO 0x0

BSY:

= WAIT0

= ACTIVE1

30 RW 0x0

ISE_EOC:

= NO_INTR0

= INTR1

28 RO 0x0

PING_PONG_STA:

= PING_INTR_STA0

= PONG_INTR_STA1

27 RO 0x0

DMA_ACTIVITY:

= IDLE0

= BUSY1

26 RO 0x0

CHANNEL_PAUSE:

= RESUME0

= PAUSE1

25 RO 0x0

CHANNEL_RX:

= NOT_ACTIVE0

= ACTIVE1

24 RO 0x0

CHANNEL_TX:

= NOT_ACTIVE0

= ACTIVE1

23 RO 0x0

IRQ_INTR_STA:

= DISABLE0

= ENABLE1

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Bit R/W Reset Description

21 RO 0x0

TRIG_STA:

= NOT_ACTIVE0

= ACTIVE1

20 RO 0x0

INTR_STA:

= NOT_ACTIVE0

= ACTIVE1

GPCDMA_CHANNEL_CH19_CSRE_0

Offset: 0x140008

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH19_0

Reset: 0x00000000 (0b0xxx,xxxx,xxxx,0000,00xx,xxxx,xxxx,xxxx)

Bit Reset Description

31 0x0

DMA_ACTIVITY:

= RESUME0

= PAUSE1

19:14

0x0

TRIG_SEL:

= SMP_241

= SMP_252

= SMP_263

= SMP_274

= XRQ_A5

= XRQ_B6

= TMR17

= TMR28

= CH09

= CH110

= CH211

= CH312

= CH413

= CH514

= CH615

= CH716

= CH817

= CH918

= CH1019

= CH1120

= CH1221

= CH1322

= CH1423

= CH1524

= CH1625

= CH1726

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Bit Reset Description

= CH1827

= CH1928

= CH2029

= CH2130

= CH2231

= CH2332

= CH2433

= CH2534

= CH2635

= CH2736

= CH2837

= CH2938

= CH3039

= CH3140

= RSVD0

GPCDMA_CHANNEL_CH19_SRC_PTR_0

Offset: 0x14000c

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH19_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

SRC_PTR

GPCDMA_CHANNEL_CH19_DST_PTR_0

Offset: 0x140010

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH19_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

DST_PTR

GPCDMA_CHANNEL_CH19_HI_ADR_PTR_0

Offset: 0x140014

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH19_0

Reset: 0x00000000 (0bxxxx,xxxx,0000,0000,xxxx,xxxx,0000,0000)

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Bit Reset Description

23:16 0x0

HI_DST_PTR

7:0 0x0

HI_SRC_PTR

GPCDMA_CHANNEL_CH19_MC_SEQ_0

Offset: 0x140018

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH19_0

Reset: 0x03800000 (0b0000,0011,1000,0000,0000,0000,0000,0000)

Bit Reset Description

31 0x0

MC_DATA_SWAP:

= DISABLE0

= ENABLE1

30:25 0x1

MC_REQ_CNT

24:23 0x3

MC_BURST:

= DMA_BURST_2WORDS0

= DMA_BURST_16WORDS3

22:20 0x0

MC_ADDR_WRAP1:

= NO_WRAP0

= WRAP_0N_32WORDS1

= WRAP_ON_64WORDS2

= WRAP_ON_128WORDS3

= WRAP_ON_256WORDS4

= WRAP_ON_512WORDS5

= WRAP_ON_1024WORDS6

= WRAP_ON_2048WORDS7

19:17 0x0

MC_ADDR_WRAP0:

= NO_WRAP0

= WRAP_0N_32WORDS1

= WRAP_ON_64WORDS2

= WRAP_ON_128WORDS3

= WRAP_ON_256WORDS4

= WRAP_ON_512WORDS5

= WRAP_ON_1024WORDS6

= WRAP_ON_2048WORDS7

16 0x0

MC_AXIID

15:14 0x0

MC_PROT

13:7 0x0

STREAMID1

6:0 0x0

STREAMID0

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GPCDMA_CHANNEL_CH19_MMIO_SEQ_0

Offset: 0x14001c

Read/Write: See table below

Parity Protection: N

SCR Protection: SCR_CH19_0

Reset: 0x2381007f (0b0010,0011,1000,0001,xxxx,xxx0,0111,1111)

Bit R/W Reset Description

31 RW 0x0

DBL_BUF:

= DISABLE0

= ENABLE1

30:28 RW 0x2

MMIO_BUS_WIDTH:

= BUS_WIDTH_80

= BUS_WIDTH_161

= BUS_WIDTH_322

27 RW 0x0

MMIO_DATA_SWAP:

= DISABLE0

= ENABLE1

26:23 RW 0x7

MMIO_BURST:

= DMA_BURST_1WORDS0

= DMA_BURST_2WORDS1

= DMA_BURST_4WORDS3

= DMA_BURST_8WORDS7

= DMA_BURST_16WORDS15

22:19 RO 0x0

MMIO_MASTER_ID:

= RSVD0

= CCPLEX1

= CCPLEX_DPMU2

= BPMP3

= SPE4

= SCE5

= DMA_PER6

= TSECA7

= TSECB8

= JTAGM9

= CSITE10

= APE11

18:16 RW 0x1

MMIO_ADDR_WRAP:

= NO_WRAP0

= WRAP_0N_1WORDS1

= WRAP_ON_2WORDS2

= WRAP_ON_4WORDS3

= WRAP_ON_8WORDS4

= WRAP_ON_16WORDS5

= WRAP_ON_32WORDS6

= WRAP_ON_64WORDS7

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Bit R/W Reset Description

8:7 RW 0x0

MMIO_PROT

6:0 RO 0x7f

MMIO_CHANNEL_SECURITY

GPCDMA_CHANNEL_CH19_BCOUNT_0

Offset: 0x140020

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH19_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

BCOUNT

GPCDMA_CHANNEL_CH19_DMA_BYTE_TRA_0

Offset: 0x140024

Read/Write: RO

Parity Protection: N

SCR Protection: SCR_CH19_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

TRANSFER_COUNT

GPCDMA_CHANNEL_CH19_DMA_BYTE_STA_0

Offset: 0x140028

Read/Write: RO

Parity Protection: N

SCR Protection: SCR_CH19_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

DMA_COUNT

GPCDMA_CHANNEL_CH19_ERR_STA_0

Offset: 0x140030

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH19_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

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Bit Reset Description

31:0 0x0

ERROR_STATUS

GPCDMA_CHANNEL_CH19_FIXED_PAT_0

Offset: 0x140034

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH19_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

FIXED_PATTERN

GPCDMA_CHANNEL_CH19_TZ_0

Offset: 0x140038

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_TZ_0

Reset: 0x00000003 (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xx11)

Bit Reset Description

1 0x1

MC_PROT_1

0 0x1

MMIO_PROT_1

GPCDMA_CHANNEL_CH20_CSR_0

Offset: 0x150000

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH20_0

Reset: 0x08008400 (0b00xx,1x00,0000,0000,1x00,01xx,xxxx,xxxx)

Bit Reset Description

31 0x0

ENB:

= DISABLE0

= ENABLE1

30 0x0

IE_EOC:

= DISABLE0

= ENABLE1

27 0x1

ONCE:

= CYCLIC_MODE0

= SINGLE_BLOCK1

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Bit Reset Description

25:24 0x0

FC_MODE:

= NO_MMIO0

= ONE_MMIO1

= TWO_MMIO2

= FOUR_MMIO3

23:21 0x0

DMA_MODE:

= IO2MEM_NO_FC0

= IO2MEM_FC1

= MEM2IO_NO_FC2

= MEM2IO_FC3

= MEM2MEM4

= RSVD5

= FIXED_PAT6

20:16 0x0

REQ_SEL:

= I2C80

= I2C101

= UARTG2

= UARTC3

= QSPI05

= QSPI16

= UARTA8

= UARTB9

= UARTF12

= UARTH13

= SPI115

= SPI216

= SPI317

= UARTD19

= UARTE20

= I2C21

= I2C222

= I2C323

= I2C524

= I2C426

= I2C727

= I2C630

= I2C931

= RSVD29

15 0x1

IRQ_MASK:

= DISABLE0

= ENABLE1

13:10 0x1

WEIGHT

GPCDMA_CHANNEL_CH20_STA_0

Offset: 0x150004

Read/Write: See table below

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Parity Protection: N

SCR Protection: SCR_CH20_0

Reset: 0x00000000 (0b00x0,0000,0x00,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit R/W Reset Description

31 RO 0x0

BSY:

= WAIT0

= ACTIVE1

30 RW 0x0

ISE_EOC:

= NO_INTR0

= INTR1

28 RO 0x0

PING_PONG_STA:

= PING_INTR_STA0

= PONG_INTR_STA1

27 RO 0x0

DMA_ACTIVITY:

= IDLE0

= BUSY1

26 RO 0x0

CHANNEL_PAUSE:

= RESUME0

= PAUSE1

25 RO 0x0

CHANNEL_RX:

= NOT_ACTIVE0

= ACTIVE1

24 RO 0x0

CHANNEL_TX:

= NOT_ACTIVE0

= ACTIVE1

23 RO 0x0

IRQ_INTR_STA:

= DISABLE0

= ENABLE1

21 RO 0x0

TRIG_STA:

= NOT_ACTIVE0

= ACTIVE1

20 RO 0x0

INTR_STA:

= NOT_ACTIVE0

= ACTIVE1

GPCDMA_CHANNEL_CH20_CSRE_0

Offset: 0x150008

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH20_0

Reset: 0x00000000 (0b0xxx,xxxx,xxxx,0000,00xx,xxxx,xxxx,xxxx)

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Bit Reset Description

31 0x0

DMA_ACTIVITY:

= RESUME0

= PAUSE1

19:14 0x0

TRIG_SEL:

= SMP_241

= SMP_252

= SMP_263

= SMP_274

= XRQ_A5

= XRQ_B6

= TMR17

= TMR28

= CH09

= CH110

= CH211

= CH312

= CH413

= CH514

= CH615

= CH716

= CH817

= CH918

= CH1019

= CH1120

= CH1221

= CH1322

= CH1423

= CH1524

= CH1625

= CH1726

= CH1827

= CH1928

= CH2029

= CH2130

= CH2231

= CH2332

= CH2433

= CH2534

= CH2635

= CH2736

= CH2837

= CH2938

= CH3039

= CH3140

= RSVD0

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GPCDMA_CHANNEL_CH20_SRC_PTR_0

Offset: 0x15000c

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH20_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

SRC_PTR

GPCDMA_CHANNEL_CH20_DST_PTR_0

Offset: 0x150010

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH20_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

DST_PTR

GPCDMA_CHANNEL_CH20_HI_ADR_PTR_0

Offset: 0x150014

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH20_0

Reset: 0x00000000 (0bxxxx,xxxx,0000,0000,xxxx,xxxx,0000,0000)

Bit Reset Description

23:16 0x0

HI_DST_PTR

7:0 0x0

HI_SRC_PTR

GPCDMA_CHANNEL_CH20_MC_SEQ_0

Offset: 0x150018

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH20_0

Reset: 0x03800000 (0b0000,0011,1000,0000,0000,0000,0000,0000)

Bit Reset Description

31 0x0

MC_DATA_SWAP:

= DISABLE0

= ENABLE1

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Bit Reset Description

30:25 0x1

MC_REQ_CNT

24:23 0x3

MC_BURST:

= DMA_BURST_2WORDS0

= DMA_BURST_16WORDS3

22:20 0x0

MC_ADDR_WRAP1:

= NO_WRAP0

= WRAP_0N_32WORDS1

= WRAP_ON_64WORDS2

= WRAP_ON_128WORDS3

= WRAP_ON_256WORDS4

= WRAP_ON_512WORDS5

= WRAP_ON_1024WORDS6

= WRAP_ON_2048WORDS7

19:17 0x0

MC_ADDR_WRAP0:

= NO_WRAP0

= WRAP_0N_32WORDS1

= WRAP_ON_64WORDS2

= WRAP_ON_128WORDS3

= WRAP_ON_256WORDS4

= WRAP_ON_512WORDS5

= WRAP_ON_1024WORDS6

= WRAP_ON_2048WORDS7

16 0x0

MC_AXIID

15:14 0x0

MC_PROT

13:7 0x0

STREAMID1

6:0 0x0

STREAMID0

GPCDMA_CHANNEL_CH20_MMIO_SEQ_0

Offset: 0x15001c

Read/Write: See table below

Parity Protection: N

SCR Protection: SCR_CH20_0

Reset: 0x2381007f (0b0010,0011,1000,0001,xxxx,xxx0,0111,1111)

Bit R/W Reset Description

31 RW 0x0

DBL_BUF:

= DISABLE0

= ENABLE1

30:28 RW 0x2

MMIO_BUS_WIDTH:

= BUS_WIDTH_80

= BUS_WIDTH_161

= BUS_WIDTH_322

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Bit R/W Reset Description

27 RW 0x0

MMIO_DATA_SWAP:

= DISABLE0

= ENABLE1

26:23 RW 0x7

MMIO_BURST:

= DMA_BURST_1WORDS0

= DMA_BURST_2WORDS1

= DMA_BURST_4WORDS3

= DMA_BURST_8WORDS7

= DMA_BURST_16WORDS15

22:19 RO 0x0

MMIO_MASTER_ID:

= RSVD0

= CCPLEX1

= CCPLEX_DPMU2

= BPMP3

= SPE4

= SCE5

= DMA_PER6

= TSECA7

= TSECB8

= JTAGM9

= CSITE10

= APE11

18:16 RW 0x1

MMIO_ADDR_WRAP:

= NO_WRAP0

= WRAP_0N_1WORDS1

= WRAP_ON_2WORDS2

= WRAP_ON_4WORDS3

= WRAP_ON_8WORDS4

= WRAP_ON_16WORDS5

= WRAP_ON_32WORDS6

= WRAP_ON_64WORDS7

8:7 RW 0x0

MMIO_PROT

6:0 RO 0x7f

MMIO_CHANNEL_SECURITY

GPCDMA_CHANNEL_CH20_BCOUNT_0

Offset: 0x150020

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH20_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

BCOUNT

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GPCDMA_CHANNEL_CH20_DMA_BYTE_TRA_0

Offset: 0x150024

Read/Write: RO

Parity Protection: N

SCR Protection: SCR_CH20_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

TRANSFER_COUNT

GPCDMA_CHANNEL_CH20_DMA_BYTE_STA_0

Offset: 0x150028

Read/Write: RO

Parity Protection: N

SCR Protection: SCR_CH20_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

DMA_COUNT

GPCDMA_CHANNEL_CH20_ERR_STA_0

Offset: 0x150030

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH20_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

ERROR_STATUS

GPCDMA_CHANNEL_CH20_FIXED_PAT_0

Offset: 0x150034

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH20_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

FIXED_PATTERN

GPCDMA_CHANNEL_CH20_TZ_0

Offset: 0x150038

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Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_TZ_0

Reset: 0x00000003 (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xx11)

Bit Reset Description

1 0x1

MC_PROT_1

0 0x1

MMIO_PROT_1

GPCDMA_CHANNEL_CH21_CSR_0

Offset: 0x160000

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH21_0

Reset: 0x08008400 (0b00xx,1x00,0000,0000,1x00,01xx,xxxx,xxxx)

Bit Reset Description

31 0x0

ENB:

= DISABLE0

= ENABLE1

30 0x0

IE_EOC:

= DISABLE0

= ENABLE1

27 0x1

ONCE:

= CYCLIC_MODE0

= SINGLE_BLOCK1

25:24 0x0

FC_MODE:

= NO_MMIO0

= ONE_MMIO1

= TWO_MMIO2

= FOUR_MMIO3

23:21 0x0

DMA_MODE:

= IO2MEM_NO_FC0

= IO2MEM_FC1

= MEM2IO_NO_FC2

= MEM2IO_FC3

= MEM2MEM4

= RSVD5

= FIXED_PAT6

20:16

0x0

REQ_SEL:

= I2C80

= I2C101

= UARTG2

= UARTC3

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Bit Reset Description

= QSPI05

= QSPI16

= UARTA8

= UARTB9

= UARTF12

= UARTH13

= SPI115

= SPI216

= SPI317

= UARTD19

= UARTE20

= I2C21

= I2C222

= I2C323

= I2C524

= I2C426

= I2C727

= I2C630

= I2C931

= RSVD29

15 0x1

IRQ_MASK:

= DISABLE0

= ENABLE1

13:10 0x1

WEIGHT

GPCDMA_CHANNEL_CH21_STA_0

Offset: 0x160004

Read/Write: See table below

Parity Protection: N

SCR Protection: SCR_CH21_0

Reset: 0x00000000 (0b00x0,0000,0x00,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit R/W Reset Description

31 RO 0x0

BSY:

= WAIT0

= ACTIVE1

30 RW 0x0

ISE_EOC:

= NO_INTR0

= INTR1

28 RO 0x0

PING_PONG_STA:

= PING_INTR_STA0

= PONG_INTR_STA1

0x0

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Bit R/W Reset Description

DMA_ACTIVITY:

= IDLE0

= BUSY1

26 RO 0x0

CHANNEL_PAUSE:

= RESUME0

= PAUSE1

25 RO 0x0

CHANNEL_RX:

= NOT_ACTIVE0

= ACTIVE1

24 RO 0x0

CHANNEL_TX:

= NOT_ACTIVE0

= ACTIVE1

23 RO 0x0

IRQ_INTR_STA:

= DISABLE0

= ENABLE1

21 RO 0x0

TRIG_STA:

= NOT_ACTIVE0

= ACTIVE1

20 RO 0x0

INTR_STA:

= NOT_ACTIVE0

= ACTIVE1

GPCDMA_CHANNEL_CH21_CSRE_0

Offset: 0x160008

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH21_0

Reset: 0x00000000 (0b0xxx,xxxx,xxxx,0000,00xx,xxxx,xxxx,xxxx)

Bit Reset Description

31 0x0

DMA_ACTIVITY:

= RESUME0

= PAUSE1

19:14

0x0

TRIG_SEL:

= SMP_241

= SMP_252

= SMP_263

= SMP_274

= XRQ_A5

= XRQ_B6

= TMR17

= TMR28

= CH09

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Bit Reset Description

= CH110

= CH211

= CH312

= CH413

= CH514

= CH615

= CH716

= CH817

= CH918

= CH1019

= CH1120

= CH1221

= CH1322

= CH1423

= CH1524

= CH1625

= CH1726

= CH1827

= CH1928

= CH2029

= CH2130

= CH2231

= CH2332

= CH2433

= CH2534

= CH2635

= CH2736

= CH2837

= CH2938

= CH3039

= CH3140

= RSVD0

GPCDMA_CHANNEL_CH21_SRC_PTR_0

Offset: 0x16000c

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH21_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

SRC_PTR

GPCDMA_CHANNEL_CH21_DST_PTR_0

Offset: 0x160010

Read/Write: R/W

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Parity Protection: N

SCR Protection: SCR_CH21_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

DST_PTR

GPCDMA_CHANNEL_CH21_HI_ADR_PTR_0

Offset: 0x160014

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH21_0

Reset: 0x00000000 (0bxxxx,xxxx,0000,0000,xxxx,xxxx,0000,0000)

Bit Reset Description

23:16 0x0

HI_DST_PTR

7:0 0x0

HI_SRC_PTR

GPCDMA_CHANNEL_CH21_MC_SEQ_0

Offset: 0x160018

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH21_0

Reset: 0x03800000 (0b0000,0011,1000,0000,0000,0000,0000,0000)

Bit Reset Description

31 0x0

MC_DATA_SWAP:

= DISABLE0

= ENABLE1

30:25 0x1

MC_REQ_CNT

24:23 0x3

MC_BURST:

= DMA_BURST_2WORDS0

= DMA_BURST_16WORDS3

22:20 0x0

MC_ADDR_WRAP1:

= NO_WRAP0

= WRAP_0N_32WORDS1

= WRAP_ON_64WORDS2

= WRAP_ON_128WORDS3

= WRAP_ON_256WORDS4

= WRAP_ON_512WORDS5

= WRAP_ON_1024WORDS6

= WRAP_ON_2048WORDS7

19:17

0x0

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Bit Reset Description

MC_ADDR_WRAP0:

= NO_WRAP0

= WRAP_0N_32WORDS1

= WRAP_ON_64WORDS2

= WRAP_ON_128WORDS3

= WRAP_ON_256WORDS4

= WRAP_ON_512WORDS5

= WRAP_ON_1024WORDS6

= WRAP_ON_2048WORDS7

16 0x0

MC_AXIID

15:14 0x0

MC_PROT

13:7 0x0

STREAMID1

6:0 0x0

STREAMID0

GPCDMA_CHANNEL_CH21_MMIO_SEQ_0

Offset: 0x16001c

Read/Write: See table below

Parity Protection: N

SCR Protection: SCR_CH21_0

Reset: 0x2381007f (0b0010,0011,1000,0001,xxxx,xxx0,0111,1111)

Bit R/W Reset Description

31 RW 0x0

DBL_BUF:

= DISABLE0

= ENABLE1

30:28 RW 0x2

MMIO_BUS_WIDTH:

= BUS_WIDTH_80

= BUS_WIDTH_161

= BUS_WIDTH_322

27 RW 0x0

MMIO_DATA_SWAP:

= DISABLE0

= ENABLE1

26:23 RW 0x7

MMIO_BURST:

= DMA_BURST_1WORDS0

= DMA_BURST_2WORDS1

= DMA_BURST_4WORDS3

= DMA_BURST_8WORDS7

= DMA_BURST_16WORDS15

22:19

0x0

MMIO_MASTER_ID:

= RSVD0

= CCPLEX1

= CCPLEX_DPMU2

= BPMP3

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Bit R/W Reset Description

= SPE4

= SCE5

= DMA_PER6

= TSECA7

= TSECB8

= JTAGM9

= CSITE10

= APE11

18:16 RW 0x1

MMIO_ADDR_WRAP:

= NO_WRAP0

= WRAP_0N_1WORDS1

= WRAP_ON_2WORDS2

= WRAP_ON_4WORDS3

= WRAP_ON_8WORDS4

= WRAP_ON_16WORDS5

= WRAP_ON_32WORDS6

= WRAP_ON_64WORDS7

8:7 RW 0x0

MMIO_PROT

6:0 RO 0x7f

MMIO_CHANNEL_SECURITY

GPCDMA_CHANNEL_CH21_BCOUNT_0

Offset: 0x160020

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH21_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

BCOUNT

GPCDMA_CHANNEL_CH21_DMA_BYTE_TRA_0

Offset: 0x160024

Read/Write: RO

Parity Protection: N

SCR Protection: SCR_CH21_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

TRANSFER_COUNT

GPCDMA_CHANNEL_CH21_DMA_BYTE_STA_0

Offset: 0x160028

Read/Write: RO

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Parity Protection: N

SCR Protection: SCR_CH21_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

DMA_COUNT

GPCDMA_CHANNEL_CH21_ERR_STA_0

Offset: 0x160030

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH21_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

ERROR_STATUS

GPCDMA_CHANNEL_CH21_FIXED_PAT_0

Offset: 0x160034

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH21_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

FIXED_PATTERN

GPCDMA_CHANNEL_CH21_TZ_0

Offset: 0x160038

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_TZ_0

Reset: 0x00000003 (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xx11)

Bit Reset Description

1 0x1

MC_PROT_1

0 0x1

MMIO_PROT_1

GPCDMA_CHANNEL_CH22_CSR_0

Offset: 0x170000

Read/Write: R/W

Parity Protection: N

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SCR Protection: SCR_CH22_0

Reset: 0x08008400 (0b00xx,1x00,0000,0000,1x00,01xx,xxxx,xxxx)

Bit Reset Description

31 0x0

ENB:

= DISABLE0

= ENABLE1

30 0x0

IE_EOC:

= DISABLE0

= ENABLE1

27 0x1

ONCE:

= CYCLIC_MODE0

= SINGLE_BLOCK1

25:24 0x0

FC_MODE:

= NO_MMIO0

= ONE_MMIO1

= TWO_MMIO2

= FOUR_MMIO3

23:21 0x0

DMA_MODE:

= IO2MEM_NO_FC0

= IO2MEM_FC1

= MEM2IO_NO_FC2

= MEM2IO_FC3

= MEM2MEM4

= RSVD5

= FIXED_PAT6

20:16

0x0

REQ_SEL:

= I2C80

= I2C101

= UARTG2

= UARTC3

= QSPI05

= QSPI16

= UARTA8

= UARTB9

= UARTF12

= UARTH13

= SPI115

= SPI216

= SPI317

= UARTD19

= UARTE20

= I2C21

= I2C222

= I2C323

= I2C524

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Bit Reset Description

= I2C426

= I2C727

= I2C630

= I2C931

= RSVD29

15 0x1

IRQ_MASK:

= DISABLE0

= ENABLE1

13:10 0x1

WEIGHT

GPCDMA_CHANNEL_CH22_STA_0

Offset: 0x170004

Read/Write: See table below

Parity Protection: N

SCR Protection: SCR_CH22_0

Reset: 0x00000000 (0b00x0,0000,0x00,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit R/W Reset Description

31 RO 0x0

BSY:

= WAIT0

= ACTIVE1

30 RW 0x0

ISE_EOC:

= NO_INTR0

= INTR1

28 RO 0x0

PING_PONG_STA:

= PING_INTR_STA0

= PONG_INTR_STA1

27 RO 0x0

DMA_ACTIVITY:

= IDLE0

= BUSY1

26 RO 0x0

CHANNEL_PAUSE:

= RESUME0

= PAUSE1

25 RO 0x0

CHANNEL_RX:

= NOT_ACTIVE0

= ACTIVE1

24 RO 0x0

CHANNEL_TX:

= NOT_ACTIVE0

= ACTIVE1

23 RO 0x0

IRQ_INTR_STA:

= DISABLE0

= ENABLE1

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Bit R/W Reset Description

21 RO 0x0

TRIG_STA:

= NOT_ACTIVE0

= ACTIVE1

20 RO 0x0

INTR_STA:

= NOT_ACTIVE0

= ACTIVE1

GPCDMA_CHANNEL_CH22_CSRE_0

Offset: 0x170008

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH22_0

Reset: 0x00000000 (0b0xxx,xxxx,xxxx,0000,00xx,xxxx,xxxx,xxxx)

Bit Reset Description

31 0x0

DMA_ACTIVITY:

= RESUME0

= PAUSE1

19:14

0x0

TRIG_SEL:

= SMP_241

= SMP_252

= SMP_263

= SMP_274

= XRQ_A5

= XRQ_B6

= TMR17

= TMR28

= CH09

= CH110

= CH211

= CH312

= CH413

= CH514

= CH615

= CH716

= CH817

= CH918

= CH1019

= CH1120

= CH1221

= CH1322

= CH1423

= CH1524

= CH1625

= CH1726

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Bit Reset Description

= CH1827

= CH1928

= CH2029

= CH2130

= CH2231

= CH2332

= CH2433

= CH2534

= CH2635

= CH2736

= CH2837

= CH2938

= CH3039

= CH3140

= RSVD0

GPCDMA_CHANNEL_CH22_SRC_PTR_0

Offset: 0x17000c

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH22_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

SRC_PTR

GPCDMA_CHANNEL_CH22_DST_PTR_0

Offset: 0x170010

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH22_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

DST_PTR

GPCDMA_CHANNEL_CH22_HI_ADR_PTR_0

Offset: 0x170014

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH22_0

Reset: 0x00000000 (0bxxxx,xxxx,0000,0000,xxxx,xxxx,0000,0000)

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Bit Reset Description

23:16 0x0

HI_DST_PTR

7:0 0x0

HI_SRC_PTR

GPCDMA_CHANNEL_CH22_MC_SEQ_0

Offset: 0x170018

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH22_0

Reset: 0x03800000 (0b0000,0011,1000,0000,0000,0000,0000,0000)

Bit Reset Description

31 0x0

MC_DATA_SWAP:

= DISABLE0

= ENABLE1

30:25 0x1

MC_REQ_CNT

24:23 0x3

MC_BURST:

= DMA_BURST_2WORDS0

= DMA_BURST_16WORDS3

22:20 0x0

MC_ADDR_WRAP1:

= NO_WRAP0

= WRAP_0N_32WORDS1

= WRAP_ON_64WORDS2

= WRAP_ON_128WORDS3

= WRAP_ON_256WORDS4

= WRAP_ON_512WORDS5

= WRAP_ON_1024WORDS6

= WRAP_ON_2048WORDS7

19:17 0x0

MC_ADDR_WRAP0:

= NO_WRAP0

= WRAP_0N_32WORDS1

= WRAP_ON_64WORDS2

= WRAP_ON_128WORDS3

= WRAP_ON_256WORDS4

= WRAP_ON_512WORDS5

= WRAP_ON_1024WORDS6

= WRAP_ON_2048WORDS7

16 0x0

MC_AXIID

15:14 0x0

MC_PROT

13:7 0x0

STREAMID1

6:0 0x0

STREAMID0

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GPCDMA_CHANNEL_CH22_MMIO_SEQ_0

Offset: 0x17001c

Read/Write: See table below

Parity Protection: N

SCR Protection: SCR_CH22_0

Reset: 0x2381007f (0b0010,0011,1000,0001,xxxx,xxx0,0111,1111)

Bit R/W Reset Description

31 RW 0x0

DBL_BUF:

= DISABLE0

= ENABLE1

30:28 RW 0x2

MMIO_BUS_WIDTH:

= BUS_WIDTH_80

= BUS_WIDTH_161

= BUS_WIDTH_322

27 RW 0x0

MMIO_DATA_SWAP:

= DISABLE0

= ENABLE1

26:23 RW 0x7

MMIO_BURST:

= DMA_BURST_1WORDS0

= DMA_BURST_2WORDS1

= DMA_BURST_4WORDS3

= DMA_BURST_8WORDS7

= DMA_BURST_16WORDS15

22:19 RO 0x0

MMIO_MASTER_ID:

= RSVD0

= CCPLEX1

= CCPLEX_DPMU2

= BPMP3

= SPE4

= SCE5

= DMA_PER6

= TSECA7

= TSECB8

= JTAGM9

= CSITE10

= APE11

18:16 RW 0x1

MMIO_ADDR_WRAP:

= NO_WRAP0

= WRAP_0N_1WORDS1

= WRAP_ON_2WORDS2

= WRAP_ON_4WORDS3

= WRAP_ON_8WORDS4

= WRAP_ON_16WORDS5

= WRAP_ON_32WORDS6

= WRAP_ON_64WORDS7

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Bit R/W Reset Description

8:7 RW 0x0

MMIO_PROT

6:0 RO 0x7f

MMIO_CHANNEL_SECURITY

GPCDMA_CHANNEL_CH22_BCOUNT_0

Offset: 0x170020

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH22_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

BCOUNT

GPCDMA_CHANNEL_CH22_DMA_BYTE_TRA_0

Offset: 0x170024

Read/Write: RO

Parity Protection: N

SCR Protection: SCR_CH22_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

TRANSFER_COUNT

GPCDMA_CHANNEL_CH22_DMA_BYTE_STA_0

Offset: 0x170028

Read/Write: RO

Parity Protection: N

SCR Protection: SCR_CH22_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

DMA_COUNT

GPCDMA_CHANNEL_CH22_ERR_STA_0

Offset: 0x170030

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH22_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

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Bit Reset Description

31:0 0x0

ERROR_STATUS

GPCDMA_CHANNEL_CH22_FIXED_PAT_0

Offset: 0x170034

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH22_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

FIXED_PATTERN

GPCDMA_CHANNEL_CH22_TZ_0

Offset: 0x170038

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_TZ_0

Reset: 0x00000003 (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xx11)

Bit Reset Description

1 0x1

MC_PROT_1

0 0x1

MMIO_PROT_1

GPCDMA_CHANNEL_CH23_CSR_0

Offset: 0x180000

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH23_0

Reset: 0x08008400 (0b00xx,1x00,0000,0000,1x00,01xx,xxxx,xxxx)

Bit Reset Description

31 0x0

ENB:

= DISABLE0

= ENABLE1

30 0x0

IE_EOC:

= DISABLE0

= ENABLE1

27 0x1

ONCE:

= CYCLIC_MODE0

= SINGLE_BLOCK1

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Bit Reset Description

25:24 0x0

FC_MODE:

= NO_MMIO0

= ONE_MMIO1

= TWO_MMIO2

= FOUR_MMIO3

23:21 0x0

DMA_MODE:

= IO2MEM_NO_FC0

= IO2MEM_FC1

= MEM2IO_NO_FC2

= MEM2IO_FC3

= MEM2MEM4

= RSVD5

= FIXED_PAT6

20:16 0x0

REQ_SEL:

= I2C80

= I2C101

= UARTG2

= UARTC3

= QSPI05

= QSPI16

= UARTA8

= UARTB9

= UARTF12

= UARTH13

= SPI115

= SPI216

= SPI317

= UARTD19

= UARTE20

= I2C21

= I2C222

= I2C323

= I2C524

= I2C426

= I2C727

= I2C630

= I2C931

= RSVD29

15 0x1

IRQ_MASK:

= DISABLE0

= ENABLE1

13:10 0x1

WEIGHT

GPCDMA_CHANNEL_CH23_STA_0

Offset: 0x180004

Read/Write: See table below

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Parity Protection: N

SCR Protection: SCR_CH23_0

Reset: 0x00000000 (0b00x0,0000,0x00,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit R/W Reset Description

31 RO 0x0

BSY:

= WAIT0

= ACTIVE1

30 RW 0x0

ISE_EOC:

= NO_INTR0

= INTR1

28 RO 0x0

PING_PONG_STA:

= PING_INTR_STA0

= PONG_INTR_STA1

27 RO 0x0

DMA_ACTIVITY:

= IDLE0

= BUSY1

26 RO 0x0

CHANNEL_PAUSE:

= RESUME0

= PAUSE1

25 RO 0x0

CHANNEL_RX:

= NOT_ACTIVE0

= ACTIVE1

24 RO 0x0

CHANNEL_TX:

= NOT_ACTIVE0

= ACTIVE1

23 RO 0x0

IRQ_INTR_STA:

= DISABLE0

= ENABLE1

21 RO 0x0

TRIG_STA:

= NOT_ACTIVE0

= ACTIVE1

20 RO 0x0

INTR_STA:

= NOT_ACTIVE0

= ACTIVE1

GPCDMA_CHANNEL_CH23_CSRE_0

Offset: 0x180008

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH23_0

Reset: 0x00000000 (0b0xxx,xxxx,xxxx,0000,00xx,xxxx,xxxx,xxxx)

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Bit Reset Description

31 0x0

DMA_ACTIVITY:

= RESUME0

= PAUSE1

19:14 0x0

TRIG_SEL:

= SMP_241

= SMP_252

= SMP_263

= SMP_274

= XRQ_A5

= XRQ_B6

= TMR17

= TMR28

= CH09

= CH110

= CH211

= CH312

= CH413

= CH514

= CH615

= CH716

= CH817

= CH918

= CH1019

= CH1120

= CH1221

= CH1322

= CH1423

= CH1524

= CH1625

= CH1726

= CH1827

= CH1928

= CH2029

= CH2130

= CH2231

= CH2332

= CH2433

= CH2534

= CH2635

= CH2736

= CH2837

= CH2938

= CH3039

= CH3140

= RSVD0

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GPCDMA_CHANNEL_CH23_SRC_PTR_0

Offset: 0x18000c

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH23_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

SRC_PTR

GPCDMA_CHANNEL_CH23_DST_PTR_0

Offset: 0x180010

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH23_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

DST_PTR

GPCDMA_CHANNEL_CH23_HI_ADR_PTR_0

Offset: 0x180014

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH23_0

Reset: 0x00000000 (0bxxxx,xxxx,0000,0000,xxxx,xxxx,0000,0000)

Bit Reset Description

23:16 0x0

HI_DST_PTR

7:0 0x0

HI_SRC_PTR

GPCDMA_CHANNEL_CH23_MC_SEQ_0

Offset: 0x180018

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH23_0

Reset: 0x03800000 (0b0000,0011,1000,0000,0000,0000,0000,0000)

Bit Reset Description

31 0x0

MC_DATA_SWAP:

= DISABLE0

= ENABLE1

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Bit Reset Description

30:25 0x1

MC_REQ_CNT

24:23 0x3

MC_BURST:

= DMA_BURST_2WORDS0

= DMA_BURST_16WORDS3

22:20 0x0

MC_ADDR_WRAP1:

= NO_WRAP0

= WRAP_0N_32WORDS1

= WRAP_ON_64WORDS2

= WRAP_ON_128WORDS3

= WRAP_ON_256WORDS4

= WRAP_ON_512WORDS5

= WRAP_ON_1024WORDS6

= WRAP_ON_2048WORDS7

19:17 0x0

MC_ADDR_WRAP0:

= NO_WRAP0

= WRAP_0N_32WORDS1

= WRAP_ON_64WORDS2

= WRAP_ON_128WORDS3

= WRAP_ON_256WORDS4

= WRAP_ON_512WORDS5

= WRAP_ON_1024WORDS6

= WRAP_ON_2048WORDS7

16 0x0

MC_AXIID

15:14 0x0

MC_PROT

13:7 0x0

STREAMID1

6:0 0x0

STREAMID0

GPCDMA_CHANNEL_CH23_MMIO_SEQ_0

Offset: 0x18001c

Read/Write: See table below

Parity Protection: N

SCR Protection: SCR_CH23_0

Reset: 0x2381007f (0b0010,0011,1000,0001,xxxx,xxx0,0111,1111)

Bit R/W Reset Description

31 RW 0x0

DBL_BUF:

= DISABLE0

= ENABLE1

30:28 RW 0x2

MMIO_BUS_WIDTH:

= BUS_WIDTH_80

= BUS_WIDTH_161

= BUS_WIDTH_322

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Bit R/W Reset Description

27 RW 0x0

MMIO_DATA_SWAP:

= DISABLE0

= ENABLE1

26:23 RW 0x7

MMIO_BURST:

= DMA_BURST_1WORDS0

= DMA_BURST_2WORDS1

= DMA_BURST_4WORDS3

= DMA_BURST_8WORDS7

= DMA_BURST_16WORDS15

22:19 RO 0x0

MMIO_MASTER_ID:

= RSVD0

= CCPLEX1

= CCPLEX_DPMU2

= BPMP3

= SPE4

= SCE5

= DMA_PER6

= TSECA7

= TSECB8

= JTAGM9

= CSITE10

= APE11

18:16 RW 0x1

MMIO_ADDR_WRAP:

= NO_WRAP0

= WRAP_0N_1WORDS1

= WRAP_ON_2WORDS2

= WRAP_ON_4WORDS3

= WRAP_ON_8WORDS4

= WRAP_ON_16WORDS5

= WRAP_ON_32WORDS6

= WRAP_ON_64WORDS7

8:7 RW 0x0

MMIO_PROT

6:0 RO 0x7f

MMIO_CHANNEL_SECURITY

GPCDMA_CHANNEL_CH23_BCOUNT_0

Offset: 0x180020

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH23_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

BCOUNT

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GPCDMA_CHANNEL_CH23_DMA_BYTE_TRA_0

Offset: 0x180024

Read/Write: RO

Parity Protection: N

SCR Protection: SCR_CH23_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

TRANSFER_COUNT

GPCDMA_CHANNEL_CH23_DMA_BYTE_STA_0

Offset: 0x180028

Read/Write: RO

Parity Protection: N

SCR Protection: SCR_CH23_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

DMA_COUNT

GPCDMA_CHANNEL_CH23_ERR_STA_0

Offset: 0x180030

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH23_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

ERROR_STATUS

GPCDMA_CHANNEL_CH23_FIXED_PAT_0

Offset: 0x180034

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH23_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

FIXED_PATTERN

GPCDMA_CHANNEL_CH23_TZ_0

Offset: 0x180038

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Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_TZ_0

Reset: 0x00000003 (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xx11)

Bit Reset Description

1 0x1

MC_PROT_1

0 0x1

MMIO_PROT_1

GPCDMA_CHANNEL_CH24_CSR_0

Offset: 0x190000

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH24_0

Reset: 0x08008400 (0b00xx,1x00,0000,0000,1x00,01xx,xxxx,xxxx)

Bit Reset Description

31 0x0

ENB:

= DISABLE0

= ENABLE1

30 0x0

IE_EOC:

= DISABLE0

= ENABLE1

27 0x1

ONCE:

= CYCLIC_MODE0

= SINGLE_BLOCK1

25:24 0x0

FC_MODE:

= NO_MMIO0

= ONE_MMIO1

= TWO_MMIO2

= FOUR_MMIO3

23:21 0x0

DMA_MODE:

= IO2MEM_NO_FC0

= IO2MEM_FC1

= MEM2IO_NO_FC2

= MEM2IO_FC3

= MEM2MEM4

= RSVD5

= FIXED_PAT6

20:16

0x0

REQ_SEL:

= I2C80

= I2C101

= UARTG2

= UARTC3

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Bit Reset Description

= QSPI05

= QSPI16

= UARTA8

= UARTB9

= UARTF12

= UARTH13

= SPI115

= SPI216

= SPI317

= UARTD19

= UARTE20

= I2C21

= I2C222

= I2C323

= I2C524

= I2C426

= I2C727

= I2C630

= I2C931

= RSVD29

15 0x1

IRQ_MASK:

= DISABLE0

= ENABLE1

13:10 0x1

WEIGHT

GPCDMA_CHANNEL_CH24_STA_0

Offset: 0x190004

Read/Write: See table below

Parity Protection: N

SCR Protection: SCR_CH24_0

Reset: 0x00000000 (0b00x0,0000,0x00,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit R/W Reset Description

31 RO 0x0

BSY:

= WAIT0

= ACTIVE1

30 RW 0x0

ISE_EOC:

= NO_INTR0

= INTR1

28 RO 0x0

PING_PONG_STA:

= PING_INTR_STA0

= PONG_INTR_STA1

0x0

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Bit R/W Reset Description

DMA_ACTIVITY:

= IDLE0

= BUSY1

26 RO 0x0

CHANNEL_PAUSE:

= RESUME0

= PAUSE1

25 RO 0x0

CHANNEL_RX:

= NOT_ACTIVE0

= ACTIVE1

24 RO 0x0

CHANNEL_TX:

= NOT_ACTIVE0

= ACTIVE1

23 RO 0x0

IRQ_INTR_STA:

= DISABLE0

= ENABLE1

21 RO 0x0

TRIG_STA:

= NOT_ACTIVE0

= ACTIVE1

20 RO 0x0

INTR_STA:

= NOT_ACTIVE0

= ACTIVE1

GPCDMA_CHANNEL_CH24_CSRE_0

Offset: 0x190008

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH24_0

Reset: 0x00000000 (0b0xxx,xxxx,xxxx,0000,00xx,xxxx,xxxx,xxxx)

Bit Reset Description

31 0x0

DMA_ACTIVITY:

= RESUME0

= PAUSE1

19:14

0x0

TRIG_SEL:

= SMP_241

= SMP_252

= SMP_263

= SMP_274

= XRQ_A5

= XRQ_B6

= TMR17

= TMR28

= CH09

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Bit Reset Description

= CH110

= CH211

= CH312

= CH413

= CH514

= CH615

= CH716

= CH817

= CH918

= CH1019

= CH1120

= CH1221

= CH1322

= CH1423

= CH1524

= CH1625

= CH1726

= CH1827

= CH1928

= CH2029

= CH2130

= CH2231

= CH2332

= CH2433

= CH2534

= CH2635

= CH2736

= CH2837

= CH2938

= CH3039

= CH3140

= RSVD0

GPCDMA_CHANNEL_CH24_SRC_PTR_0

Offset: 0x19000c

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH24_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

SRC_PTR

GPCDMA_CHANNEL_CH24_DST_PTR_0

Offset: 0x190010

Read/Write: R/W

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Parity Protection: N

SCR Protection: SCR_CH24_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

DST_PTR

GPCDMA_CHANNEL_CH24_HI_ADR_PTR_0

Offset: 0x190014

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH24_0

Reset: 0x00000000 (0bxxxx,xxxx,0000,0000,xxxx,xxxx,0000,0000)

Bit Reset Description

23:16 0x0

HI_DST_PTR

7:0 0x0

HI_SRC_PTR

GPCDMA_CHANNEL_CH24_MC_SEQ_0

Offset: 0x190018

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH24_0

Reset: 0x03800000 (0b0000,0011,1000,0000,0000,0000,0000,0000)

Bit Reset Description

31 0x0

MC_DATA_SWAP:

= DISABLE0

= ENABLE1

30:25 0x1

MC_REQ_CNT

24:23 0x3

MC_BURST:

= DMA_BURST_2WORDS0

= DMA_BURST_16WORDS3

22:20 0x0

MC_ADDR_WRAP1:

= NO_WRAP0

= WRAP_0N_32WORDS1

= WRAP_ON_64WORDS2

= WRAP_ON_128WORDS3

= WRAP_ON_256WORDS4

= WRAP_ON_512WORDS5

= WRAP_ON_1024WORDS6

= WRAP_ON_2048WORDS7

19:17

0x0

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Bit Reset Description

MC_ADDR_WRAP0:

= NO_WRAP0

= WRAP_0N_32WORDS1

= WRAP_ON_64WORDS2

= WRAP_ON_128WORDS3

= WRAP_ON_256WORDS4

= WRAP_ON_512WORDS5

= WRAP_ON_1024WORDS6

= WRAP_ON_2048WORDS7

16 0x0

MC_AXIID

15:14 0x0

MC_PROT

13:7 0x0

STREAMID1

6:0 0x0

STREAMID0

GPCDMA_CHANNEL_CH24_MMIO_SEQ_0

Offset: 0x19001c

Read/Write: See table below

Parity Protection: N

SCR Protection: SCR_CH24_0

Reset: 0x2381007f (0b0010,0011,1000,0001,xxxx,xxx0,0111,1111)

Bit R/W Reset Description

31 RW 0x0

DBL_BUF:

= DISABLE0

= ENABLE1

30:28 RW 0x2

MMIO_BUS_WIDTH:

= BUS_WIDTH_80

= BUS_WIDTH_161

= BUS_WIDTH_322

27 RW 0x0

MMIO_DATA_SWAP:

= DISABLE0

= ENABLE1

26:23 RW 0x7

MMIO_BURST:

= DMA_BURST_1WORDS0

= DMA_BURST_2WORDS1

= DMA_BURST_4WORDS3

= DMA_BURST_8WORDS7

= DMA_BURST_16WORDS15

22:19

0x0

MMIO_MASTER_ID:

= RSVD0

= CCPLEX1

= CCPLEX_DPMU2

= BPMP3

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Bit R/W Reset Description

= SPE4

= SCE5

= DMA_PER6

= TSECA7

= TSECB8

= JTAGM9

= CSITE10

= APE11

18:16 RW 0x1

MMIO_ADDR_WRAP:

= NO_WRAP0

= WRAP_0N_1WORDS1

= WRAP_ON_2WORDS2

= WRAP_ON_4WORDS3

= WRAP_ON_8WORDS4

= WRAP_ON_16WORDS5

= WRAP_ON_32WORDS6

= WRAP_ON_64WORDS7

8:7 RW 0x0

MMIO_PROT

6:0 RO 0x7f

MMIO_CHANNEL_SECURITY

GPCDMA_CHANNEL_CH24_BCOUNT_0

Offset: 0x190020

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH24_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

BCOUNT

GPCDMA_CHANNEL_CH24_DMA_BYTE_TRA_0

Offset: 0x190024

Read/Write: RO

Parity Protection: N

SCR Protection: SCR_CH24_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

TRANSFER_COUNT

GPCDMA_CHANNEL_CH24_DMA_BYTE_STA_0

Offset: 0x190028

Read/Write: RO

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Parity Protection: N

SCR Protection: SCR_CH24_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

DMA_COUNT

GPCDMA_CHANNEL_CH24_ERR_STA_0

Offset: 0x190030

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH24_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

ERROR_STATUS

GPCDMA_CHANNEL_CH24_FIXED_PAT_0

Offset: 0x190034

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH24_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

FIXED_PATTERN

GPCDMA_CHANNEL_CH24_TZ_0

Offset: 0x190038

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_TZ_0

Reset: 0x00000003 (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xx11)

Bit Reset Description

1 0x1

MC_PROT_1

0 0x1

MMIO_PROT_1

GPCDMA_CHANNEL_CH25_CSR_0

Offset: 0x1a0000

Read/Write: R/W

Parity Protection: N

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SCR Protection: SCR_CH25_0

Reset: 0x08008400 (0b00xx,1x00,0000,0000,1x00,01xx,xxxx,xxxx)

Bit Reset Description

31 0x0

ENB:

= DISABLE0

= ENABLE1

30 0x0

IE_EOC:

= DISABLE0

= ENABLE1

27 0x1

ONCE:

= CYCLIC_MODE0

= SINGLE_BLOCK1

25:24 0x0

FC_MODE:

= NO_MMIO0

= ONE_MMIO1

= TWO_MMIO2

= FOUR_MMIO3

23:21 0x0

DMA_MODE:

= IO2MEM_NO_FC0

= IO2MEM_FC1

= MEM2IO_NO_FC2

= MEM2IO_FC3

= MEM2MEM4

= RSVD5

= FIXED_PAT6

20:16

0x0

REQ_SEL:

= I2C80

= I2C101

= UARTG2

= UARTC3

= QSPI05

= QSPI16

= UARTA8

= UARTB9

= UARTF12

= UARTH13

= SPI115

= SPI216

= SPI317

= UARTD19

= UARTE20

= I2C21

= I2C222

= I2C323

= I2C524

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Bit Reset Description

= I2C426

= I2C727

= I2C630

= I2C931

= RSVD29

15 0x1

IRQ_MASK:

= DISABLE0

= ENABLE1

13:10 0x1

WEIGHT

GPCDMA_CHANNEL_CH25_STA_0

Offset: 0x1a0004

Read/Write: See table below

Parity Protection: N

SCR Protection: SCR_CH25_0

Reset: 0x00000000 (0b00x0,0000,0x00,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit R/W Reset Description

31 RO 0x0

BSY:

= WAIT0

= ACTIVE1

30 RW 0x0

ISE_EOC:

= NO_INTR0

= INTR1

28 RO 0x0

PING_PONG_STA:

= PING_INTR_STA0

= PONG_INTR_STA1

27 RO 0x0

DMA_ACTIVITY:

= IDLE0

= BUSY1

26 RO 0x0

CHANNEL_PAUSE:

= RESUME0

= PAUSE1

25 RO 0x0

CHANNEL_RX:

= NOT_ACTIVE0

= ACTIVE1

24 RO 0x0

CHANNEL_TX:

= NOT_ACTIVE0

= ACTIVE1

23 RO 0x0

IRQ_INTR_STA:

= DISABLE0

= ENABLE1

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Bit R/W Reset Description

21 RO 0x0

TRIG_STA:

= NOT_ACTIVE0

= ACTIVE1

20 RO 0x0

INTR_STA:

= NOT_ACTIVE0

= ACTIVE1

GPCDMA_CHANNEL_CH25_CSRE_0

Offset: 0x1a0008

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH25_0

Reset: 0x00000000 (0b0xxx,xxxx,xxxx,0000,00xx,xxxx,xxxx,xxxx)

Bit Reset Description

31 0x0

DMA_ACTIVITY:

= RESUME0

= PAUSE1

19:14

0x0

TRIG_SEL:

= SMP_241

= SMP_252

= SMP_263

= SMP_274

= XRQ_A5

= XRQ_B6

= TMR17

= TMR28

= CH09

= CH110

= CH211

= CH312

= CH413

= CH514

= CH615

= CH716

= CH817

= CH918

= CH1019

= CH1120

= CH1221

= CH1322

= CH1423

= CH1524

= CH1625

= CH1726

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Bit Reset Description

= CH1827

= CH1928

= CH2029

= CH2130

= CH2231

= CH2332

= CH2433

= CH2534

= CH2635

= CH2736

= CH2837

= CH2938

= CH3039

= CH3140

= RSVD0

GPCDMA_CHANNEL_CH25_SRC_PTR_0

Offset: 0x1a000c

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH25_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

SRC_PTR

GPCDMA_CHANNEL_CH25_DST_PTR_0

Offset: 0x1a0010

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH25_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

DST_PTR

GPCDMA_CHANNEL_CH25_HI_ADR_PTR_0

Offset: 0x1a0014

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH25_0

Reset: 0x00000000 (0bxxxx,xxxx,0000,0000,xxxx,xxxx,0000,0000)

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Bit Reset Description

23:16 0x0

HI_DST_PTR

7:0 0x0

HI_SRC_PTR

GPCDMA_CHANNEL_CH25_MC_SEQ_0

Offset: 0x1a0018

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH25_0

Reset: 0x03800000 (0b0000,0011,1000,0000,0000,0000,0000,0000)

Bit Reset Description

31 0x0

MC_DATA_SWAP:

= DISABLE0

= ENABLE1

30:25 0x1

MC_REQ_CNT

24:23 0x3

MC_BURST:

= DMA_BURST_2WORDS0

= DMA_BURST_16WORDS3

22:20 0x0

MC_ADDR_WRAP1:

= NO_WRAP0

= WRAP_0N_32WORDS1

= WRAP_ON_64WORDS2

= WRAP_ON_128WORDS3

= WRAP_ON_256WORDS4

= WRAP_ON_512WORDS5

= WRAP_ON_1024WORDS6

= WRAP_ON_2048WORDS7

19:17 0x0

MC_ADDR_WRAP0:

= NO_WRAP0

= WRAP_0N_32WORDS1

= WRAP_ON_64WORDS2

= WRAP_ON_128WORDS3

= WRAP_ON_256WORDS4

= WRAP_ON_512WORDS5

= WRAP_ON_1024WORDS6

= WRAP_ON_2048WORDS7

16 0x0

MC_AXIID

15:14 0x0

MC_PROT

13:7 0x0

STREAMID1

6:0 0x0

STREAMID0

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GPCDMA_CHANNEL_CH25_MMIO_SEQ_0

Offset: 0x1a001c

Read/Write: See table below

Parity Protection: N

SCR Protection: SCR_CH25_0

Reset: 0x2381007f (0b0010,0011,1000,0001,xxxx,xxx0,0111,1111)

Bit R/W Reset Description

31 RW 0x0

DBL_BUF:

= DISABLE0

= ENABLE1

30:28 RW 0x2

MMIO_BUS_WIDTH:

= BUS_WIDTH_80

= BUS_WIDTH_161

= BUS_WIDTH_322

27 RW 0x0

MMIO_DATA_SWAP:

= DISABLE0

= ENABLE1

26:23 RW 0x7

MMIO_BURST:

= DMA_BURST_1WORDS0

= DMA_BURST_2WORDS1

= DMA_BURST_4WORDS3

= DMA_BURST_8WORDS7

= DMA_BURST_16WORDS15

22:19 RO 0x0

MMIO_MASTER_ID:

= RSVD0

= CCPLEX1

= CCPLEX_DPMU2

= BPMP3

= SPE4

= SCE5

= DMA_PER6

= TSECA7

= TSECB8

= JTAGM9

= CSITE10

= APE11

18:16 RW 0x1

MMIO_ADDR_WRAP:

= NO_WRAP0

= WRAP_0N_1WORDS1

= WRAP_ON_2WORDS2

= WRAP_ON_4WORDS3

= WRAP_ON_8WORDS4

= WRAP_ON_16WORDS5

= WRAP_ON_32WORDS6

= WRAP_ON_64WORDS7

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Bit R/W Reset Description

8:7 RW 0x0

MMIO_PROT

6:0 RO 0x7f

MMIO_CHANNEL_SECURITY

GPCDMA_CHANNEL_CH25_BCOUNT_0

Offset: 0x1a0020

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH25_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

BCOUNT

GPCDMA_CHANNEL_CH25_DMA_BYTE_TRA_0

Offset: 0x1a0024

Read/Write: RO

Parity Protection: N

SCR Protection: SCR_CH25_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

TRANSFER_COUNT

GPCDMA_CHANNEL_CH25_DMA_BYTE_STA_0

Offset: 0x1a0028

Read/Write: RO

Parity Protection: N

SCR Protection: SCR_CH25_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

DMA_COUNT

GPCDMA_CHANNEL_CH25_ERR_STA_0

Offset: 0x1a0030

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH25_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

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Bit Reset Description

31:0 0x0

ERROR_STATUS

GPCDMA_CHANNEL_CH25_FIXED_PAT_0

Offset: 0x1a0034

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH25_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

FIXED_PATTERN

GPCDMA_CHANNEL_CH25_TZ_0

Offset: 0x1a0038

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_TZ_0

Reset: 0x00000003 (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xx11)

Bit Reset Description

1 0x1

MC_PROT_1

0 0x1

MMIO_PROT_1

GPCDMA_CHANNEL_CH26_CSR_0

Offset: 0x1b0000

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH26_0

Reset: 0x08008400 (0b00xx,1x00,0000,0000,1x00,01xx,xxxx,xxxx)

Bit Reset Description

31 0x0

ENB:

= DISABLE0

= ENABLE1

30 0x0

IE_EOC:

= DISABLE0

= ENABLE1

27 0x1

ONCE:

= CYCLIC_MODE0

= SINGLE_BLOCK1

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Bit Reset Description

25:24 0x0

FC_MODE:

= NO_MMIO0

= ONE_MMIO1

= TWO_MMIO2

= FOUR_MMIO3

23:21 0x0

DMA_MODE:

= IO2MEM_NO_FC0

= IO2MEM_FC1

= MEM2IO_NO_FC2

= MEM2IO_FC3

= MEM2MEM4

= RSVD5

= FIXED_PAT6

20:16 0x0

REQ_SEL:

= I2C80

= I2C101

= UARTG2

= UARTC3

= QSPI05

= QSPI16

= UARTA8

= UARTB9

= UARTF12

= UARTH13

= SPI115

= SPI216

= SPI317

= UARTD19

= UARTE20

= I2C21

= I2C222

= I2C323

= I2C524

= I2C426

= I2C727

= I2C630

= I2C931

= RSVD29

15 0x1

IRQ_MASK:

= DISABLE0

= ENABLE1

13:10 0x1

WEIGHT

GPCDMA_CHANNEL_CH26_STA_0

Offset: 0x1b0004

Read/Write: See table below

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Parity Protection: N

SCR Protection: SCR_CH26_0

Reset: 0x00000000 (0b00x0,0000,0x00,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit R/W Reset Description

31 RO 0x0

BSY:

= WAIT0

= ACTIVE1

30 RW 0x0

ISE_EOC:

= NO_INTR0

= INTR1

28 RO 0x0

PING_PONG_STA:

= PING_INTR_STA0

= PONG_INTR_STA1

27 RO 0x0

DMA_ACTIVITY:

= IDLE0

= BUSY1

26 RO 0x0

CHANNEL_PAUSE:

= RESUME0

= PAUSE1

25 RO 0x0

CHANNEL_RX:

= NOT_ACTIVE0

= ACTIVE1

24 RO 0x0

CHANNEL_TX:

= NOT_ACTIVE0

= ACTIVE1

23 RO 0x0

IRQ_INTR_STA:

= DISABLE0

= ENABLE1

21 RO 0x0

TRIG_STA:

= NOT_ACTIVE0

= ACTIVE1

20 RO 0x0

INTR_STA:

= NOT_ACTIVE0

= ACTIVE1

GPCDMA_CHANNEL_CH26_CSRE_0

Offset: 0x1b0008

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH26_0

Reset: 0x00000000 (0b0xxx,xxxx,xxxx,0000,00xx,xxxx,xxxx,xxxx)

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Bit Reset Description

31 0x0

DMA_ACTIVITY:

= RESUME0

= PAUSE1

19:14 0x0

TRIG_SEL:

= SMP_241

= SMP_252

= SMP_263

= SMP_274

= XRQ_A5

= XRQ_B6

= TMR17

= TMR28

= CH09

= CH110

= CH211

= CH312

= CH413

= CH514

= CH615

= CH716

= CH817

= CH918

= CH1019

= CH1120

= CH1221

= CH1322

= CH1423

= CH1524

= CH1625

= CH1726

= CH1827

= CH1928

= CH2029

= CH2130

= CH2231

= CH2332

= CH2433

= CH2534

= CH2635

= CH2736

= CH2837

= CH2938

= CH3039

= CH3140

= RSVD0

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GPCDMA_CHANNEL_CH26_SRC_PTR_0

Offset: 0x1b000c

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH26_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

SRC_PTR

GPCDMA_CHANNEL_CH26_DST_PTR_0

Offset: 0x1b0010

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH26_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

DST_PTR

GPCDMA_CHANNEL_CH26_HI_ADR_PTR_0

Offset: 0x1b0014

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH26_0

Reset: 0x00000000 (0bxxxx,xxxx,0000,0000,xxxx,xxxx,0000,0000)

Bit Reset Description

23:16 0x0

HI_DST_PTR

7:0 0x0

HI_SRC_PTR

GPCDMA_CHANNEL_CH26_MC_SEQ_0

Offset: 0x1b0018

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH26_0

Reset: 0x03800000 (0b0000,0011,1000,0000,0000,0000,0000,0000)

Bit Reset Description

31 0x0

MC_DATA_SWAP:

= DISABLE0

= ENABLE1

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Bit Reset Description

30:25 0x1

MC_REQ_CNT

24:23 0x3

MC_BURST:

= DMA_BURST_2WORDS0

= DMA_BURST_16WORDS3

22:20 0x0

MC_ADDR_WRAP1:

= NO_WRAP0

= WRAP_0N_32WORDS1

= WRAP_ON_64WORDS2

= WRAP_ON_128WORDS3

= WRAP_ON_256WORDS4

= WRAP_ON_512WORDS5

= WRAP_ON_1024WORDS6

= WRAP_ON_2048WORDS7

19:17 0x0

MC_ADDR_WRAP0:

= NO_WRAP0

= WRAP_0N_32WORDS1

= WRAP_ON_64WORDS2

= WRAP_ON_128WORDS3

= WRAP_ON_256WORDS4

= WRAP_ON_512WORDS5

= WRAP_ON_1024WORDS6

= WRAP_ON_2048WORDS7

16 0x0

MC_AXIID

15:14 0x0

MC_PROT

13:7 0x0

STREAMID1

6:0 0x0

STREAMID0

GPCDMA_CHANNEL_CH26_MMIO_SEQ_0

Offset: 0x1b001c

Read/Write: See table below

Parity Protection: N

SCR Protection: SCR_CH26_0

Reset: 0x2381007f (0b0010,0011,1000,0001,xxxx,xxx0,0111,1111)

Bit R/W Reset Description

31 RW 0x0

DBL_BUF:

= DISABLE0

= ENABLE1

30:28 RW 0x2

MMIO_BUS_WIDTH:

= BUS_WIDTH_80

= BUS_WIDTH_161

= BUS_WIDTH_322

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Bit R/W Reset Description

27 RW 0x0

MMIO_DATA_SWAP:

= DISABLE0

= ENABLE1

26:23 RW 0x7

MMIO_BURST:

= DMA_BURST_1WORDS0

= DMA_BURST_2WORDS1

= DMA_BURST_4WORDS3

= DMA_BURST_8WORDS7

= DMA_BURST_16WORDS15

22:19 RO 0x0

MMIO_MASTER_ID:

= RSVD0

= CCPLEX1

= CCPLEX_DPMU2

= BPMP3

= SPE4

= SCE5

= DMA_PER6

= TSECA7

= TSECB8

= JTAGM9

= CSITE10

= APE11

18:16 RW 0x1

MMIO_ADDR_WRAP:

= NO_WRAP0

= WRAP_0N_1WORDS1

= WRAP_ON_2WORDS2

= WRAP_ON_4WORDS3

= WRAP_ON_8WORDS4

= WRAP_ON_16WORDS5

= WRAP_ON_32WORDS6

= WRAP_ON_64WORDS7

8:7 RW 0x0

MMIO_PROT

6:0 RO 0x7f

MMIO_CHANNEL_SECURITY

GPCDMA_CHANNEL_CH26_BCOUNT_0

Offset: 0x1b0020

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH26_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

BCOUNT

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GPCDMA_CHANNEL_CH26_DMA_BYTE_TRA_0

Offset: 0x1b0024

Read/Write: RO

Parity Protection: N

SCR Protection: SCR_CH26_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

TRANSFER_COUNT

GPCDMA_CHANNEL_CH26_DMA_BYTE_STA_0

Offset: 0x1b0028

Read/Write: RO

Parity Protection: N

SCR Protection: SCR_CH26_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

DMA_COUNT

GPCDMA_CHANNEL_CH26_ERR_STA_0

Offset: 0x1b0030

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH26_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

ERROR_STATUS

GPCDMA_CHANNEL_CH26_FIXED_PAT_0

Offset: 0x1b0034

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH26_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

FIXED_PATTERN

GPCDMA_CHANNEL_CH26_TZ_0

Offset: 0x1b0038

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Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_TZ_0

Reset: 0x00000003 (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xx11)

Bit Reset Description

1 0x1

MC_PROT_1

0 0x1

MMIO_PROT_1

GPCDMA_CHANNEL_CH27_CSR_0

Offset: 0x1c0000

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH27_0

Reset: 0x08008400 (0b00xx,1x00,0000,0000,1x00,01xx,xxxx,xxxx)

Bit Reset Description

31 0x0

ENB:

= DISABLE0

= ENABLE1

30 0x0

IE_EOC:

= DISABLE0

= ENABLE1

27 0x1

ONCE:

= CYCLIC_MODE0

= SINGLE_BLOCK1

25:24 0x0

FC_MODE:

= NO_MMIO0

= ONE_MMIO1

= TWO_MMIO2

= FOUR_MMIO3

23:21 0x0

DMA_MODE:

= IO2MEM_NO_FC0

= IO2MEM_FC1

= MEM2IO_NO_FC2

= MEM2IO_FC3

= MEM2MEM4

= RSVD5

= FIXED_PAT6

20:16

0x0

REQ_SEL:

= I2C80

= I2C101

= UARTG2

= UARTC3

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Bit Reset Description

= QSPI05

= QSPI16

= UARTA8

= UARTB9

= UARTF12

= UARTH13

= SPI115

= SPI216

= SPI317

= UARTD19

= UARTE20

= I2C21

= I2C222

= I2C323

= I2C524

= I2C426

= I2C727

= I2C630

= I2C931

= RSVD29

15 0x1

IRQ_MASK:

= DISABLE0

= ENABLE1

13:10 0x1

WEIGHT

GPCDMA_CHANNEL_CH27_STA_0

Offset: 0x1c0004

Read/Write: See table below

Parity Protection: N

SCR Protection: SCR_CH27_0

Reset: 0x00000000 (0b00x0,0000,0x00,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit R/W Reset Description

31 RO 0x0

BSY:

= WAIT0

= ACTIVE1

30 RW 0x0

ISE_EOC:

= NO_INTR0

= INTR1

28 RO 0x0

PING_PONG_STA:

= PING_INTR_STA0

= PONG_INTR_STA1

0x0

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Bit R/W Reset Description

DMA_ACTIVITY:

= IDLE0

= BUSY1

26 RO 0x0

CHANNEL_PAUSE:

= RESUME0

= PAUSE1

25 RO 0x0

CHANNEL_RX:

= NOT_ACTIVE0

= ACTIVE1

24 RO 0x0

CHANNEL_TX:

= NOT_ACTIVE0

= ACTIVE1

23 RO 0x0

IRQ_INTR_STA:

= DISABLE0

= ENABLE1

21 RO 0x0

TRIG_STA:

= NOT_ACTIVE0

= ACTIVE1

20 RO 0x0

INTR_STA:

= NOT_ACTIVE0

= ACTIVE1

GPCDMA_CHANNEL_CH27_CSRE_0

Offset: 0x1c0008

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH27_0

Reset: 0x00000000 (0b0xxx,xxxx,xxxx,0000,00xx,xxxx,xxxx,xxxx)

Bit Reset Description

31 0x0

DMA_ACTIVITY:

= RESUME0

= PAUSE1

19:14

0x0

TRIG_SEL:

= SMP_241

= SMP_252

= SMP_263

= SMP_274

= XRQ_A5

= XRQ_B6

= TMR17

= TMR28

= CH09

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Bit Reset Description

= CH110

= CH211

= CH312

= CH413

= CH514

= CH615

= CH716

= CH817

= CH918

= CH1019

= CH1120

= CH1221

= CH1322

= CH1423

= CH1524

= CH1625

= CH1726

= CH1827

= CH1928

= CH2029

= CH2130

= CH2231

= CH2332

= CH2433

= CH2534

= CH2635

= CH2736

= CH2837

= CH2938

= CH3039

= CH3140

= RSVD0

GPCDMA_CHANNEL_CH27_SRC_PTR_0

Offset: 0x1c000c

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH27_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

SRC_PTR

GPCDMA_CHANNEL_CH27_DST_PTR_0

Offset: 0x1c0010

Read/Write: R/W

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Parity Protection: N

SCR Protection: SCR_CH27_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

DST_PTR

GPCDMA_CHANNEL_CH27_HI_ADR_PTR_0

Offset: 0x1c0014

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH27_0

Reset: 0x00000000 (0bxxxx,xxxx,0000,0000,xxxx,xxxx,0000,0000)

Bit Reset Description

23:16 0x0

HI_DST_PTR

7:0 0x0

HI_SRC_PTR

GPCDMA_CHANNEL_CH27_MC_SEQ_0

Offset: 0x1c0018

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH27_0

Reset: 0x03800000 (0b0000,0011,1000,0000,0000,0000,0000,0000)

Bit Reset Description

31 0x0

MC_DATA_SWAP:

= DISABLE0

= ENABLE1

30:25 0x1

MC_REQ_CNT

24:23 0x3

MC_BURST:

= DMA_BURST_2WORDS0

= DMA_BURST_16WORDS3

22:20 0x0

MC_ADDR_WRAP1:

= NO_WRAP0

= WRAP_0N_32WORDS1

= WRAP_ON_64WORDS2

= WRAP_ON_128WORDS3

= WRAP_ON_256WORDS4

= WRAP_ON_512WORDS5

= WRAP_ON_1024WORDS6

= WRAP_ON_2048WORDS7

19:17

0x0

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Bit Reset Description

MC_ADDR_WRAP0:

= NO_WRAP0

= WRAP_0N_32WORDS1

= WRAP_ON_64WORDS2

= WRAP_ON_128WORDS3

= WRAP_ON_256WORDS4

= WRAP_ON_512WORDS5

= WRAP_ON_1024WORDS6

= WRAP_ON_2048WORDS7

16 0x0

MC_AXIID

15:14 0x0

MC_PROT

13:7 0x0

STREAMID1

6:0 0x0

STREAMID0

GPCDMA_CHANNEL_CH27_MMIO_SEQ_0

Offset: 0x1c001c

Read/Write: See table below

Parity Protection: N

SCR Protection: SCR_CH27_0

Reset: 0x2381007f (0b0010,0011,1000,0001,xxxx,xxx0,0111,1111)

Bit R/W Reset Description

31 RW 0x0

DBL_BUF:

= DISABLE0

= ENABLE1

30:28 RW 0x2

MMIO_BUS_WIDTH:

= BUS_WIDTH_80

= BUS_WIDTH_161

= BUS_WIDTH_322

27 RW 0x0

MMIO_DATA_SWAP:

= DISABLE0

= ENABLE1

26:23 RW 0x7

MMIO_BURST:

= DMA_BURST_1WORDS0

= DMA_BURST_2WORDS1

= DMA_BURST_4WORDS3

= DMA_BURST_8WORDS7

= DMA_BURST_16WORDS15

22:19

0x0

MMIO_MASTER_ID:

= RSVD0

= CCPLEX1

= CCPLEX_DPMU2

= BPMP3

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Bit R/W Reset Description

= SPE4

= SCE5

= DMA_PER6

= TSECA7

= TSECB8

= JTAGM9

= CSITE10

= APE11

18:16 RW 0x1

MMIO_ADDR_WRAP:

= NO_WRAP0

= WRAP_0N_1WORDS1

= WRAP_ON_2WORDS2

= WRAP_ON_4WORDS3

= WRAP_ON_8WORDS4

= WRAP_ON_16WORDS5

= WRAP_ON_32WORDS6

= WRAP_ON_64WORDS7

8:7 RW 0x0

MMIO_PROT

6:0 RO 0x7f

MMIO_CHANNEL_SECURITY

GPCDMA_CHANNEL_CH27_BCOUNT_0

Offset: 0x1c0020

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH27_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

BCOUNT

GPCDMA_CHANNEL_CH27_DMA_BYTE_TRA_0

Offset: 0x1c0024

Read/Write: RO

Parity Protection: N

SCR Protection: SCR_CH27_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

TRANSFER_COUNT

GPCDMA_CHANNEL_CH27_DMA_BYTE_STA_0

Offset: 0x1c0028

Read/Write: RO

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Parity Protection: N

SCR Protection: SCR_CH27_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

DMA_COUNT

GPCDMA_CHANNEL_CH27_ERR_STA_0

Offset: 0x1c0030

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH27_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

ERROR_STATUS

GPCDMA_CHANNEL_CH27_FIXED_PAT_0

Offset: 0x1c0034

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH27_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

FIXED_PATTERN

GPCDMA_CHANNEL_CH27_TZ_0

Offset: 0x1c0038

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_TZ_0

Reset: 0x00000003 (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xx11)

Bit Reset Description

1 0x1

MC_PROT_1

0 0x1

MMIO_PROT_1

GPCDMA_CHANNEL_CH28_CSR_0

Offset: 0x1d0000

Read/Write: R/W

Parity Protection: N

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SCR Protection: SCR_CH28_0

Reset: 0x08008400 (0b00xx,1x00,0000,0000,1x00,01xx,xxxx,xxxx)

Bit Reset Description

31 0x0

ENB:

= DISABLE0

= ENABLE1

30 0x0

IE_EOC:

= DISABLE0

= ENABLE1

27 0x1

ONCE:

= CYCLIC_MODE0

= SINGLE_BLOCK1

25:24 0x0

FC_MODE:

= NO_MMIO0

= ONE_MMIO1

= TWO_MMIO2

= FOUR_MMIO3

23:21 0x0

DMA_MODE:

= IO2MEM_NO_FC0

= IO2MEM_FC1

= MEM2IO_NO_FC2

= MEM2IO_FC3

= MEM2MEM4

= RSVD5

= FIXED_PAT6

20:16

0x0

REQ_SEL:

= I2C80

= I2C101

= UARTG2

= UARTC3

= QSPI05

= QSPI16

= UARTA8

= UARTB9

= UARTF12

= UARTH13

= SPI115

= SPI216

= SPI317

= UARTD19

= UARTE20

= I2C21

= I2C222

= I2C323

= I2C524

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Bit Reset Description

= I2C426

= I2C727

= I2C630

= I2C931

= RSVD29

15 0x1

IRQ_MASK:

= DISABLE0

= ENABLE1

13:10 0x1

WEIGHT

GPCDMA_CHANNEL_CH28_STA_0

Offset: 0x1d0004

Read/Write: See table below

Parity Protection: N

SCR Protection: SCR_CH28_0

Reset: 0x00000000 (0b00x0,0000,0x00,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit R/W Reset Description

31 RO 0x0

BSY:

= WAIT0

= ACTIVE1

30 RW 0x0

ISE_EOC:

= NO_INTR0

= INTR1

28 RO 0x0

PING_PONG_STA:

= PING_INTR_STA0

= PONG_INTR_STA1

27 RO 0x0

DMA_ACTIVITY:

= IDLE0

= BUSY1

26 RO 0x0

CHANNEL_PAUSE:

= RESUME0

= PAUSE1

25 RO 0x0

CHANNEL_RX:

= NOT_ACTIVE0

= ACTIVE1

24 RO 0x0

CHANNEL_TX:

= NOT_ACTIVE0

= ACTIVE1

23 RO 0x0

IRQ_INTR_STA:

= DISABLE0

= ENABLE1

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Bit R/W Reset Description

21 RO 0x0

TRIG_STA:

= NOT_ACTIVE0

= ACTIVE1

20 RO 0x0

INTR_STA:

= NOT_ACTIVE0

= ACTIVE1

GPCDMA_CHANNEL_CH28_CSRE_0

Offset: 0x1d0008

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH28_0

Reset: 0x00000000 (0b0xxx,xxxx,xxxx,0000,00xx,xxxx,xxxx,xxxx)

Bit Reset Description

31 0x0

DMA_ACTIVITY:

= RESUME0

= PAUSE1

19:14

0x0

TRIG_SEL:

= SMP_241

= SMP_252

= SMP_263

= SMP_274

= XRQ_A5

= XRQ_B6

= TMR17

= TMR28

= CH09

= CH110

= CH211

= CH312

= CH413

= CH514

= CH615

= CH716

= CH817

= CH918

= CH1019

= CH1120

= CH1221

= CH1322

= CH1423

= CH1524

= CH1625

= CH1726

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Bit Reset Description

= CH1827

= CH1928

= CH2029

= CH2130

= CH2231

= CH2332

= CH2433

= CH2534

= CH2635

= CH2736

= CH2837

= CH2938

= CH3039

= CH3140

= RSVD0

GPCDMA_CHANNEL_CH28_SRC_PTR_0

Offset: 0x1d000c

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH28_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

SRC_PTR

GPCDMA_CHANNEL_CH28_DST_PTR_0

Offset: 0x1d0010

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH28_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

DST_PTR

GPCDMA_CHANNEL_CH28_HI_ADR_PTR_0

Offset: 0x1d0014

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH28_0

Reset: 0x00000000 (0bxxxx,xxxx,0000,0000,xxxx,xxxx,0000,0000)

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Bit Reset Description

23:16 0x0

HI_DST_PTR

7:0 0x0

HI_SRC_PTR

GPCDMA_CHANNEL_CH28_MC_SEQ_0

Offset: 0x1d0018

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH28_0

Reset: 0x03800000 (0b0000,0011,1000,0000,0000,0000,0000,0000)

Bit Reset Description

31 0x0

MC_DATA_SWAP:

= DISABLE0

= ENABLE1

30:25 0x1

MC_REQ_CNT

24:23 0x3

MC_BURST:

= DMA_BURST_2WORDS0

= DMA_BURST_16WORDS3

22:20 0x0

MC_ADDR_WRAP1:

= NO_WRAP0

= WRAP_0N_32WORDS1

= WRAP_ON_64WORDS2

= WRAP_ON_128WORDS3

= WRAP_ON_256WORDS4

= WRAP_ON_512WORDS5

= WRAP_ON_1024WORDS6

= WRAP_ON_2048WORDS7

19:17 0x0

MC_ADDR_WRAP0:

= NO_WRAP0

= WRAP_0N_32WORDS1

= WRAP_ON_64WORDS2

= WRAP_ON_128WORDS3

= WRAP_ON_256WORDS4

= WRAP_ON_512WORDS5

= WRAP_ON_1024WORDS6

= WRAP_ON_2048WORDS7

16 0x0

MC_AXIID

15:14 0x0

MC_PROT

13:7 0x0

STREAMID1

6:0 0x0

STREAMID0

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GPCDMA_CHANNEL_CH28_MMIO_SEQ_0

Offset: 0x1d001c

Read/Write: See table below

Parity Protection: N

SCR Protection: SCR_CH28_0

Reset: 0x2381007f (0b0010,0011,1000,0001,xxxx,xxx0,0111,1111)

Bit R/W Reset Description

31 RW 0x0

DBL_BUF:

= DISABLE0

= ENABLE1

30:28 RW 0x2

MMIO_BUS_WIDTH:

= BUS_WIDTH_80

= BUS_WIDTH_161

= BUS_WIDTH_322

27 RW 0x0

MMIO_DATA_SWAP:

= DISABLE0

= ENABLE1

26:23 RW 0x7

MMIO_BURST:

= DMA_BURST_1WORDS0

= DMA_BURST_2WORDS1

= DMA_BURST_4WORDS3

= DMA_BURST_8WORDS7

= DMA_BURST_16WORDS15

22:19 RO 0x0

MMIO_MASTER_ID:

= RSVD0

= CCPLEX1

= CCPLEX_DPMU2

= BPMP3

= SPE4

= SCE5

= DMA_PER6

= TSECA7

= TSECB8

= JTAGM9

= CSITE10

= APE11

18:16 RW 0x1

MMIO_ADDR_WRAP:

= NO_WRAP0

= WRAP_0N_1WORDS1

= WRAP_ON_2WORDS2

= WRAP_ON_4WORDS3

= WRAP_ON_8WORDS4

= WRAP_ON_16WORDS5

= WRAP_ON_32WORDS6

= WRAP_ON_64WORDS7

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Bit R/W Reset Description

8:7 RW 0x0

MMIO_PROT

6:0 RO 0x7f

MMIO_CHANNEL_SECURITY

GPCDMA_CHANNEL_CH28_BCOUNT_0

Offset: 0x1d0020

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH28_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

BCOUNT

GPCDMA_CHANNEL_CH28_DMA_BYTE_TRA_0

Offset: 0x1d0024

Read/Write: RO

Parity Protection: N

SCR Protection: SCR_CH28_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

TRANSFER_COUNT

GPCDMA_CHANNEL_CH28_DMA_BYTE_STA_0

Offset: 0x1d0028

Read/Write: RO

Parity Protection: N

SCR Protection: SCR_CH28_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

DMA_COUNT

GPCDMA_CHANNEL_CH28_ERR_STA_0

Offset: 0x1d0030

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH28_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

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Bit Reset Description

31:0 0x0

ERROR_STATUS

GPCDMA_CHANNEL_CH28_FIXED_PAT_0

Offset: 0x1d0034

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH28_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

FIXED_PATTERN

GPCDMA_CHANNEL_CH28_TZ_0

Offset: 0x1d0038

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_TZ_0

Reset: 0x00000003 (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xx11)

Bit Reset Description

1 0x1

MC_PROT_1

0 0x1

MMIO_PROT_1

GPCDMA_CHANNEL_CH29_CSR_0

Offset: 0x1e0000

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH29_0

Reset: 0x08008400 (0b00xx,1x00,0000,0000,1x00,01xx,xxxx,xxxx)

Bit Reset Description

31 0x0

ENB:

= DISABLE0

= ENABLE1

30 0x0

IE_EOC:

= DISABLE0

= ENABLE1

27 0x1

ONCE:

= CYCLIC_MODE0

= SINGLE_BLOCK1

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Bit Reset Description

25:24 0x0

FC_MODE:

= NO_MMIO0

= ONE_MMIO1

= TWO_MMIO2

= FOUR_MMIO3

23:21 0x0

DMA_MODE:

= IO2MEM_NO_FC0

= IO2MEM_FC1

= MEM2IO_NO_FC2

= MEM2IO_FC3

= MEM2MEM4

= RSVD5

= FIXED_PAT6

20:16 0x0

REQ_SEL:

= I2C80

= I2C101

= UARTG2

= UARTC3

= QSPI05

= QSPI16

= UARTA8

= UARTB9

= UARTF12

= UARTH13

= SPI115

= SPI216

= SPI317

= UARTD19

= UARTE20

= I2C21

= I2C222

= I2C323

= I2C524

= I2C426

= I2C727

= I2C630

= I2C931

= RSVD29

15 0x1

IRQ_MASK:

= DISABLE0

= ENABLE1

13:10 0x1

WEIGHT

GPCDMA_CHANNEL_CH29_STA_0

Offset: 0x1e0004

Read/Write: See table below

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Parity Protection: N

SCR Protection: SCR_CH29_0

Reset: 0x00000000 (0b00x0,0000,0x00,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit R/W Reset Description

31 RO 0x0

BSY:

= WAIT0

= ACTIVE1

30 RW 0x0

ISE_EOC:

= NO_INTR0

= INTR1

28 RO 0x0

PING_PONG_STA:

= PING_INTR_STA0

= PONG_INTR_STA1

27 RO 0x0

DMA_ACTIVITY:

= IDLE0

= BUSY1

26 RO 0x0

CHANNEL_PAUSE:

= RESUME0

= PAUSE1

25 RO 0x0

CHANNEL_RX:

= NOT_ACTIVE0

= ACTIVE1

24 RO 0x0

CHANNEL_TX:

= NOT_ACTIVE0

= ACTIVE1

23 RO 0x0

IRQ_INTR_STA:

= DISABLE0

= ENABLE1

21 RO 0x0

TRIG_STA:

= NOT_ACTIVE0

= ACTIVE1

20 RO 0x0

INTR_STA:

= NOT_ACTIVE0

= ACTIVE1

GPCDMA_CHANNEL_CH29_CSRE_0

Offset: 0x1e0008

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH29_0

Reset: 0x00000000 (0b0xxx,xxxx,xxxx,0000,00xx,xxxx,xxxx,xxxx)

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Bit Reset Description

31 0x0

DMA_ACTIVITY:

= RESUME0

= PAUSE1

19:14 0x0

TRIG_SEL:

= SMP_241

= SMP_252

= SMP_263

= SMP_274

= XRQ_A5

= XRQ_B6

= TMR17

= TMR28

= CH09

= CH110

= CH211

= CH312

= CH413

= CH514

= CH615

= CH716

= CH817

= CH918

= CH1019

= CH1120

= CH1221

= CH1322

= CH1423

= CH1524

= CH1625

= CH1726

= CH1827

= CH1928

= CH2029

= CH2130

= CH2231

= CH2332

= CH2433

= CH2534

= CH2635

= CH2736

= CH2837

= CH2938

= CH3039

= CH3140

= RSVD0

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GPCDMA_CHANNEL_CH29_SRC_PTR_0

Offset: 0x1e000c

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH29_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

SRC_PTR

GPCDMA_CHANNEL_CH29_DST_PTR_0

Offset: 0x1e0010

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH29_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

DST_PTR

GPCDMA_CHANNEL_CH29_HI_ADR_PTR_0

Offset: 0x1e0014

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH29_0

Reset: 0x00000000 (0bxxxx,xxxx,0000,0000,xxxx,xxxx,0000,0000)

Bit Reset Description

23:16 0x0

HI_DST_PTR

7:0 0x0

HI_SRC_PTR

GPCDMA_CHANNEL_CH29_MC_SEQ_0

Offset: 0x1e0018

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH29_0

Reset: 0x03800000 (0b0000,0011,1000,0000,0000,0000,0000,0000)

Bit Reset Description

31 0x0

MC_DATA_SWAP:

= DISABLE0

= ENABLE1

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Bit Reset Description

30:25 0x1

MC_REQ_CNT

24:23 0x3

MC_BURST:

= DMA_BURST_2WORDS0

= DMA_BURST_16WORDS3

22:20 0x0

MC_ADDR_WRAP1:

= NO_WRAP0

= WRAP_0N_32WORDS1

= WRAP_ON_64WORDS2

= WRAP_ON_128WORDS3

= WRAP_ON_256WORDS4

= WRAP_ON_512WORDS5

= WRAP_ON_1024WORDS6

= WRAP_ON_2048WORDS7

19:17 0x0

MC_ADDR_WRAP0:

= NO_WRAP0

= WRAP_0N_32WORDS1

= WRAP_ON_64WORDS2

= WRAP_ON_128WORDS3

= WRAP_ON_256WORDS4

= WRAP_ON_512WORDS5

= WRAP_ON_1024WORDS6

= WRAP_ON_2048WORDS7

16 0x0

MC_AXIID

15:14 0x0

MC_PROT

13:7 0x0

STREAMID1

6:0 0x0

STREAMID0

GPCDMA_CHANNEL_CH29_MMIO_SEQ_0

Offset: 0x1e001c

Read/Write: See table below

Parity Protection: N

SCR Protection: SCR_CH29_0

Reset: 0x2381007f (0b0010,0011,1000,0001,xxxx,xxx0,0111,1111)

Bit R/W Reset Description

31 RW 0x0

DBL_BUF:

= DISABLE0

= ENABLE1

30:28 RW 0x2

MMIO_BUS_WIDTH:

= BUS_WIDTH_80

= BUS_WIDTH_161

= BUS_WIDTH_322

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Bit R/W Reset Description

27 RW 0x0

MMIO_DATA_SWAP:

= DISABLE0

= ENABLE1

26:23 RW 0x7

MMIO_BURST:

= DMA_BURST_1WORDS0

= DMA_BURST_2WORDS1

= DMA_BURST_4WORDS3

= DMA_BURST_8WORDS7

= DMA_BURST_16WORDS15

22:19 RO 0x0

MMIO_MASTER_ID:

= RSVD0

= CCPLEX1

= CCPLEX_DPMU2

= BPMP3

= SPE4

= SCE5

= DMA_PER6

= TSECA7

= TSECB8

= JTAGM9

= CSITE10

= APE11

18:16 RW 0x1

MMIO_ADDR_WRAP:

= NO_WRAP0

= WRAP_0N_1WORDS1

= WRAP_ON_2WORDS2

= WRAP_ON_4WORDS3

= WRAP_ON_8WORDS4

= WRAP_ON_16WORDS5

= WRAP_ON_32WORDS6

= WRAP_ON_64WORDS7

8:7 RW 0x0

MMIO_PROT

6:0 RO 0x7f

MMIO_CHANNEL_SECURITY

GPCDMA_CHANNEL_CH29_BCOUNT_0

Offset: 0x1e0020

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH29_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

BCOUNT

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GPCDMA_CHANNEL_CH29_DMA_BYTE_TRA_0

Offset: 0x1e0024

Read/Write: RO

Parity Protection: N

SCR Protection: SCR_CH29_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

TRANSFER_COUNT

GPCDMA_CHANNEL_CH29_DMA_BYTE_STA_0

Offset: 0x1e0028

Read/Write: RO

Parity Protection: N

SCR Protection: SCR_CH29_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

DMA_COUNT

GPCDMA_CHANNEL_CH29_ERR_STA_0

Offset: 0x1e0030

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH29_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

ERROR_STATUS

GPCDMA_CHANNEL_CH29_FIXED_PAT_0

Offset: 0x1e0034

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH29_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

FIXED_PATTERN

GPCDMA_CHANNEL_CH29_TZ_0

Offset: 0x1e0038

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Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_TZ_0

Reset: 0x00000003 (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xx11)

Bit Reset Description

1 0x1

MC_PROT_1

0 0x1

MMIO_PROT_1

GPCDMA_CHANNEL_CH30_CSR_0

Offset: 0x1f0000

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH30_0

Reset: 0x08008400 (0b00xx,1x00,0000,0000,1x00,01xx,xxxx,xxxx)

Bit Reset Description

31 0x0

ENB:

= DISABLE0

= ENABLE1

30 0x0

IE_EOC:

= DISABLE0

= ENABLE1

27 0x1

ONCE:

= CYCLIC_MODE0

= SINGLE_BLOCK1

25:24 0x0

FC_MODE:

= NO_MMIO0

= ONE_MMIO1

= TWO_MMIO2

= FOUR_MMIO3

23:21 0x0

DMA_MODE:

= IO2MEM_NO_FC0

= IO2MEM_FC1

= MEM2IO_NO_FC2

= MEM2IO_FC3

= MEM2MEM4

= RSVD5

= FIXED_PAT6

20:16

0x0

REQ_SEL:

= I2C80

= I2C101

= UARTG2

= UARTC3

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Bit Reset Description

= QSPI05

= QSPI16

= UARTA8

= UARTB9

= UARTF12

= UARTH13

= SPI115

= SPI216

= SPI317

= UARTD19

= UARTE20

= I2C21

= I2C222

= I2C323

= I2C524

= I2C426

= I2C727

= I2C630

= I2C931

= RSVD29

15 0x1

IRQ_MASK:

= DISABLE0

= ENABLE1

13:10 0x1

WEIGHT

GPCDMA_CHANNEL_CH30_STA_0

Offset: 0x1f0004

Read/Write: See table below

Parity Protection: N

SCR Protection: SCR_CH30_0

Reset: 0x00000000 (0b00x0,0000,0x00,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit R/W Reset Description

31 RO 0x0

BSY:

= WAIT0

= ACTIVE1

30 RW 0x0

ISE_EOC:

= NO_INTR0

= INTR1

28 RO 0x0

PING_PONG_STA:

= PING_INTR_STA0

= PONG_INTR_STA1

0x0

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Bit R/W Reset Description

DMA_ACTIVITY:

= IDLE0

= BUSY1

26 RO 0x0

CHANNEL_PAUSE:

= RESUME0

= PAUSE1

25 RO 0x0

CHANNEL_RX:

= NOT_ACTIVE0

= ACTIVE1

24 RO 0x0

CHANNEL_TX:

= NOT_ACTIVE0

= ACTIVE1

23 RO 0x0

IRQ_INTR_STA:

= DISABLE0

= ENABLE1

21 RO 0x0

TRIG_STA:

= NOT_ACTIVE0

= ACTIVE1

20 RO 0x0

INTR_STA:

= NOT_ACTIVE0

= ACTIVE1

GPCDMA_CHANNEL_CH30_CSRE_0

Offset: 0x1f0008

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH30_0

Reset: 0x00000000 (0b0xxx,xxxx,xxxx,0000,00xx,xxxx,xxxx,xxxx)

Bit Reset Description

31 0x0

DMA_ACTIVITY:

= RESUME0

= PAUSE1

19:14

0x0

TRIG_SEL:

= SMP_241

= SMP_252

= SMP_263

= SMP_274

= XRQ_A5

= XRQ_B6

= TMR17

= TMR28

= CH09

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Bit Reset Description

= CH110

= CH211

= CH312

= CH413

= CH514

= CH615

= CH716

= CH817

= CH918

= CH1019

= CH1120

= CH1221

= CH1322

= CH1423

= CH1524

= CH1625

= CH1726

= CH1827

= CH1928

= CH2029

= CH2130

= CH2231

= CH2332

= CH2433

= CH2534

= CH2635

= CH2736

= CH2837

= CH2938

= CH3039

= CH3140

= RSVD0

GPCDMA_CHANNEL_CH30_SRC_PTR_0

Offset: 0x1f000c

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH30_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

SRC_PTR

GPCDMA_CHANNEL_CH30_DST_PTR_0

Offset: 0x1f0010

Read/Write: R/W

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Parity Protection: N

SCR Protection: SCR_CH30_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

DST_PTR

GPCDMA_CHANNEL_CH30_HI_ADR_PTR_0

Offset: 0x1f0014

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH30_0

Reset: 0x00000000 (0bxxxx,xxxx,0000,0000,xxxx,xxxx,0000,0000)

Bit Reset Description

23:16 0x0

HI_DST_PTR

7:0 0x0

HI_SRC_PTR

GPCDMA_CHANNEL_CH30_MC_SEQ_0

Offset: 0x1f0018

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH30_0

Reset: 0x03800000 (0b0000,0011,1000,0000,0000,0000,0000,0000)

Bit Reset Description

31 0x0

MC_DATA_SWAP:

= DISABLE0

= ENABLE1

30:25 0x1

MC_REQ_CNT

24:23 0x3

MC_BURST:

= DMA_BURST_2WORDS0

= DMA_BURST_16WORDS3

22:20 0x0

MC_ADDR_WRAP1:

= NO_WRAP0

= WRAP_0N_32WORDS1

= WRAP_ON_64WORDS2

= WRAP_ON_128WORDS3

= WRAP_ON_256WORDS4

= WRAP_ON_512WORDS5

= WRAP_ON_1024WORDS6

= WRAP_ON_2048WORDS7

19:17

0x0

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Bit Reset Description

MC_ADDR_WRAP0:

= NO_WRAP0

= WRAP_0N_32WORDS1

= WRAP_ON_64WORDS2

= WRAP_ON_128WORDS3

= WRAP_ON_256WORDS4

= WRAP_ON_512WORDS5

= WRAP_ON_1024WORDS6

= WRAP_ON_2048WORDS7

16 0x0

MC_AXIID

15:14 0x0

MC_PROT

13:7 0x0

STREAMID1

6:0 0x0

STREAMID0

GPCDMA_CHANNEL_CH30_MMIO_SEQ_0

Offset: 0x1f001c

Read/Write: See table below

Parity Protection: N

SCR Protection: SCR_CH30_0

Reset: 0x2381007f (0b0010,0011,1000,0001,xxxx,xxx0,0111,1111)

Bit R/W Reset Description

31 RW 0x0

DBL_BUF:

= DISABLE0

= ENABLE1

30:28 RW 0x2

MMIO_BUS_WIDTH:

= BUS_WIDTH_80

= BUS_WIDTH_161

= BUS_WIDTH_322

27 RW 0x0

MMIO_DATA_SWAP:

= DISABLE0

= ENABLE1

26:23 RW 0x7

MMIO_BURST:

= DMA_BURST_1WORDS0

= DMA_BURST_2WORDS1

= DMA_BURST_4WORDS3

= DMA_BURST_8WORDS7

= DMA_BURST_16WORDS15

22:19

0x0

MMIO_MASTER_ID:

= RSVD0

= CCPLEX1

= CCPLEX_DPMU2

= BPMP3

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Bit R/W Reset Description

= SPE4

= SCE5

= DMA_PER6

= TSECA7

= TSECB8

= JTAGM9

= CSITE10

= APE11

18:16 RW 0x1

MMIO_ADDR_WRAP:

= NO_WRAP0

= WRAP_0N_1WORDS1

= WRAP_ON_2WORDS2

= WRAP_ON_4WORDS3

= WRAP_ON_8WORDS4

= WRAP_ON_16WORDS5

= WRAP_ON_32WORDS6

= WRAP_ON_64WORDS7

8:7 RW 0x0

MMIO_PROT

6:0 RO 0x7f

MMIO_CHANNEL_SECURITY

GPCDMA_CHANNEL_CH30_BCOUNT_0

Offset: 0x1f0020

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH30_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

BCOUNT

GPCDMA_CHANNEL_CH30_DMA_BYTE_TRA_0

Offset: 0x1f0024

Read/Write: RO

Parity Protection: N

SCR Protection: SCR_CH30_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

TRANSFER_COUNT

GPCDMA_CHANNEL_CH30_DMA_BYTE_STA_0

Offset: 0x1f0028

Read/Write: RO

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Parity Protection: N

SCR Protection: SCR_CH30_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

DMA_COUNT

GPCDMA_CHANNEL_CH30_ERR_STA_0

Offset: 0x1f0030

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH30_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

ERROR_STATUS

GPCDMA_CHANNEL_CH30_FIXED_PAT_0

Offset: 0x1f0034

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH30_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

FIXED_PATTERN

GPCDMA_CHANNEL_CH30_TZ_0

Offset: 0x1f0038

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_TZ_0

Reset: 0x00000003 (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xx11)

Bit Reset Description

1 0x1

MC_PROT_1

0 0x1

MMIO_PROT_1

GPCDMA_CHANNEL_CH31_CSR_0

Offset: 0x200000

Read/Write: R/W

Parity Protection: N

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SCR Protection: SCR_CH31_0

Reset: 0x08008400 (0b00xx,1x00,0000,0000,1x00,01xx,xxxx,xxxx)

Bit Reset Description

31 0x0

ENB:

= DISABLE0

= ENABLE1

30 0x0

IE_EOC:

= DISABLE0

= ENABLE1

27 0x1

ONCE:

= CYCLIC_MODE0

= SINGLE_BLOCK1

25:24 0x0

FC_MODE:

= NO_MMIO0

= ONE_MMIO1

= TWO_MMIO2

= FOUR_MMIO3

23:21 0x0

DMA_MODE:

= IO2MEM_NO_FC0

= IO2MEM_FC1

= MEM2IO_NO_FC2

= MEM2IO_FC3

= MEM2MEM4

= RSVD5

= FIXED_PAT6

20:16

0x0

REQ_SEL:

= I2C80

= I2C101

= UARTG2

= UARTC3

= QSPI05

= QSPI16

= UARTA8

= UARTB9

= UARTF12

= UARTH13

= SPI115

= SPI216

= SPI317

= UARTD19

= UARTE20

= I2C21

= I2C222

= I2C323

= I2C524

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Bit Reset Description

= I2C426

= I2C727

= I2C630

= I2C931

= RSVD29

15 0x1

IRQ_MASK:

= DISABLE0

= ENABLE1

13:10 0x1

WEIGHT

GPCDMA_CHANNEL_CH31_STA_0

Offset: 0x200004

Read/Write: See table below

Parity Protection: N

SCR Protection: SCR_CH31_0

Reset: 0x00000000 (0b00x0,0000,0x00,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit R/W Reset Description

31 RO 0x0

BSY:

= WAIT0

= ACTIVE1

30 RW 0x0

ISE_EOC:

= NO_INTR0

= INTR1

28 RO 0x0

PING_PONG_STA:

= PING_INTR_STA0

= PONG_INTR_STA1

27 RO 0x0

DMA_ACTIVITY:

= IDLE0

= BUSY1

26 RO 0x0

CHANNEL_PAUSE:

= RESUME0

= PAUSE1

25 RO 0x0

CHANNEL_RX:

= NOT_ACTIVE0

= ACTIVE1

24 RO 0x0

CHANNEL_TX:

= NOT_ACTIVE0

= ACTIVE1

23 RO 0x0

IRQ_INTR_STA:

= DISABLE0

= ENABLE1

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Bit R/W Reset Description

21 RO 0x0

TRIG_STA:

= NOT_ACTIVE0

= ACTIVE1

20 RO 0x0

INTR_STA:

= NOT_ACTIVE0

= ACTIVE1

GPCDMA_CHANNEL_CH31_CSRE_0

Offset: 0x200008

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH31_0

Reset: 0x00000000 (0b0xxx,xxxx,xxxx,0000,00xx,xxxx,xxxx,xxxx)

Bit Reset Description

31 0x0

DMA_ACTIVITY:

= RESUME0

= PAUSE1

19:14

0x0

TRIG_SEL:

= SMP_241

= SMP_252

= SMP_263

= SMP_274

= XRQ_A5

= XRQ_B6

= TMR17

= TMR28

= CH09

= CH110

= CH211

= CH312

= CH413

= CH514

= CH615

= CH716

= CH817

= CH918

= CH1019

= CH1120

= CH1221

= CH1322

= CH1423

= CH1524

= CH1625

= CH1726

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Bit Reset Description

= CH1827

= CH1928

= CH2029

= CH2130

= CH2231

= CH2332

= CH2433

= CH2534

= CH2635

= CH2736

= CH2837

= CH2938

= CH3039

= CH3140

= RSVD0

GPCDMA_CHANNEL_CH31_SRC_PTR_0

Offset: 0x20000c

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH31_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

SRC_PTR

GPCDMA_CHANNEL_CH31_DST_PTR_0

Offset: 0x200010

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH31_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

DST_PTR

GPCDMA_CHANNEL_CH31_HI_ADR_PTR_0

Offset: 0x200014

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH31_0

Reset: 0x00000000 (0bxxxx,xxxx,0000,0000,xxxx,xxxx,0000,0000)

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Bit Reset Description

23:16 0x0

HI_DST_PTR

7:0 0x0

HI_SRC_PTR

GPCDMA_CHANNEL_CH31_MC_SEQ_0

Offset: 0x200018

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH31_0

Reset: 0x03800000 (0b0000,0011,1000,0000,0000,0000,0000,0000)

Bit Reset Description

31 0x0

MC_DATA_SWAP:

= DISABLE0

= ENABLE1

30:25 0x1

MC_REQ_CNT

24:23 0x3

MC_BURST:

= DMA_BURST_2WORDS0

= DMA_BURST_16WORDS3

22:20 0x0

MC_ADDR_WRAP1:

= NO_WRAP0

= WRAP_0N_32WORDS1

= WRAP_ON_64WORDS2

= WRAP_ON_128WORDS3

= WRAP_ON_256WORDS4

= WRAP_ON_512WORDS5

= WRAP_ON_1024WORDS6

= WRAP_ON_2048WORDS7

19:17 0x0

MC_ADDR_WRAP0:

= NO_WRAP0

= WRAP_0N_32WORDS1

= WRAP_ON_64WORDS2

= WRAP_ON_128WORDS3

= WRAP_ON_256WORDS4

= WRAP_ON_512WORDS5

= WRAP_ON_1024WORDS6

= WRAP_ON_2048WORDS7

16 0x0

MC_AXIID

15:14 0x0

MC_PROT

13:7 0x0

STREAMID1

6:0 0x0

STREAMID0

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GPCDMA_CHANNEL_CH31_MMIO_SEQ_0

Offset: 0x20001c

Read/Write: See table below

Parity Protection: N

SCR Protection: SCR_CH31_0

Reset: 0x2381007f (0b0010,0011,1000,0001,xxxx,xxx0,0111,1111)

Bit R/W Reset Description

31 RW 0x0

DBL_BUF:

= DISABLE0

= ENABLE1

30:28 RW 0x2

MMIO_BUS_WIDTH:

= BUS_WIDTH_80

= BUS_WIDTH_161

= BUS_WIDTH_322

27 RW 0x0

MMIO_DATA_SWAP:

= DISABLE0

= ENABLE1

26:23 RW 0x7

MMIO_BURST:

= DMA_BURST_1WORDS0

= DMA_BURST_2WORDS1

= DMA_BURST_4WORDS3

= DMA_BURST_8WORDS7

= DMA_BURST_16WORDS15

22:19 RO 0x0

MMIO_MASTER_ID:

= RSVD0

= CCPLEX1

= CCPLEX_DPMU2

= BPMP3

= SPE4

= SCE5

= DMA_PER6

= TSECA7

= TSECB8

= JTAGM9

= CSITE10

= APE11

18:16 RW 0x1

MMIO_ADDR_WRAP:

= NO_WRAP0

= WRAP_0N_1WORDS1

= WRAP_ON_2WORDS2

= WRAP_ON_4WORDS3

= WRAP_ON_8WORDS4

= WRAP_ON_16WORDS5

= WRAP_ON_32WORDS6

= WRAP_ON_64WORDS7

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Bit R/W Reset Description

8:7 RW 0x0

MMIO_PROT

6:0 RO 0x7f

MMIO_CHANNEL_SECURITY

GPCDMA_CHANNEL_CH31_BCOUNT_0

Offset: 0x200020

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH31_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

BCOUNT

GPCDMA_CHANNEL_CH31_DMA_BYTE_TRA_0

Offset: 0x200024

Read/Write: RO

Parity Protection: N

SCR Protection: SCR_CH31_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

TRANSFER_COUNT

GPCDMA_CHANNEL_CH31_DMA_BYTE_STA_0

Offset: 0x200028

Read/Write: RO

Parity Protection: N

SCR Protection: SCR_CH31_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

DMA_COUNT

GPCDMA_CHANNEL_CH31_ERR_STA_0

Offset: 0x200030

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH31_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

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Bit Reset Description

31:0 0x0

ERROR_STATUS

GPCDMA_CHANNEL_CH31_FIXED_PAT_0

Offset: 0x200034

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_CH31_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

FIXED_PATTERN

GPCDMA_CHANNEL_CH31_TZ_0

Offset: 0x200038

Read/Write: R/W

Parity Protection: N

SCR Protection: SCR_TZ_0

Reset: 0x00000003 (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xx11)

Bit Reset Description

1 0x1

MC_PROT_1

0 0x1

MMIO_PROT_1

3.4 System Memory Management Unit (SMMU)

3.4.1 Overview

This chapter describes the Xavier Series SoC System Memory Management Unit (SMMU), which is part of the

memory system in Xavier. The purpose of the SMMU is to allow the use of virtual addressing for memory

accesses by the hardware devices in Xavier. The SMMU provides address translation, supports a two-stage

look-up for hypervisor support, and can apply various controls and protections for memory access. This function

is sometimes also referred to as an IOMMU.

The SMMU is based on the ARM MMU-500. This chapter should be read in conjunction with the ARM

documentation, in particular the

ARM CoreLink™ MMU-500 System Memory Management Unit Technical

, which details the implementation defined features, and the

Reference Manual ARM System Memory

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which is necessary in understanding the programming model.

Management Unit Architecture Specification,

Refer also to the Memory Subsystem (MSS) chapter of this TRM, where many SMMU related concepts are

discussed.

For the latest version of the ARM documents, refer to the ARM website: http://infocenter.arm.com/help/index.jsp

ARM CoreLink™ MMU-500 System Memory Management Unit Technical Reference Manual:

Document ID ARM DDI

0517E (ID072715)

ARM System Memory Management Unit Architecture Specification:

Document ID ARM IHI 0062D.b (ID071415)

SMMU Configuration

Xavier has three instances of SMMU. One of them serves the real-time requests from display and VI, and is

referred to as the ISO MMU (ISO is an abbreviation for isochronous). The other two serve the rest of the SOC

client traffic, and are referred to as NISO MMUs. All the SMMU instances are configured to support the

following:

64 contexts

Stage 1 and Stage 2 translation

7-bit streamID

128 stream matching groups

Six TBUs in each of NISO SMMU and four TBUs in ISO SMMU

The above configuration parameters may have an effect on registers defined in the

ARM System Memory

Management Unit Architecture Specification

Revision of the ARM IP used:

TBU: r2p2

TCU: r2p4

For the Xavier memory subsystem (MSS) data path to operate correctly, the following must be programmed:

AArch32 short descriptors should not be used.

Xavier supports only 7-bit StreamIDs, so SMR.MASK[14:7] must be programmed to 'hFF.

Program SCTLR.CFRE / SCTLR.CFIE / CR0.GFRE / CR0.GFIE / CR0.GCFGFRE / CR0.GCFGFIE = 1.

The stall-fault model is not supported. Program SCTLR.CFCFG = 0.

Prefetch must be disabled by setting SMMU_CBn_ACTLR.CPRE = 0.

StreamID

The StreamID is used to select a context in SMMU that is used for translation. For information on how to map a

streamID to a context, refer to the .

ARM System Memory Management Unit Architecture Specification

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The StreamID can be set by a client on a per-transaction basis. However, this behavior can be overridden by

programming the streamID override registers. The override is applied on a per-client basis for all transactions

issued by that client. Refer to the Memory Controller (MC) chapter for client details.

The StreamID override registers are part of a separate aperture aligned to 64 KB so that this can be controlled

by the hypervisor in a virtualized system.

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4 Boot and Power Management

4.1 Boot and Power Management Processor (BPMP)

4.1.1 Overview

The Boot and Power Management Processor (BPMP) complex provides a set of hardware functions that

support the following tasks:

Boot

Cold boot

Warm boot

Deep-sleep (SC7) entry and exit

Power Management

DVFS and clock/voltage management

SoC power state management

Core rail power management (i.e., VDD_CPU, VDD_CORE, VDD_CV, VDD_SOC)

Process, Voltage, and Temperature Sensor management

The BPMP complex includes:

Dual ARM Cortex-R5F cores running in delayed lock-step with 32 KiB of I-cache and 32 KiB of D-cache, both with

ECC

128 KiB of tightly-coupled memory (TCM) with ECC

Boot ROM

Timers, a DMA controller, an interrupt controller, and a set of peripherals for controlling the functions listed above

Note: The BPMP processor runs NVIDIA supplied software and is controlled through an NVIDIA API. Details of

the hardware programming interface are not supplied in this document.

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5 CPU Complex (CCPLEX)

The CPU Complex in the NVIDIA Xavier series SoC consists of four CPU clusters, each containing two

NVIDIA designed Carmel CPUs.

This chapter describes the overall CPU Complex and the Carmel clusters in Xavier, and is intended for use by

system programmers.

List of References

This chapter makes the implicit use of the following documents available from ARM , and assumes readers are

familiar with the ARM Architecture, and have access to the documents for reference. Refer to the ARM website

to download these documents.

ARM Architecture Reference Manual ARMv8

, .

for ARMv8-A architecture profile (ARM DDI 0487B.b)

ARM Debug Interface Architecture Specification

(ARM IHI 0031B)

ARM Generic Interrupt Controller Architecture Specification GICv2

(ARM IHI0048B)

ARM Reliability, Availability, and Serviceability

(RAS)

Specification ARMv8, for the ARMv8-A architecture profile

(ARM DDI 0587B)

The floating-point unit conforms to the following two specifications, available from the IEEE:

ANSI/IEEE, , Std 754-1985.

IEEE Standard for Binary Floating-Point Arithmetic

ANSI/IEEE, , Std 754-2008.

IEEE Standard for Floating-Point Arithmetic

The following ARM documents are also useful references for this TRM chapter and can be obtained from ARM:

ARM CoreSight SoC Technical Reference Manual

(ARM DDI 0480D), December 2012

ARM CoreSight Components Technical Reference Manual

(ARM DDI 0314H)

ARM CoreSight SoC User Guide

(ARM DUI 0563)

ARM CoreSight Integration Manual

(ARM DIT 0037)

ARM CoreSight Architecture Specification

(ARM IHI 0029)

Conventions of Units

This TRM chapter follows the IEEE and NIST conventions for multiplying prefixes. Among other things, this

convention uses an 'i' to indicate the binary convention, and its absence to indicate decimal. So, 1 KiB is 2 or

1,024 bytes, and 1 KB is 10 or 1,000 bytes. Similarly it uses:

Mi for 2 and M for 10

20 6

Gi for 2 and G for 10

30 9

Ti for 2 and T for 10

40 12

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5.1 CCPLEX Overview

The NVIDIA Xavier series SoC CPU complex contains four dual-core ARM CPU clusters, where each cluster

contains two NVIDIA Carmel ARM CPUs. All clusters are coherent and support SMP. All clusters can be active

simultaneously. All of the CPUs include full Advanced SIMD, VFP, ARMv8.0 Cryptographic Extension, and

ARMv8.2-FP16 support. Each cluster has its own L2 Cache which is shared between the two cores in the

cluster. The CPU Complex also has a 4 MiB victim L3 Cache which is strictly exclusive with the L2 Caches.

All the Carmel are identical, and implement the ARMv8.2 architecture. The CPU features include:

Full implementation of ARMv8.2 architecture

NVIDIA's Dynamic Code Optimization

10-wide Superscalar architecture

Dynamic branch prediction with a Branch Target Buffer, a Branch Information Buffer, a first level conditional predictor

backed by a multi-component direct predictor using Global History Buffer, a return stack buffer, and an indirect

predictor.

128-entry 4-way set-associative L1 instruction TLB with native support for the 4 KiB, 16 KiB, and 64 KiB page sizes

64-entry fully associative L1 data TLB with native support for the 4 KiB, 16 KiB, 64 KiB, 1 MiB, 2 MiB, 16 MiB, 32 MiB,

512 MiB, and 1 GiB page sizes

1024-entry 4-way set associative L2 instruction/data TLB with native support for the 4 KiB, 16 KiB, 64 KiB, 1 MiB, 2

MiB, 32 MiB, and 512 MiB page sizes.

2048-entry 4-way set-associative translation walk accelerator Cache shared by two Carmel cores

128 KiB 4-way set-associative parity-protected L1 Instruction Cache

64 KiB 4-way set-associative ECC-protected L1 Data Cache

2 MiB 16-way set-associative ECC-protected L2 Cache shared by two Carmel cores

L1 data hardware prefetcher which can cross page boundaries

L2 code and data hardware prefetcher which can cross page boundaries

Performance Monitor Unit (PMU) based on the PMUv3 architecture (with 16-bit evtCount field)

Cross Trigger Interface (CTI) for multiprocessor debugging

ARMv8.0 Cryptographic Extension support

ARMv8.2-FP16 support

Interface to an external Generic Interrupt Controller (vGIC-400)

Support for power management with multiple power domains

4 MiB 16-way set-associative ECC-protected victim L3 Cache which is strictly exclusive of the L2 Caches.

5.1.1 High-Level Multi-Core Block Diagram

The figure below shows a high-level diagram of the core complex (CCPLEX) as instantiated in the Xavier. The

CCPLEX consists of the following elements:

Four core clusters, each containing:

Two symmetric Carmel cores

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An L2 Cache complex, including the coherence logic and MMU for the two cores

System Coherence Fabric (SCF):

A request router to interact with the SoC's Memory Controller Fabric (MCF) and the IO Bridge (IOB) which

connects to the SoC's Control Backbone (CBB)

Inter cluster coherence logic to maintain coherence between the four CPU core clusters in the Coherence

Fabric.

The coherence fabric supports coherence between the four CPU core clusters and I/O coherence Note:

between the core clusters and other agents in the SoC.

A 4 MiB victim-style L3 Cache.

CCPLEX Miscellaneous Unit (CMU)

Debug logic for the SCF

A Generic Interrupt Controller (GICv2) for the eight cores in the CCPLEX

A Generic Timer Block

Power Management Control Logic for the whole CCPLEX

Figure 5.1 CCPLEX in Xavier Device

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5.1.2 Architectural Compliance

The Carmel processors comply with the ARMv8.2-A architecture profile. All the exception levels (EL0-EL3) are

supported in the AArch64 state. Exception levels EL0 and EL1 are supported in the AArch32 state. Jazelle is

only supported in the trivial implementation, and Thumb EE is not supported, as it has been removed from the

ARMv8 specification.

The Carmel processor also supports VFP operations, Advanced SIMD operations, the ARMv8.0 Cryptographic

Extension, and the ARMv8.2-FP16 extension.

5.1.3 GICv2

The CCPLEX contains a Generic Interrupt Controller, GICv2. The GIC-400 version r0p1 interrupt controller logic

is provided by ARM. The Generic Interrupt Controller in the CCPLEX is on the VDD_CORE SoC power rail, not

on the CPU voltage rail, so all the logic in the CPU voltage domain can be power gated and the GIC can wake

the processor from power-gated states. The GIC services all Carmel cores with unified interrupt routing.

5.1.4 High-Level Description of Micro-coded Implementation

The Carmel processor can decode the A32, T32, and A64 instructions using its hardware decoder into

microcode, which implements the instructions and executes on the machine. Some complex instructions cannot

be fully handled by the hardware decoder, so microcode routines implementing that functionality are executed

from the microcode carve-out located in main memory (DRAM). Additionally, the Carmel processor can detect

A32, T32, and A64 instruction sequences which execute repetitively, and improve the performance of those

sequences by using a technology called Dynamic Code Optimization (DCO). This is done by considering the

instruction sequences as a whole, translating them into higher performing microcode sequences stored in the

optimization Cache in the microcode carve-out, and executing the microcode sequences instead of the original

A32/T32/A64 instruction sequences when appropriate. Due to this, the Carmel processor requires that the

microcode carve-out be allocated an initialized in DRAM by boot software before any of the Carmel cores are

brought out of architectural reset.

5.1.5 High-Level Description of Power Management

The Xavier CCPLEX implements multiple power management capabilities:

Individual hardware blocks are clock-gated automatically when idle to save dynamic power.

Each core clock can be gated when the core is not actively executing instructions due to execution of WFI/WFE

instructions.

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Each core can be independently power-gated.

Each core cluster can be independently clock-gated when all cores are clock-gated or power-gated.

Each core cluster can be independently power-gated when all cores are power-gated.

Carmel implements an enhanced algorithm for managing power states, where allowed power states and

expected wakeup times are specified, and the hardware/microcode determines the best power state to enter for

the core, cluster, and CCPLEX. The Carmel cores support simplified power state entry sequences in ARM

software with the work offloaded to microcode. Refer to the "Functional Description" section below for more

details.

5.1.6 Cache Flushes and Multi-processor Coherence

The ARMv8 Cache flush by set/way instructions were originally designed for single-processor systems.

Therefore, they are not suitable for Cache cleaning or invalidation in a multi-processor system except under

carefully controlled circumstances. ARM has specified in the ARMv8 Architecture Reference Manual that these

instructions are expected to be used primarily for preparing for entry into a power state. The Xavier CPU

Complex (CCPLEX) has been designed with these limitations in mind. The Cache flush by set/way instructions

do not have an expected use-case for the Carmel processors and should not be used. Note that the Cache

flush by address instructions do work correctly in a multiprocessor system.

The Xavier CCPLEX implements a global Cache flush state machine to handle coherent Cache flushes of the

entire CCPLEX correctly. Cache flushes are requested via system registers, as specified in the System Control

section of this chapter.

5.2 CCPLEX Functional Description

This section describes the functionality of the Core Complex (CCPLEX) in the Xavier series SoC.

5.2.1 Top-Level Functional Diagram

The following figure shows the high-level functional diagram of the Core Complex in Xavier. Note that details

and connections are shown for only one of the four clusters.

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Figure 5.2 Core Complex Functional Diagram

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5.2.2 Xavier Processor Components

Instruction Fetch

The instruction fetch unit fetches half Cache lines from the L1 Instruction Cache and delivers up to three

instructions per cycle through the decode unit to the scheduler or bypasses the decode unit and provides up to

eight instructions per cycle directly to the scheduler. It supports dynamic and static branch prediction. The

instruction fetch unit includes:

128 KiB, 4-way set-associative Cache with 64-byte Cache lines with one Parity bit per byte in the data and one Parity

bit per 2 bytes in the tag.

128-entry, 4-way set-associative instruction TLB with native support for the 4 KiB, 16 KiB, and 64 KiB page sizes.

Branch Prediction

The branch prediction unit predicts branches in the instruction fetch code stream and the associated targets. It

includes:

A Next Line Predictor (NLP) which predicts the targets of conditional direct taken branches

A Branch Information Buffer (BIB) which contains the locations and types of previously detected branches.

A global history-based Conditional Direction Predictor (CDP) based on the Prediction by Partial Matching algorithm

A Branch Target Buffer (BTB) which predicts targets for direct branches

A path history-based Indirect Target Predictor (ITP) which predicts targets for indirect branches

A Return Stack Buffer (RSB)

A static predictor

Decode

The decode unit decodes the following ARMv8.2 instruction sets, including Advanced SIMD, VFP, the ARMv8.0

Cryptographic Extension, and ARMv8.2-FP16 instructions:

A32

T32

A64

The decode unit can issue up to three instructions to the scheduler per cycle.

Scheduler

The scheduler unit controls when instructions are dispatched to the execution pipelines. The scheduler can

dispatch up to eight instructions per cycle.

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Integer Execute/Integer Register File

The integer execute unit includes:

a basic ALU pipeline plus multiplies, integer divides, and Integer SIMD instructions

three additional basic ALU pipelines

a branch pipeline

a bypass network

an integer register file

Load/Store Unit

The load store execution unit contains the following:

two Load pipelines

one Store pipeline

64 KiB, 4-way set-associative L1 Data Cache with 8 bits of ECC per 8 data bytes

64-entry fully associative L1 data TLB with native support for the 4 KiB, 16 KiB, 64 KiB, 1 MiB, 2 MiB, 16 MiB, 32 MiB,

512 MiB, and 1 GiB page sizes

1024-entry 4-way set associative L2 instruction/data TLB with native support for the 4 KiB, 16 KiB, 64 KiB, 1 MiB, 2

MiB, 32 MiB, and 512 MiB page sizes

an L1 data Hardware Prefetcher that can prefetch across page boundaries

Advanced SIMD and Floating Point Unit

The Advanced SIMD and Floating Point Unit (FPU) executes the ARMv8.0, ARMv8.1, and ARMv8.2 Advanced

SIMD, VFP, the ARMv8.0 Cryptographic Extension, and ARMv8.2-FP16 instructions. This unit contains two

pipelines to execute these instructions. Both pipelines execute generic Floating-point and Advanced SIMD

instructions, with asymmetries highlighted below:

Floating-point and Advanced SIMD pipeline, including:

AES cryptography instructions

Floating-point division and square root instructions

Floating-point reciprocal and reciprocal square root estimate instructions

Advanced SIMD Integer reciprocal and reciprocal square root estimate instructions

Advanced SIMD Integer absolute difference instructions

SHA schedule update cryptography instructions

Floating-point multiply and fused multiply add instructions

Floating-point and Advanced SIMD pipeline, including:

Floating-point multiply and fused multiply add instructions

SHA hash cryptography instructions

Advanced SIMD Integer multiplication

Advanced SIMD Integer multiply-accumulate

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L2 Memory System

The L2 memory system services L1 Instruction Cache misses from each processor, L1 Data Cache misses

from each processor, and MMU requests, and contains Caches that are inclusive of all lines in L1 Data Caches.

The L2 memory system includes:

Shared pipeline for Coherent Cache and Non-Temporal and Partial Cache

2 MiB, 16-way set-associative L2 Coherent Cache with SEC-DED ECC protection per 128 bits

8 KiB (128 entries * 64 B / entry), fully-associative Non-Temporal and Partial Cache

L2 code and data Hardware Prefetcher that can prefetch across page boundaries

Memory Management Unit with 2048 entry Accelerator Cache for handling translation table walk requests

Power management logic

System Coherence Fabric

The System Coherency Fabric (SCF) connects the coherent clients, namely the Carmel CPU clusters, to DRAM

and MMIO space. CPU Core requests destined to MMIO space are directed to the input-output bridge (IOB)

sub-block within SCF which interfaces with the Control Backbone (CBB) that connects with the SoC IPs through

AXI fabric. SCF also connects clients attached through the memory controller fabric to DRAM. PCI-clients can

use this path to DRAM channels to benefit from the higher bandwidth address-independent WAW ordering

support in SCF. The SCF includes a 4 MiB L3 victim Cache.

These requests do snoop the CPU-Caches en route to DRAM.Note:

The SCF also implements a Coherency Cache Flush engine which facilitates software-based coherency with

the non-coherent clients in the system. There are two variants of flushes – one which cleans all Caches in the

CCPLEX and writes back dirty data to memory and another which invalidates all Cache lines resident in the

CCPLEX Caches before the flush was initiated. The CPUs do not have to be quiesced while the flush is in

progress.

The coherency fabric not only supports coherency only between the CPU core clusters, but also supports Note:

I/O coherency in hardware.

Generic Timer

The Generic Timer provides the ability to schedule events and trigger interrupts.

Even though the Generic Timer is a logical part of a core, it is implemented separately from the core to Note:

allow the functionality to persist when a core is power gated.

vGIC

The vGIC handles interrupts and the delivery of interrupts to the processor. This vGIC implementation is an

instantiation of the ARM Generic Interrupt Controller architecture version 2.0.

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Debug

The debug unit includes:

Support for ARMv8.2 Debug architecture with an AMBA Advanced Peripheral Bus (APB) slave interface for access to

the debug registers.

Performance Monitor Unit (PMU) based on the PMUv3 architecture.

Cross trigger interfaces for multiprocessor debugging.

5.3 CCPLEX Programming Guidelines

The Carmel processor implements the ARMv8.2 architecture, including

Support for all Exception levels, EL3-EL0 in AArch64

Support for EL0 and EL1 in AArch32

The following instruction sets:

AArch64 Execution state – the A64 instruction set

AArch32 Execution state – the T32 and A32 instruction sets

The Carmel processor also supports the following features:

A32, T32, and A64 Advanced Single Instruction Multiple Data (SIMD) instructions including the ARMv8.2-FP16

extension instructions

A32, T32, and A64 VFP (Floating-point) instructions including the ARMv8.2-FP16 extension instructions

A32, T32, and A64 ARMv8.0 Cryptographic Extension instructions

Generic Timer

The Carmel processor does not support the ThumbEE instruction set that has been removed from the ARMv8

architecture.

5.3.1 ARMv8 Architecture Concepts

Refer to the ARM Architecture Reference Manual ARMv8 ( ).https://developer.arm.com

5.3.2 Former ThumbEE Registers

ThumbEE is not supported in the ARMv8 architecture. Attempts to access the TEECR and TEEHBR registers

shall cause an Undefined Instruction trap.

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5.3.3 Jazelle Implementation

The Carmel processor implements a trivial Jazelle implementation as specified in the ARMv8 architecture.

5.3.4 Memory Model

The Carmel processor views memory as a linear collection of bytes numbered in ascending order from zero.

For example, byte 0 ~ 3 hold the first stored word, byte 4 ~ 7 hold the second stored word, and so on. The

processor can store words in the memory in either endianness format:

Big-endian format

Little-endian format

See the ARMv8 architecture documentation for more information about big-endian and little-endian memory

systems.

Instructions are always treated as little-endian.

5.3.5 Optimizing CPU Workloads

Core Selection

This section provides guidance on selecting cores for applications in an optimal manner

General Guidance on Core Selection for Workloads

The eight Carmel processors each have the same performance and power characteristics. However, due to

cache sharing effects and communication latencies it can sometimes be beneficial from a performance

perspective to statically assign applications to a specific core.

Guidance

On Unix/Linux/Android based kernels, the taskset utility is available and can be used to pin an application to a

given core ID or set of core ID’s. Core ID information can be obtained with the command in

cat /proc/cpuinfo

Unix/Linux/Android based kernels.

On QNX, an application can be pinned to a given core ID or set of core ID's using the construct

on -R

, e.g., to run on core 0 and 2, do the following:

<runmask> <program + options> 'ls' on -R 0x05 'ls'

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When running two threads that are either very performance demanding, or have tight communication with each other,

then the effects of L2 cache sharing will impact performance, see below under 'Background.'

Usually logical core 0 is loaded with system tasks, so to get peak performance, first schedule workloads on cores

other than core 0.

Background

The Carmel cores are all identical so are expected to deliver the same performance/power level. However, each

pair of cores share an L2 cache (two cores and an L2 cache form a core cluster), so it is sometimes beneficial

to schedule two performance demanding threads on two separate clusters. On the other hand, communication

latency is lower within a cluster than between clusters so threads that communicate frequently can benefit from

being scheduled on cores that are in the same cluster.

Software Scheduling on Carmel Cores Under Linux

The Linux operating system exposes several features that can be used to explicitly partition the CPUs in the

system into different sets. Notably, these are:

isolcpus - This kernel command line parameter isolates a subset of cores from the general system. No tasks will be

scheduled on these cores, unless explicitly assigned by the user.

cgroups/cpusets - More flexible runtime configuration mechanism that allows the creation of 'sets' of CPUs and

groups of tasks, and bind tasks to specific cpusets.

sched_setaffinity() - System call to specify what subset of cores an individual task is allowed to run on.

The user/application developer can use to map specific tasks to the sched_setaffinity()/cpusets

Carmel cores.

Single-threaded Workload Optimization

This section provides guidance on optimizing for single-threaded workloads.

Use cache invalidation by address, as opposed to I-cache invalidation

Invalidation by address has a lower performance penalty than full I-cache invalidation.

Guidance

Avoid or minimize the usage of full I-cache invalidation, that is, avoid using ARM instructions “ic iallu” and “ic

alluis” after Xavier has booted.

Background

Instruction cache invalidation typically has a higher performance penalty than cache-line invalidation, since the

cache needs to be reloaded. Further, this triggers a re-optimization of code in Carmel's DCO framework, since

an invalidation of the instruction cache is usually the result of a code change. Performance can be improved by

using a more directed cache invalidation technique, which is why invalidation by address is recommended.

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When possible, use non-temporal loads to access non-cacheable Memory Types, and

avoid running with the cache and MMU off

Non-cacheable (both device and non-streaming normal non-cacheable) loads in Carmel are strongly serializing.

Therefore these accesses can be slow, so the use of these kind of memory types is discouraged unless it is

required.

Running with caches and the MMU off is also discouraged. When the data cache is off, all loads are treated as

accessing device or non-cacheable memory; and when the MMU is off, all loads are treated as loads to device

memory.

Guidance

Either use cacheable normal memory, or when Use normal memory types only when accessing DRAM.

accessing non-cacheable regions, use streaming (non-temporal) loads.

Turn the MMU and data cache on as quickly as possible at startup.

Background

The Carmel memory system is essentially a fully out-of-order memory system, which does not preserve order

between independent loads. For cacheable loads, this is not problematic because the coupling between the

commitment logic and coherence snoops resolves potential ordering issues. However, for uncached access

operations (device and normal non-cacheable), there are no coherence snoops, and hence ordering must be

preserved by other means. In Carmel, this is done by completely serializing such uncached loads. This way,

there is only one outstanding at a time. Multiple outstanding uncached loads could lose order.

Streaming (non-temporal) loads to normal non-cacheable memory have relaxed ordering constraints. There can

be multiple such loads outstanding. Thus, for bulk data transfers, either use cacheable loads or streaming (non-

temporal) loads to normal non-cacheable memory.

Avoid lazy floating-point context save/restore

The cost of lazy floating-point (FP) save/restore outweighs the benefits on Carmel cores.

Guidance

Avoid or minimize the usage of lazy FP context save/restore.

Background

Lazy FP context save/restore is a method that allows the OS to skip floating-point register save and restore on

context switches, via disabling floating-point. This saves some latency, however, when a floating-point

instruction is issued, an exception is raised which loads the FP context. The cost of handling this exception

makes it unlikely for this optimization to be beneficial.

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Avoid unnecessary data movement between floating-point and integer registers

Performance might degrade when data moves from integer registers to floating-point registers for floating-point

operations, and is transferred back to integer registers before storing in memory.

Guidance

Reduce the number of floating-point and integer register interactions by using native float and double data types

and reducing casts between types in software. This does not require the use of intrinsics or compiler changes.

When there are both integer and floating-point versions of the data, use integer operations provided by the Advanced

SIMD instruction set that operates on the floating-point register file. Use direct loads and stores to the floating-point

registers (VLD/VST in AArch32, FLD/FST in AArch64). This may require usage of intrinsics. Alternatively, an

improved compiler can help.

When integer versions are not required, use direct loads and stores to the floating-point registers (VLD/VST in

AArch32, FLD/FST in AArch64) with VFP or floating-point flavors of Advanced SIMD operations. This may require

usage of intrinsics. Alternatively, an improved compiler can help.

Background

This behavior causes poor performance on all processors. Carmel supports one integer-to-floating-point register

transfer operation per cycle. Carmel also supports one floating-point-to-integer register transfer operation per

cycle, but it shares resources with the memory pipeline and thus competes for bandwidth.

Avoid converting from fixed point to FP16 in certain cases

The cost of converting from fixed point to FP16 is high in certain cases.

Guidance

Avoid converting from fixed point to FP16 unless FPCR.fz16==1 or unless the prevailing rounding mode is

Round-to-Zero.

Background

When (FPCR.fz16 == 0) or (rounding mode != Round-to-Zero), converting from fixed-point to FP16 involves

micro-code, thus making it a multi-cycle operation.

Use aligned accesses to memory, especially around 1 MiB Boundaries

Memory access operations that cross 1 MiB boundaries are slower than load or store operations that do not

cross 1 MiB. The cost of these 1 MiB boundary crossings can be up to 20 extra cycles.

Guidance

For wide operations, like those commonly performed in memcpy routines, try to keep every static ARM load or store

operation aligned.

Keep the stack pointer cache-line aligned and ensure that stack stores and loads are cache-line aligned.

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Background

Memory accesses that cross 1 MiB boundaries requires one extra access to the cache and incur a performance

penalty.

Avoid or minimize use of the MRC/MCR/MSR/MRS Instructions

The following system register access instructions can be slower than in other processor implementations:

MRC

MCR

MCRR

MRRC

MSR

MRS

Guidance

Minimize usage of these system register access instructions except in infrequently executed code. Frequently

executed code should consider reducing use, based on observed performance characteristics and trade-offs

with maintaining comparable processor state.

Background

System register access instructions are implemented in microcode and can take more cycles than on hardwired

ARM machines.

Avoid frequent context switches

Context switches are expensive in any architecture.

Guidance

Avoid frequent context switches.

Background

Context switches can result in performance problems when software is architected to run such a large number

of threads, that context switching between all these threads becomes a significant portion of the execution time.

Some micro-kernels have been observed to generally have kernel calls lead to context switches, which could

lead to performance problems due to very frequent context switches. In a performance-conscious

implementation care must be taken to minimize context switches.

Avoid a single lock for kernel calls

A single lock acquired when a process performs a kernel call results in stalling subsequent kernel calls from

other processes while the lock is held by the first process.

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Guidance

When an operating system implements a single lock for kernel calls, the recommendation is to try to minimize

calling into the kernel too frequently. In cases where frequent kernel calls are expected, it may be beneficial to

schedule the calling process on core zero. Note that there is also a drawback with scheduling applications on

core zero since they have to compete with the operating system, therefore there is no good scheduling rule that

always works best, the choice needs to be made based on profiling of performance sensitive applications.

Background

A performance concern observed in some micro-kernels is the lack of fine-grained locking of kernel data

structures. In multi-core systems like Xavier this serialization of kernel calls can result in significant performance

degradation.

Batch non-load/store operations requiring DMB/DSB/ISB

Barriers that are used to guarantee ordering and/or completion of operations other than load and store

operations may be expensive. This includes:

DMB barriers used to order cache maintenance operations with memory access operations.

DSB barriers used to order cache maintenance operations with memory access operations, or complete broadcast

TLB invalidations.

ISB barriers used to guarantee that system register access operations take effect.

DMB and DSB barriers that are just used to order load and store operations are relatively inexpensive. ISB

barriers used to flush the instruction fetch pipeline are also relatively inexpensive.

Guidance

Barriers with additional ordering or completion properties can degrade performance. DSBs that complete

broadcast TLB invalidations send DVM sync messages, and block forward progress until all outstanding

messages have been acknowledged by other cores. Such barriers should be batched.

Background

MMIO accesses in any system can take very long amounts of time to complete, and DSB or DMB will block

forward progress on the issuing core until a system MMIO access has resolved or timed out. Cache

maintenance operations in a large cache-coherent system can require probing structures distant from the core

which track cache occupancy. Broadcast TLB invalidation synchronization requires acknowledgement of DVM

messages from all active cores in the system. DMB and DSB barriers that merely order load and store

operations, and ISB barriers that merely flush the instruction fetch pipeline, can complete with only core-local

communication. DMB and DSB barriers, which order cacheable memory access operations, are close to NOPs

and should not be used to implement delays. Use the PAUSE instruction or consider ways to avoid

synchronization entirely.

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Breakpoints and watchpoints might interfere with optimizations

Some breakpoints and watchpoints logic may potentially lead to unexpected speed decreases, even when no

breakpoint or watchpoint related code is executed.

Guidance

Use of Breakpoints and Watchpoints should be minimized. When used, it should be done so with the

understanding that they can cause performance degradation even when the code at which they are placed isn’t

executed.

Background

Some breakpoint and watchpoint logic is implemented on 4 KiB granules, potentially leading to unexpected

slowdowns even when no breakpoint or watchpoint produces a match. This can result in code located on the

same 4 KiB region as the breakpoint/watchpoint running in a less optimized fashion on the CPU.

Avoid counting architectural instructions outside of code profiling

Counting architectural instructions might cause a small (~1%) reduction in program execution speed.

Guidance

Turn on architectural-instruction counting only when profiling code during application development. When

turned on, the impact to the profile is minimal, and the profile is accurate.

Background

Architectural instructions are counted using microarchitectural operations that occupy functional units.

Avoid instruction cache invalidates to pages which contain executable code

On Carmel, each time code is modified dynamically, that code might temporarily incur a significant reduction in

speed when the instruction cache is invalidated to make the modified code visible. When any part of a 4 Ki page

is invalidated, any code on that page is treated as though it is modified, incurring the same speed reduction.

Guidance

In general, minimize self-modifying code. Try to place mutable constant pools on a separate page from

executable code. Constant pools that are immutable should remain on the same page as the code.

Avoid placing mutable data on the same page as executable code. JIT compilers should evaluate strategies

that avoid allocating generated code on the same page as mutable data, including garbage-collection bits.

JITs should batch modifications and icache invalidates to a single page so that the cost of modifying the page is

not incurred repeatedly. This guideline applies both to the initial generation of code and to any later

modifications.

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Background

Self-modifying code may render dynamically optimized code invalid. The protection to detect modified code

operates at the granularity of a 4 Ki page. When the code has not actually changed, the dynamically optimized

code may be kept, at the cost of validating that the source code remains unchanged. When the validation fails,

the optimized code must be regenerated.

Avoid code re-use that accesses uncacheable or device memory

As explained above, accessing normal, non-cacheable memory or device memory is slower than accessing

normal, cacheable memory. When the same ARM code is used to access both cacheable and uncacheable

memory then optimization may be reduced.

Guidance

There should be few pieces of code that need to be applied to different memory types and it will usually be clear

which memory type is being accessed both as source and/or destination. Create separate copies of that code,

and use them only in the appropriate cases. For example, memcpy (source, destination) where source and

destination can be cached (C), non-cacheable (NC), or device (D) could require as many as nine versions for

highest performance - (C,C), (C,NC), (C,D), (NC,C), (NC,NC), (NC,D), (D,C), (D,NC), (D,D). Never apply

specialized versions of memcpy to mismatched source/destination memory types or use the regular system

memcpy for non-cached or device memory types.

Generally, this code duplication should be necessary only for the limited set of functions that need high

performance access to non-cacheable or device memory. Note also that the device specializations are required

on all ARM systems to abide by device memory alignment rules.

Background

The dynamic code optimizer changes the code that it generates to mitigate performance losses from access

operations to non-cacheable and device memory. Those changes result in reduced performance when applied

to normal cacheable memory.

This tension can be avoided by specializing the ARM code and applying the different versions against the

different memory types. The dynamic code optimizer tailors the generated code appropriately.

Emit aligned registers when using floating-point "S" registers in AArch32 code

The Carmel processor implements a high-performance, 128-bit FP datapath that executes best when operating

on aligned FP registers in AArch32 mode.

Guidance

For AArch32 code, use aligned floating-point "S" register allocation in your compiler or JIT.

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For S registers, source and destination operands for a given operation should be aligned in the same 32b sub-

lane of the 128b wide register, i.e., (src1_reg % 4) == (src2 % 4) == (dest_reg % 4). Thus, VADD S1, S5, S9 is

preferred over VADD S0, S1, S2.

Background

The Carmel CPU cores implement a 128 bit-wide floating-point data path which provides performance benefits

for AArch64 and full width advanced SIMD, i.e., 4-wide vector single precision code. However, due to the ARM

architectural layout of the AArch32 floating-point register file, source operands that do not use the full width of

the register file might be misaligned and require extra latency for alignment.

Use floating-point “Fused Multiply-Add” instead of “Floating-Point Chained Multiply-

Add” (also applies to SIMD MAC instructions)

Enable fused multiply-add instructions in compiled code, or use them in hand written assembly.

Guidance

Compile or write assembly in programs such that multiply-followed-by-add instructions can use a fused multiply-

add instructions (e.g. AArch32: VFMA, AArch64: FMADD, FMLA) rather than chained multiply-add (AArch32:

VMLA) or separate multiply and add instructions. One way to achieve this with the GCC compiler is to use the

GCC flags “–mfpu=vfpv4” and/or “–mfloat-abi=hard”. This may vary across GCC versions. Note that chained

multiply-add is only available in AArch32.

Background

Fused multiply-add instructions use a single rounding step for a multiply and add. In contrast, chained multiply-

add instructions require rounding after the multiply and add. As such, the fused versions of these instructions

are faster on the Carmel processor. The fused versions also use less code space than a multiply followed by an

add instruction.

Leverage fast floating-point Divides/Sqrt on Carmel

Software can leverage relatively fast floating-point divide and square root operations on Carmel.

Guidance

No need to avoid completely the usage of floating-point Divides/Sqrt on Carmel.

Background

FP divide/sqrt hardware is traditionally high latency, however Carmel uses fast hardware for relatively low

latency (compared to other dividers), so it may be more acceptable to use FP divide/sqrt on Carmel versus

other microarchitectures.

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Traditionally FP divide/sqrt hardware only allows one divide in flight at a time. Carmel has an optimization to

allow two scalar FP divides/sqrt in-flight at a time. This property may be leveraged by Software to allow more

divide density and yield higher FP divide/sqrt throughput.

Unroll loops no more than four times

Excessive loop unrolling can result in degraded performance.

Guidance

Unroll loops a limited number of times. A significant benefit from unrolling more than four times is unlikely.

For GCC this can be achieved by using the following option:

--param max-unroll-times=4

For clang this can be achieved by using the following option:

-mllvm -unroll-max-count=4

When the clang wrapper is not used but the optimizer is called directly, use:

-unroll-max-count=4

Background

The dynamic code optimizer unrolls loops further when there is an expected performance improvement. When

the loop has already been unrolled in software, the dynamic optimizer cannot undo the unrolling, which might

result in inferior performance because:

The dynamic optimizer might not form a region large enough to capture the loop, resulting in missed optimization

opportunities.

The dynamic optimizer might not allow a transaction long enough to capture the entire body of an excessively

unrolled loop, resulting in missed optimization opportunities.

The unrolled loop may dirty more architectural registers with temporary values and reduce opportunities for the

optimizer to remove computation

Excessive unrolling wastes icache space, resulting in stalls and reduced performance.

Multi-threaded Workload Optimization

This section provides guidance on optimizing for multi-threaded workloads.

Use the True Atomic Instructions defined in ARMv8.1, and avoid using the LDREX and

STREX Instructions for atomics

ARMv8.1 adds true atomic read-modify-write instructions, and the Carmel CPU implements these instructions. It

is highly encouraged to use the true atomic read-modify-write instructions to implement locks, rather than using

the LDREX and STREX sequences. LDREX and STREX sequences for locks cannot avoid live-lock and

starvation and cannot guarantee forward-progress. True atomic instructions are far preferable.

Guidance

ARMv8.1 introduced three types of atomic instructions:

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Compare and Swap instructions, CAS, and CASP.

Atomic memory operation instructions, LD<OP>, and ST<OP>, where <OP> is one of ADD, CLR, EOR, SET, SMAX,

SMIN, UMAX, and UMIN.

Swap instruction, SWP.

Use these to implement locks to avoid all issues with LDREX/STREX.

Carmel only supports exclusive instructions and atomic instructions when the memory type is Write-Back

cacheable. When using an unsupported memory type for atomics and exclusives, CPU will generate ARM MMU

fault. MMIO cannot be mapped as WB, so successful exclusive and atomic operations are known not to be

steered to MMIO.

It is still recommended to use an exclusive load along with WFE to back off when a lock cannot be acquired.

Background

Carmel supports ARMv8.2-A, and implements the True Atomic instructions added in ARMv8.1, these are a

significant improvement over the exclusive instructions due to the inherent live-lock issues with exclusives. Also

the exclusives define a monitor which incurs extra overhead to maintain on larger systems. Note these issues

are not specific to Carmel, but rather inherent in the ARM exclusives architecture.

Avoid False Sharing

Locating any mutable variable on the same cacheline as other variables accessed or updated by multiple cores

can result in reduced performance.

Even locating variables used temporally closely by different cores on adjacent cachelines may cause contention

when the cores prefetch nearby lines in an exclusive state.

Guidance

Attempt to localize mutated data to the fewest number of cores possible. Put frequently mutated data on

cachelines which do not contain data frequently read by other cores. Consider separating frequently updated

data by more than a cacheline from frequently read data. When sharing of frequently mutated data is required,

consider first sharing mutated data between cores in a cluster, and build a hierarchical data structure to

minimize cross-cluster accesses.

Background

Cache coherent multiprocessors must move data between processors when reads or writes are performed by a

core to a cache line it does not possess. Reads of data will remove exclusive permissions from processors

when data is shared. Writes to lines which are shared will tend to remove the shared data from other

processors caches before they can proceed. False-sharing or closely adjacent unshared data can waste time

and power on any processor, but especially larger multi-cluster designs.

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Avoid Frequent Lock Contention

Spin locks can consume large amounts of power when they are heavily contended by multiple cores.

Contended locks degrade single-threaded performance, waste power, and decrease aggregate throughput.

Carmel core-to-core and cluster-to-cluster cache transfers have higher cost than some other ARM processors,

particularly single cluster designs. Excessive lock contention between threads on different cores can degrade

performance.

Guidance

Preferentially construct locks with atomic operations. Follow the lock conventions specified by ARM: when lock

acquire code fails to acquire the lock, it should execute a LDREX/WFE before trying again; lock-release code

should execute a SEV when the lock is released (explicit SEV is not needed when writing to a line under the

WFE’s armed monitor). Allocate each lock to its own cache line. Cache lines including locks should not be

adjacent to other heavily shared or contended data structures because of the next-line prefetching scheme in

Carmel.

Avoid situations where multiple threads frequently contend for the same lock. This is especially important when

the threads span different core clusters.

Background

The Carmel cores are organized into clusters of two cores per cluster with each cluster having a shared L2.

Transferring cache lines between two different clusters incurs longer latency because the cores don't share an

L2 cache.

Avoid Frequent DVM Sync Messages

The cost of sending and serving a DVM sync message is relatively high in Carmel.

Guidance

Minimize or batch operations that require DVM sync messages to be sent other cores for their synchronization,

e.g., icache invalidates and broadcast TLB invalidates.

Background

DVM sync messages must be broadcast to all Carmel cores in a system and acknowledged before the

synchronization instruction can be passed. DVM sync messages incur some overhead when they arrive at their

destination by forcing an ACK to be issued. The cross cluster transfer latency for the messages in Xavier are

also greater than smaller single-cluster machines.

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5.4 System Control

5.4.1 Overview

This section describes the system control registers for the Carmel processor and how to program them.

The System control registers are employed to control the functions of the Carmel processor and provide their

status information. An understanding of the System register architecture as specified in the ARMv8

documentation is a necessary prerequisite before reading the rest of this section.

The Carmel processor does not implement the CP15SDISABLE feature.

AArch64 Register Summary

The following sections summarize the AArch64 registers implemented in the Carmel processor, their types

(Read-only, Write-only, Read-Write), their reset values, and widths. For more detailed descriptions, see the

ARMv8-A architecture profile documentation and AArch64 Debug Register Descriptions for implementation-

defined information. Note that registers associated with VFP, Advanced SIMD, the ARMv8.0 Cryptographic

Extension, the ARMv8.2-FP16 feature, and ARM Debug are documented in their individual sections of this

document. Also the detailed information on the RAS registers can be found in the RAS Architecture section.

AArch64 Identification Registers

Name Width Type Reset

MIDR_EL1 32 RO 0x4e0f0040

MPIDR_EL1 64 RO 0x0000000080000000 |

(cluster_id << 8) |

core_id

REVIDR_EL1 32 RO 0x00000000

ID_PFR0_EL1 32 RO 0x10000131

ID_PFR1_EL1 32 RO 0x00011011

ID_DFR0_EL1 32 RO 0x04000088

ID_AFR0_EL1 32 RO 0x00011030

ID_MMFR0_EL1 32 RO 0x10201105

ID_MMFR1_EL1 32 RO 0x40000000

ID_MMFR2_EL1 32 RO 0x01260000

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Name Width Type Reset

ID_MMFR3_EL1 32 RO 0x02122211

ID_MMFR4_EL1 32 RO 0x00021011

ID_ISAR0_EL1 32 RO 0x02101110

ID_ISAR1_EL1 32 RO 0x13112111

ID_ISAR2_EL1 32 RO 0x21232042

ID_ISAR3_EL1 32 RO 0x01112131

ID_ISAR4_EL1 32 RO 0x00011142

ID_ISAR5_EL1 32 RO 0x01011121

ID_AA64PFR0_EL1 64 RO 0x0000000010111122

ID_AA64DFR0_EL1 64 RO 0x0000000010305408

ID_AA64ISAR0_EL1 64 RO 0x0000000010211120

ID_AA64ISAR1_EL1 64 RO 0x0000000000000001

ID_AA64MMFR0_EL1 64 RO 0x0000000000101122

ID_AA64MMFR1_EL1 64 RO 0x0000000011212120

ID_AA64MMFR2_EL1 64 RO 0x0000000000001011

ID_AA64AFR0_EL1 64 RO 0x0000000000011030

CCSIDR_EL1 32 RO 0x70000002 (CSSELR == 0)

0x20000002 (CSSELR == 1)

0x70000002 (CSSELR == 2)

0x00000000 (CSSELR == 3)

0x50000002 (CSSELR == 4)

0x00000000 (CSSELR >= 5)

CLIDR_EL1 32 RO 0x0b200123

AIDR_EL1 32 RO (Microcode build number)

CSSELR_EL1 32 RW 0x00000000

CTR_EL0 32 RO 0x8444c004

DCZID_EL0 32 RO 0x00000004

VPIDR_EL2 32 RW 0x4e0f0040 (MIDR_EL1 value)

VMPIDR_EL2 64 RW 0x0000000080000000 |

(cluster_id << 8) |

core_id (MPIDR_EL1 value)

NVCCSIDR0_EL1 32 RO 0x001fe018 (CSSELR == 0)

0x003fe018 (CSSELR == 1)

0x00ffe078 (CSSELR == 2)

0x00000000 (CSSELR == 3)

0x01ffe078 (CSSELR == 4)

0x00000000 (CSSELR >= 5)

NVCCSIDR1_EL1

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Name Width Type Reset

0x0001e019 (CSSELR == 0)

0x00000000 (CSSELR == 1)

0x000003f9 (CSSELR == 2)

0x00000000 (CSSELR >= 3)

AArch64 Exception Handling Registers

Name Width Type Reset

AFSR0_EL1 32 RW 0x00000000 (Writes ignored)

AFSR1_EL1 32 RW 0x00000000 (Writes ignored)

ESR_EL1 32 RW 0x00000000

IFSR32_EL2 32 RW 0x00000000

AFSR0_EL2 32 RW 0x00000000 (Writes ignored)

AFSR1_EL2 32 RW 0x00000000 (Writes ignored)

ESR_EL2 32 RW 0x00000000

AFSR0_EL3 32 RW 0x00000000 (Writes ignored)

AFSR1_EL3 32 RW 0x00000000 (Writes ignored)

ESR_EL3 32 RW 0x00000000

FAR_EL1 64 RW 0x0000000000000000

FAR_EL2 64 RW 0x0000000000000000

HPFAR_EL2 64 RW 0x0000000000000000

FAR_EL3 64 RW 0x0000000000000000

VBAR_EL1 64 RW 0x0000000000000000

ISR_EL1 32 RO 0x00000000

VBAR_EL2 64 RW 0x0000000000000000

VBAR_EL3 64 RW 0x0000000000000000

AArch64 Virtual Memory Control Registers

Name Width Type Reset

SCTLR_EL1 32 RW 0x30d50820

SCTLR_EL2 32 RW 0x30c50820

SCTLR_EL3 32 RW 0x30c50830

TTBR0_EL1 64 RW 0x0000000000000000

TTBR1_EL1 64 RW 0x0000000000000000

TCR_EL1 64 RW 0x0000000000000000

TTBR0_EL2 64 RW 0x0000000000000000

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Name Width Type Reset

TCR_EL2 32 RW 0x80800000

VTTBR_EL2 64 RW 0x0000000000000000

VTCR_EL2 32 RW 0x80000000

TTBR0_EL3 64 RW 0x0000000000000000

TCR_EL3 32 RW 0x80800000

MAIR_EL1 64 RW 0x0000000000000000

AMAIR_EL1 64 RW 0x0000000000000000 (Writes ignored)

MAIR_EL2 64 RW 0x0000000000000000

AMAIR_EL2 64 RW 0x0000000000000000 (Writes ignored)

MAIR_EL3 64 RW 0x0000000000000000

AMAIR_EL3 64 RW 0x0000000000000000 (Writes ignored)

CONTEXTIDR_EL1 32 RW 0x00000000

AArch64 Other System Registers

Name Width Type Reset

ACTLR_EL1 32 RW 0x00000000

CPACR_EL1 32 RW 0x00000000

ACTLR_EL2 32 RW 0x00000000

ACTLR_EL3 32 RW 0x00000000

AArch64 Cache Maintenance Operations

The Carmel processor implements all the defined AArch64 Cache maintenance operations. See the ARMv8

AArch64 architecture documentation for the list and definition of the operations.

AArch64 TLB Maintenance Operations

The Carmel processor implements all the defined AArch64 TLB maintenance operations. See the ARMv8

architecture documentation for the list and definition of the operations.

AArch64 Address Translation Operations

Name Width Type Reset

PAR_EL1 64 RW 0x0000000000000000

AArch64 Miscellaneous Operations

Name Width Type Reset

TPIDR_EL0 64 RW 0x0000000000000000

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Name Width Type Reset

TPIDR_EL1 64 RW 0x0000000000000000

TPIDRRO_EL0 64 RW 0x0000000000000000

TPIDR_EL2 64 RW 0x0000000000000000

TPIDR_EL3 64 RW 0x0000000000000000

AArch64 Performance Monitors Registers

Name Width Type Reset

PMCR_EL0 32 RW 0x4e023000

PMCNTENSET_EL0 32 RW 0x00000000

PMCNTENCLR_EL0 32 RW 0x00000000

PMOVSCLR_EL0 32 RW 0x00000000

PMSWINC_EL0 32 WO N/A

PMSELR_EL0 32 RW 0x00000000

PMCEID0_EL0 32 RO 0x143f0f3f

PMCEID1_EL0 32 RO 0x0000001e

PMCCNTR_EL0 64 RW 0x0000000000000000

PMXEVTYPER_EL0 32 RW 0x00000000

PMCCFILTR_EL0 32 RW 0x00000000

PMXEVCNTR_EL0 32 RW 0x00000000

PMUSERENR_EL0 32 RW 0x00000000

PMINTENSET_EL1 32 RW 0x00000000

PMINTENCLR_EL1 32 RW 0x00000000

PMOVSSET_EL0 32 RW 0x00000000

AArch64 Reset Register

Name Width Type Reset

RVBAR_EL3 64 RO (Reset vector address)

AArch64 Security Registers

Name Width Type Reset

SCR_EL3 32 RW 0x00000030

SDER32_EL3 32 RW 0x00000000

CPTR_EL3 32 RW 0x00000000

MDCR_EL3 32 RW 0x00000000

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Name Width Type Reset

AFSR0_EL3 32 RW 0x00000000 (Writes ignored)

AFSR1_EL3 32 RW 0x00000000 (Writes ignored)

VBAR_EL3 64 RW 0x0000000000000000

AArch64 Virtualization Registers

Name Width Type Reset

VPIDR_EL2 32 RW 0x4e0f0040 (MIDR_EL1 value)

VMPIDR_EL2 64 RW 0x0000000080000000 |

(cluster_id << 8) |

core_id (MPIDR_EL1 value)

SCTLR_EL2 32 RW 0x30c50820

ACTLR_EL2 32 RW 0x00000000

HCR_EL2 64 RW 0x0000000000000000

MDCR_EL2 32 RW 0x00000006

CPTR_EL2 32 RW 0x000033ff

HSTR_EL2 32 RW 0x00000000

HACR_EL2 32 RW 0x00000000 (Writes ignored)

TTBR0_EL2 64 RW 0x0000000000000000

TCR_EL2 32 RW 0x80800000

VTTBR_EL2 64 RW 0x0000000000000000

VTCR_EL2 32 RW 0x80000000

DACR32_EL2 32 RW 0x00000000

AFSR0_EL2 32 RW 0x00000000 (Writes ignored)

AFSR1_EL2 32 RW 0x00000000 (Writes ignored)

ESR_EL2 32 RW 0x00000000

FAR_EL2 64 RW 0x0000000000000000

HPFAR_EL2 64 RW 0x0000000000000000

MAIR_EL2 64 RW 0x0000000000000000

AMAIR_EL2 64 RW 0x0000000000000000 (Writes ignored)

VBAR_EL2 64 RW 0x0000000000000000

AArch64 EL2 TLB Maintenance Operations

The Carmel processor implements all the defined ARMv8 AArch64 EL2 TLB maintenance operations. For

details, see the ARMv8 documentation.

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AArch64 Generic Timer Registers

Name Width Type Reset

CNTFRQ_EL0 32 RW 0x00000000

CNTPCT_EL0 64 RO (physical counter value)

CNTVCT_EL0 64 RO (same as physical counter value)

CNTVOFF_EL2 64 RW 0x0000000000000000

CNTKCTL_EL1 32 RW 0x00000000

CNTHCTL_EL2 32 RW 0x00000003

CNTP_TVAL_EL0 32 RW (derived from physical counter value)

CNTP_CTL_EL0 32 RW 0x00000000

CNTP_CVAL_EL0 64 RW 0x0000000000000000

CNTV_TVAL_EL0 32 RW (derived from physical counter value)

CNTV_CTL_EL0 32 RW 0x00000000

CNTV_CVAL_EL0 64 RW 0x0000000000000000

CNTHP_TVAL_EL2 32 RW (derived from physical counter value)

CNTHP_CTL_EL2 32 RW 0x00000000

CNTHP_CVAL_EL2 64 RW 0x0000000000000000

CNTPS_TVAL_EL1 32 RW (derived from physical counter value)

CNTPS_CTL_EL1 32 RW 0x00000000

CNTPS_CVAL_EL1 64 RW 0x0000000000000000

AArch64 Implementation-Defined Registers

Architecturally Specified Registers

Name Width Type Reset

ACTLR_EL1 32 RW 0x00000001

ACTLR_EL2 32 RW 0x00000000

ACTLR_EL3 32 RW 0x00000000

AFSR0_EL1 32 RW 0x00000000 (Writes ignored)

AFSR1_EL1 32 RW 0x00000000 (Writes ignored)

AFSR0_EL2 32 RW 0x00000000 (Writes ignored)

AFSR1_EL2 32 RW 0x00000000 (Writes ignored)

AFSR0_EL3 32 RW 0x00000000 (Writes ignored)

AFSR1_EL3 32 RW 0x00000000 (Writes ignored)

AMAIR_EL1 64 RW 0x0000000000000000 (Writes ignored)

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Name Width Type Reset

AMAIR_EL2 64 RW 0x0000000000000000 (Writes ignored)

AMAIR_EL3 64 RW 0x0000000000000000 (Writes ignored)

Cache Enumeration Registers

The Carmel processor Caches cannot be enumerated correctly in the ARMv8 defined CCSIDR_EL1 register.

So there are multiple Implementation-defined registers to enumerate the Cache information.

Name Width Type Reset

NVCCSIDR0_EL1 32 RO 0x001fe018 (CSSELR == 0)

0x003fe018 (CSSELR == 1)

0x00ffe078 (CSSELR == 2)

0x00000000 (CSSELR == 3)

0x01ffe078 (CSSELR == 4)

0x00000000 (CSSELR >= 5)

NVCCSIDR1_EL1 32 RO 0x0001e019 (CSSELR == 0)

0x00000000 (CSSELR == 1)

0x000003f9 (CSSELR == 2)

0x00000000 (CSSELR >= 3)

Microcode Activity and Control

The Carmel processor provides registers to monitor microcode activities and their means of control.

Name Width Type Reset

NVMSTAT0_EL1 64 RW 0x0000000000000000

NVMSTAT1_EL1 64 RO 0x0000000000000000

NVBGALLOWED_EL1 64 RW 0x000000ff00000000

NVIDIA Generic Interface Registers

The Carmel processor provides a generic indirect system register interface to support various types of

functionality. For details, see the AArch64 Register Descriptions section below.

Name Width Type Reset

NVGINDEX_EL1 32 RW 0x00000000

NVGDATA_EL1 64 RW 0x0000000000000000

Other Implementation Defined Registers

Name Width Type Reset

NV_NVLINK_CFG_EL1 32 RW 0x00000000

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Name Width Type Reset

NVFREQ_REQ_EL1 32 RW 0x00000000

NVFREQ_FEEDBACK_EL1 64 RO 0x0000000000000000

NV_BRANCH_PRED_FLUSH 64 WO N/A

NV_CLUSTER_COUNT_EL1 64 RO 0x0000000000000000

NV_ERXPFGCTL_EL1 64 RW 0x0000000000000000

NV_ERXPFGF_EL1 32 RO 0x40000042

NV_ERXPFGCDN_EL1 32 RW 0x00000000

NV_PMENTRY_START_TS_EL1 32 RO 0x00000000

NV_PMENTRY_END_TS_EL1 32 RO 0x00000000

NV_PMEXIT_START_TS_EL1 32 RO 0x00000000

NV_PMEXIT_END_TS_EL1 32 RO 0x00000000

NV_LAST_PMSTATE 32 RO 0x00000000

AArch64 Register Descriptions

For the most part, System registers are as defined in the ARMv8 documentation when the Carmel processor is

in AArch64 state. This subsection provides further information on the Carmel processor System registers, which

are unspecified in the ARMv8 documentation. Additionally, the Implementation-defined registers and fields are

specified here.

MIDR_EL1

The Carmel processor has the following MIDR_EL1 field values:

Implementer: 0x4e ('N')

Variant: 0x0 (This field changes values when programmer-visible ISA changes have been added to a product)

Architecture: 0xf (defined by the CPUID scheme)

Primary Part Number: 0x4

Revision: 0x0 (This number reflects the silicon base layer revision)

MPIDR_EL1

The Carmel processor has the following MPIDR_EL1 field values:

U: 0 (multiprocessor system)

MT: 0 (no multi-threading approach)

AFF2: 0

AFF1: Cluster number (0, 1, 2, or 3)

AFF0: Core number (0 or 1)

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REVIDR_EL1

The Carmel processor uses the REVIDR_EL1 register to specify the metal layer version associated with the

silicon base layer version specified in MIDR_EL1.

[7:0] Metal layer version (starts with 0 and increments)

ID_PFR0_EL1

The Carmel processor has the following ID_PFR0_EL1 field values:

RAS: 0x1 (Version 1 of the RAS Extension present)

State3: 0x0 (No ThumbEE support)

State2: 0x1 (Trivial implementation of Jazelle)

State1: 0x3 (Support Thumb, Thumb2)

State0: 0x1 (ARM support)

ID_PFR1_EL1

The Carmel processor has the following ID_PFR1_EL1 field values:

GIC cp15 Interface: 0x0 (Not supported)

Virtualization Extensions Fractional Field: 0x0 (the Carmel processor implements the full Virtualization Extensions)

Security Extensions Fractional Field: 0x0 (the Carmel processor implements the full Security Extensions)

Generic Timer Support: 0x1 (Supported)

Virtualization Extensions: 0x1 (Supported)

M profile programmers' model: 0x0 (Not supported)

Security Extensions: 0x1 (Supports Monitor mode and SMC)

Programmers' model: 0x1 (Standard programmers' model supported)

ID_DFR0_EL1

The Carmel processor has the following ID_DFR0_EL1 field values:

Performance Monitor model, A and R Profiles: 0x4 (Support for performance monitor features, version 3 with 16-bit

evtCount field)

Debug model, M profile: 0x0 (Not supported)

Memory-mapped trace model: 0x0 (Not compatible with v7-A memory map, and memory mapped trace model is not

supported in the Carmel processor)

Coprocessor trace model: 0x0 (Not supported)

Memory-mapped debug model, A and R profiles: 0x0 (Not supported)

Coprocessor Secure debug model: 0x8 (Support for ARMv8.2 Debug architecture with CP14 access)

Coprocessor debug model: 0x8 (Support for ARMv8.2 Debug architecture with CP14 access)

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ID_AFR0_EL1

The Carmel processor defines the ID_AFR0_EL1 register as follows:

[3:0] SERROR support: 0x0 (No IMPLEMENTATION DEFINED SERROR support)

[7:4] Performance monitoring extension: 0x3 (Supports the Performance monitoring extension registers as

implemented in the Carmel processor)

[11:8] NVIDIA Cache Operations support: 0x0 (NVIDIA Cache operations extension not supported)

[15:12] NVIDIA Interruptible Cache Operations support: 0x1 (NVIDIA Interruptible Cache Operations extension

supported)

[19:16] NVIDIA Branch Predictor Operations support: 0x1 (NVIDIA Branch Predictor Operations extension supported,

including the NV_BRANCH_PRED_FLUSH coprocessor register and ACTLR_EL2 trap support)

[31:20] Not defined, Read-as-0

ID_MMFR0_EL1

The Carmel processor has the following ID_MMFR0_EL1 field values:

Innermost Shareability: 0x1 (Implemented with hardware coherency support)

FCSE Support: 0x0 (Not Supported)

Auxiliary Registers: 0x2(ACTLR, AIFSR, and ADFSR are supported)

TCM Support: 0x0 (Not Supported)

Shareability Levels: 0x1 (Two levels of shareability implemented)

Outermost Shareability: 0x1 (Implemented with hardware coherency support)

PMSA Support: 0x0 (Not supported)

VMSA Support: 0x5 (Support for VMSAv7, including remapping and the access flag, PXN in first level descriptors,

and 64-bit translation descriptors)

ID_MMFR1_EL1

The Carmel processor has the following ID_MMFR1_EL1 field values:

Branch Predictor: 0x4 (For execution correctness, branch predictor requires no flushing at any time)

L1 Cache Test and Clean: 0x0 (None Supported)

L1 Unified Cache: 0x0 (None Supported)

L1 Harvard Cache: 0x0 (None Supported)

L1 Unified Cache Set/Way: 0x0 (None Supported)

L1 Harvard Cache Set/Way: 0x0 (None Supported)

L1 Unified Cache VA: 0x0 (None Supported)

L1 Harvard Cache VA: 0x0 (None Supported)

ID_MMFR2_EL1

The Carmel processor has the following ID_MMFR2_EL1 field values:

Hardware Access Flag: 0x0 (Not Supported)

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WFI stall: 0x1 (Support for WFI stalling)

Mem barrier: 0x2 (Support for CP15 DSB, ISB, and DMB)

Unified TLB: 0x6 (Support for invalidate all, invalidate by MVA, invalidate by ASID, invalidate by MVA all ASID,

invalidate Hyp entry by MVA, invalidate entire non-secure, non-Hyp, invalidate entire Hyp, TLBIMVALIS,

TLBIMVAALIS, TLBIMVALHIS, TLBIMVAL, TLBIMVAAL, TLBIMVALH, TLBIIPAS2IS, TLBIIPAS2LIS, TLBIIPAS2,

TLBIIPAS2L)

Harvard TLB: 0x0 (Not Supported)

L1 Harvard range: 0x0 (Not Supported)

L1 Harvard bg prefetch: 0x0 (Not Supported)

L1 Harvard fg prefetch: 0x0 (Not Supported)

ID_MMFR3_EL1

The Carmel processor has the following ID_MMFR3_EL1 field values:

Supersection Support: 0x0 (Supersections supported)

Physical Memory Size (4 bits): 0x2 (40 bits)

Coherent Walk: 0x1 (Updates to the translation tables do not require a clean to the point of unification to ensure

visibility by subsequent translation table walks)

Privileged Access Never: 0x2 (Privileged Access Never and AT S1E1RP/S1E1WP instructions supported)

Maintenance Broadcast: 0x2 (Cache, TLB, and branch predictor operations affect structures according to shareability

and defined behavior of instructions)

BP Maintain: 0x2 (Supported branch predictor maintenance operations are Invalidate all branch predictors and

Invalidate branch predictors by MVA)

Cache Maintain Set/Way: 0x1 (Invalidate by set/way, clean by set/way, clean and invalidate by set/way supported)

Cache Maintain MVA: 0x1 (invalidate data Cache by MVA, clean data Cache by MVA, clean and invalidate data

Cache by MVA, invalidate instruction Cache by MVA, invalidate all instruction Cache entries)

ID_MMFR4_EL1

The Carmel processor has the following ID_MMFR4_EL1 field values:

LDM/STM Ordering Behavior Control: 0x0 (LSMAOE and nTLSMD bits not supported)

Hierarchical Permission Disables: 0x2 (Hierarchical Permission Disables supported and Hardware allocation of bits

[62:59] supported

Common Not Private: 0x1 (Common Not Private bit supported)

EL0/1 Execute Never Control at Stage 2: 0x1 (EL0/EL1 execute control distinction at stage2 bit supported)

ACTLR2/HACTLR2: 0x1 (ACTLR2/HACTLR2 supported)

SError interrupt on speculative reads: 0x1 (The PE might generate an SError interrupt due to an external abort on a

speculative read)

ID_ISAR0_EL1

The Carmel processor has the following ID_ISAR0_EL1 field values:

Divide Instructions: 0x2 (SDIV and UDIV are supported in Thumb and ARM ISAs)

Debug Instructions: 0x1 (BKPT supported)

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Coproc Instructions: 0x0 (none implemented, except for instructions separately attributed by the architecture,

including CP15, CP14, Advanced SIMD Extension and the Floating-point Extension)

CmpBranch Instructions: 0x1 (CBNZ and CBZ are supported)

Bitfield Instructions: 0x1 (BFC, BFI, SBFX, and UBFX are supported)

Bitcount Instructions: 0x1 (CLZ is supported)

Swap Instructions: 0x0 (none supported)

ID_ISAR1_EL1

The Carmel processor has the following ID_ISAR1_EL1 field values:

Jazelle Instructions: 0x1 (BXJ and the J-bit are supported; trivial implementation of Jazelle)

Interwork Instructions: 0x3 (BX, BLX instructions supported, T-bit is supported in PSR, data processing instructions in

ARM ISA with PC as dest and S-bit clear have BX-like behavior)

Immediate Instructions: 0x1 (MOVT, MOV with zero-extended 16-bit immediates, Thumb ADD/SUB with zero-

extended 12-bit immediates are supported)

If/Then Instructions: 0x1 (IT instructions and the IT bits in the PSRs are supported)

Extend Instructions: 0x2 (SXTB, SXTH, UXTB, UXTH, SXTB16, SXTAB, SXTAB16, SXTAH, UXTB16, UXTAB,

UXTAB16, and UXTAH are supported)

Except AR Instructions: 0x1 (SRS, RFE, and CPS are supported)

Except Instructions: 0x1 (LDM (exception return), LDM (user registers), and STM (user registers) are supported)

Endian Instructions: 0x1 (SETEND and the E bit in the PSRs are supported)

ID_ISAR2_EL1

The Carmel processor has the following ID_ISAR2_EL1 field values:

Reversal Instructions: 0x2 (REV, REV16, REVSH, RBIT instructions supported)

PSR AR Instructions: 0x1 (MRS/MSR to PSR and exception return forms of data processing instructions supported)

MultU Instructions: 0x2 (UMULL, UMLAL, UMAAL instructions supported)

MultS Instructions: 0x3 (SMULL, SMLAL, SMLABB, SMLABT, SMLALBB, SMLALBT, SMLALTB, SMLALTT,

SMLATB, SMLATT, SMLAWB, SMLAWT, SMULBB, SMULBT, SMULTB, SMULTT, SMULSB, SMULWT, SMLAD,

SMLADX, SMLALD, SMLALDX, SMLSD, SMLSDX, SMLSLD, SMLSLDX, SMMLA, SMMLAR, SMMLS, SMMLSR,

SMMUL, SMMULR, SMUAD, SMUADX, SMUSD, SMUXDX instructions are supported along with the Q bit in the

PSRs)

Mult Instructions: 0x2 (MLA and MLS are supported)

MultiAccess Instructions: 0x0 (LDM and STM are not interruptible)

MemHint Instructions: 0x4 (PLD, PLI, and PLDW supported)

LoadStore Instructions: 0x2 (LDRD, STRD, and load-acquire/store-release instructions supported)

ID_ISAR3_EL1

The Carmel processor has the following ID_ISAR3_EL1 field values:

ThumbEE Extn Instructions: 0x0 (None supported)

TrueNOP Instructions: 0x1 (True NOP instructions are supported for Thumb/ARM ISAs along with additional NOP-

compatible hints)

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ThumbCopy Instructions: 0x1 (T1 encoding of the MOV (register) instruction supports a copy from a low register to a

low register)

TabBranch Instructions: 0x1 (TBB and TBH are supported)

SynchPrim Instructions: 0x2 (LDREX, STREX, CLREX, LDREXB, LDREXH, STREXB, STREXH, LDREXD, and

STREXD instructions are supported)

SVC Instructions: 0x1 (SVC is supported)

SIMD Instructions: 0x3 (SSAT, USAT, PKHBT, PKHTB, QADD16, QADD8, QASX, QSUB16,QSUB8, QSAX,

SADD16, SADD8, SASX, SEL, SHADD16, SHADD8, SHASX, HSUB16, SHSUB8, SHSAX, SSAT16, SSUB16,

SSUB8, SSAX, SXTAB16, SXTB16, UADD16, UADD8, UASX, UHADD16, UHADD8, UHASX, UHSUB16, UHSUB8,

UHSAX, UQADD16, UQADD8, UQASX, UQSUB16, UQSUB8, UQSAX, USAD8, USADA8, USAT16, USUB16,

USUB8, USAX, UXTAB16, and UXTB16 instructions are supported and GE[3:0] bits in the PSRs are supported)

Saturate Instructions: 0x1 (QADD, QDADD, QDSUB, and QSUB instructions are supported and the Q bit in the PSRs

is implemented)

ID_ISAR4_EL1

The Carmel processor has the following ID_ISAR4_EL1 field values:

SWP frac: 0x0 (SWP/SWPB not supported)

PSR M Instructions: 0x0 (None Supported)

SynchPrim Instructions Frac: 0x0 (LDREX, STREX, CLREX, LDREXB, LDREXH, STREXB, STREXH, LDREXD, and

STREXD instructions are supported)

Barriers Instructions: 0x1 (DMB, DSB, ISB instructions supported)

SMC Instructions: 0x1 (SMC instruction supported)

Writeback Instructions: 0x1 (All Writeback addressing modes in ARMv7 supported)

WithShifts Instructions: 0x4 (All forms of shift options supported)

Unpriv Instructions: 0x2 (LDRBT, LDRT, STRBT, STRT, LDRHT, LDRSBT, LDRSHT, STRHT instructions supported)

ID_ISAR5_EL1

The Carmel processor has the following ID_ISAR5_EL1 field values:

RDM: 0x1 (SQRDMLAH and SQRDMLSH supported in AArch32)

CRC32: 0x1 (CRC32/CRC32C instructions implemented)

SHA2: 0x1 (SHA256H, SHA256H2, SHA256SU0, SHA256SU1 instructions implemented)

SHA1: 0x1 (SHA1C, SHA1P, SHA1M, SHA1H, SHA1SU0, SHA1SU1 instructions implemented)

AES: 0x2 (AESE, AESD, AESMC, AESIMC, PMULL, PMULL2 instructions implemented)

SEVL: 0x1 (SEVL implemented to send event local)

Note that some versions of the Carmel processor may have the ARMv8.0 Cryptographic Extension instructions

disabled, in which case the SHA2, SHA1, and AES fields will return 0.

ID_AA64PFR0_EL1

The Carmel processor has the following ID_AA64PFR0_EL1 field values:

RAS: 0x1 (Version 1 of the RAS Extension present)

GIC system registers: 0x0 (No GIC System registers are supported)

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Advanced SIMD: 0x1 (Advanced SIMD is implemented, including Half-precision floating point support)

Floating-point: 0x1 (Floating point is implemented, including Half-precision floating point support)

EL3 Exception Level Handling: 0x1 (EL3 can only be executed in AArch64 state)

EL2 Exception Level Handling: 0x1 (EL2 can only be executed in AArch64 state)

EL1 Exception Level Handling: 0x2 (EL1 can be executed in either AArch64 or AArch32 state)

EL0 Exception Level Handling: 0x2 (EL0 can be executed in either AArch64 or AArch32 state)

ID_AA64DFR0_EL1

The Carmel processor has the following ID_AA64DFR0_EL1 field values:

CTX_CMPs: 0x1 (2 context aware breakpoints)

WRPs: 0x3 (4 watchpoints)

BRPs: 0x5 (6 breakpoints)

Performance Monitor Extension Version: 0x4 (Performance monitor extension system registers implemented, PMUv3,

with a 16-bit evtCount field and MDCR_EL2.HPMD)

Trace extension version: 0x0 (SYS interface to trace registers not supported)

Debug architecture version: 0x8 (ARMv8.2 debug architecture supported)

ID_AA64ISAR0_EL1

The Carmel processor has the following ID_AA64ISAR0_EL1 field values:

RDM: 0x1 (SQRDMLAH and SQRDMLSH instructions implemented)

Atomic: 0x2 (LDADD, LDCLR, LDEOR, LDSET, LDSMAX, LDSMIN, LDUMAX, LDUMIN, CAS, CASP, and SWP

instructions implemented)

CRC32 Instructions in AArch64: 0x1 (CRC32/CRC32C supported)

SHA2 Instructions in AArch64: 0x1 (SHA256H, SHA256H2, SHA256SU0, SHA256SU1 supported)

SHA1 Instructions in AArch64: 0x1 (SHA1C, SHA1P, SHA1M, SHAH, SHA1SU0, SHA1SU1 supported)

AES Instructions in AArch64: 0x2 (AESE, AESD, AESMC, AESIMC, PMULL, PMULL2 supported)

ID_AA64ISAR1_EL1

The Carmel processor has the following ID_AA64ISAR1_EL1 field values:

DPB: 0x1 (DC CVAP supported)

ID_AA64MMFR0_EL1

The Carmel processor has the following ID_AA64MMFR0_EL1 field values:

4 KiB Granule Support: 0x0 (4 KiB granule supported)

64 KiB Granule Support: 0x0 (64 KiB granule supported)

16 KiB Granule Support: 0x1 (16 KiB granule supported)

Mixed Endian Support at EL0 only: 0x0 (RES0 since Mixed Endian Configuration is non-zero)

Secure/Nonsecure Memory: 0x1 (Supports a distinction between Secure and Non-secure memory). This is at the

processor level and not necessarily the platform level.

Mixed Endian Configuration: 0x1 (Mixed-endian support)

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Number of ASID Bits: 0x2 (16 bits of ASID supported)

Physical Address Range: 0x2 (40 bits of physical address)

ID_AA64MMFR1_EL1

The Carmel processor has the following ID_AA64MMFR1_EL1 field values:

EL0/1 Execute Never Control at Stage 2: 0x1 (EL0/EL1 execute control distinction at stage2 bit supported)

SError interrupt on speculative reads: 0x1 (The PE might generate an SError interrupt due to an external abort on a

speculative read)

Privileged Access Never: 0x2 (Privileged Access Never and AT S1E1RP/S1E1WP instructions supported)

Limited Order Regions: 0x1 (LORRegions supported)

Hierarchical Permission Disables: 0x2 (Hierarchical Permission Disables supported and Hardware allocation of bits

[62:59] supported

Virtualization Host Extensions: 0x1 (Virtualization Host Extensions supported)

VMID Size: 2 (16 bits)

HW A/D Bit Update: 0x0 (no hardware update of the Access and Dirty bits)

ID_AA64MMFR2_EL1

The Carmel processor has the following ID_AA64MMFR2_EL1 field values:

Virtual Address Size: 0 (48 bits of VA for each translation table page register (for 64 KiB stage1 pages) are

supported)

Implicit Error Synchronization Barrier: 0x1 (SCTLR_ELx.IESB implicit ErrorSynchronizationBarrier control is

implemented)

LDM/STM Ordering Behavior Control: 0x0 (LSMAOE and nTLSMD bits not supported)

User Access Override: 0x1 (User Access Override supported)

Common Not Private: 0x1 (Common Not Private bit supported)

ID_AA64AFR0_EL1

The Carmel processor defines the ID_AA64AFR0_EL1 register as follows:

[3:0] SERROR Support: 0x0 (Does not support IMPLEMENTATION DEFINED mechanisms for signaling SERROR)

[7:4] Performance monitoring extension: 0x3 (Supports the Performance monitoring extension registers as

implemented in the Carmel processor)

[11:8]: NVIDIA Cache Operations: 0x0 (Does not support the NVIDIA system register Cache flush extension)

[15:12] NVIDIA Interruptible Cache Operations: 0x1 (Supports the NVIDIA Interruptible Cache Operations extension)

[19:16] NVIDIA Branch Predictor Operations: 0x1 (Supports the NVIDIA Branch Predictor Operations extension,

including the NV_BRANCH_PRED_FLUSH system register and trapping support in ACTLR_EL2

[31:20]: Not defined, Read-as-0

CCSIDR_EL1

The Carmel processor has the following CCSIDR_EL1 field values:

CSSELR 0 (L1 Data Cache)

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WT/WB/RA/WA: 0x7

NumSets: 0x0

Associativity: 0x0

Linesize: 0x2 (64 byte Cache line)

CSSELR 1 (L1 Instruction Cache)

WT/WB/RA/WA: 0x2

NumSets: 0x0

Associativity: 0x0

Linesize: 0x2 (64 byte Cache line)

CSSELR 2 (L2 Cache)

WT/WB/RA/WA: 0x7

NumSets: 0x0

Associativity: 0x0

Linesize: 0x2 (64 byte Cache line)

CSSELR 4 (L3 Cache)

WT/WB/RA/WA: 0x5

NumSets: 0x0

Associativity: 0x0

Linesize: 0x2 (64 byte Cache line)

CSSELR 3 >= 5 (Reserved: no further Caches enumerated)

0x00000000

Note that the number of sets and ways (Associativity) are reported as 1 and 1, respectively, to allow the Cache

manipulation by set/way instructions to work correctly.

CLIDR_EL1

The Carmel processor has the following CLIDR_EL1 field values:

ICB: 0x0 (not disclosed in this mechanism)

LoUU: 0x1 (IL1 and DL1 need to be flushed for self-modifying code to work)

LoC: 0x3 (non-snooping DMA needs to flush through the L3)

LoUIS: 0x1 (IL1 and DL1 need to be flushed for self-modifying code to work)

Ctype4 ~ Ctype7: 0x0 (No Cache)

Ctype3: 0x4 (Unified Cache)

Ctype2: 0x4 (Unified Cache)

Ctype1: 0x3 (Separate instruction and data Caches)

AIDR_EL1

The Carmel processor returns a value for AIDR_EL1 which indicates the microcode revision. All microcode

revisions are unique, and a higher value indicates a more recent microcode revision.

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CTR_EL0

The Carmel processor has the following CTR_EL0 field values:

CWG: 0x4 (16 words * 4 bytes/word = 64-byte Cache lines)

ERG: 0x4 (16 words * 4 bytes/word = 64-byte Cache lines)

DminLine: 0x4 (16 words * 4 bytes/word = 64-byte L1 Cache lines)

L1Ip: 0x3 (Physical Index, Physical Tag)

IminLine: 0x4 (16 words * 4 bytes/word = 64-byte L1 Cache lines)

DCZID_EL0

The Carmel processor has the following DCZID_EL0 field values:

Block Size: 4 (log2 (64bytes/4 bytes/word))

DZP: Value based on the values of SCTLR_EL1.DZE, HCR_EL2.TDZ, the exception level, and the security state.

ACTLR_EL1

The Carmel processor has the following definition for ACTLR_EL1:

[3:0] PMSTATE: Software-requested core power management state to be used at the next WFI instruction

[4] DUAL_EXEC_EL1: When set, only dual execution dynamic code sequences are executed at EL1. When clear,

normal dynamic code sequences are executed at EL1.

[5] DUAL_EXEC_EL0: When set, only dual execution dynamic code sequences are executed at EL0. When clear,

normal dynamic code sequences are executed at EL0.

[6] DIS_MD_EL1: When set and not overridden by ACTLR_EL2, speculative memory disambiguation is disabled at

EL1. When cleared, speculative memory disambiguation operates normally in EL1.

[7] DIS_MD_EL0: When set and not overridden by ACTLR_EL2, speculative memory disambiguation is disabled at

EL0. When cleared, speculative memory disambiguation operates normally in EL0.

[8] DIS_SSB_EL1: When set and not overridden by ACTLR_EL2, speculative store buffering is disabled at EL1.

When cleared, speculative store buffering operates normally in EL1.

[9] DIS_SSB_EL0: When set and not overridden by ACTLR_EL2, speculative store buffering is disabled at EL0.

When cleared, speculative store buffering operates normally in EL0.

[12:10] Reserved: always returns 0

[13] RESET_RAS_FMON: A write of 1 to this write-only bit re-enables checking for RAS cluster frequency monitoring

errors which are temporarily disabled when detected. A write of 0 is ignored.

[31:14] Reserved: always returns 0

The PMSTATE field is shared state across ACTLR_EL1, ACTLR_EL2, and ACTLR_EL3. The supported

encodings for this field are:

Name Value Description

C1 0x1 Core C1 power management state (clock gated)

C6 0x6 Core C6 power management state (power gated, retain state)

C7 0x7 Core C7 power management state (power gated, resume at reset vector)

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Other encodings are reserved and should not be used.

On entry to the C0 power state or on taking an ARM architectural interrupt, the PMSTATE field is reset to the

C1 value.

ACTLR_EL2

The Carmel processor has the following definition for ACTLR_EL2:

[3:0] PMSTATE: Software-requested core power management state to be used at the next WFI instruction

[4] TRAP_IC_IALLU: When set, an attempt to execute IC IALLU, IC IALLUIS, ICIALLU, or ICIALLUIS in non-secure

EL1 trap to EL2.

[5] TRAP_UCODE_STAT_REGS: When set, an attempt to read/Write the microcode activity and control registers in

non-secure EL1 causes a trap to EL2.

[6] TRAP_BRANCH_PRED_FLUSH: When set, an attempt to write the NV_BRANCH_PRED_FLUSH coprocessor or

system register in non-secure EL1 causes a trap to EL2.

[8] TRAP_NVG_XFACE: When set, an attempt to access the NVIDIA System register generic interface in non-secure

EL0/EL1 modes traps to EL2

[9] DUAL_EXEC_EL2: When set, only dual execution dynamic code sequences are executed at EL2.

[10] TRAP_NVLINK_CFG: When set, attempts to access the NV_NVLINK_CFG system register in all non-secure EL1

modes trap to EL2.

[11] TRAP_FREQ_INFO: When set, attempts to access the frequency request and feedback system registers in all

non-secure EL1 modes trap to EL2.

[12] TRAP_ERX_REGS: When set, attempts to access the NV_ERXPFGCTL_EL1, NV_ERXPFGF_EL1, and

NV_ERXPFGCDN_EL1 system registers in all non-secure EL1 modes trap to EL2.

[13] RESET_RAS_FMON: A write of 1 to this write-only bit re-enables checking for RAS cluster frequency monitoring

errors which are temporarily disabled when detected. A write of 0 is ignored.

[14] TRAP_NV_PERFMON: When set, attempts to access system registers associated with the NVIDIA Performance

Monitoring Extension in all non-secure EL0 and EL1 modes trap to EL2.

[15] TRAP_PM_INFO: When set, attempts to access system registers associated with power management state

information in all non-secure EL1 modes trap to EL2.

[16] TRAP_NV_Cache_OP: When set, attempts to access system registers associated with the NVIDIA Cache

operations in all non-secure EL1 modes trap to EL2.

[17] TRAP_TLBI_IS: When set, all inner-shareable TLB invalidation instructions executed in non-secure EL1 modes

trap to EL2.

[18] TRAP_DSB: When set, all DSB instructions executed in non-secure EL0 and EL1 modes trap to EL2.

[19] DUAL_EXEC_EL0_OVR: When set, the ACTLR_EL1.DUAL_EXEC_EL0 bit does not control whether optimized

translations are executed in dual execution mode in EL0. Instead, the ACTLR_EL2.DUAL_EXEC_EL0_HW_VAL bit

controls this functionality. When clear, the ACTLR_EL1.DUAL_EXEC_EL0 bit has its defined behavior.

[20] DUAL_EXEC_EL0_HW_VAL: When the ACTLR_EL2.DUAL_EXEC_EL0_OVR bit is set, this bit controls whether

optimized translations are executed in dual execution mode in EL0 (1: dual execution mode, 0: normal). When the

ACTLR_EL2.DUAL_EXEC_EL0_OVR bit is cleared, this bit has no functional affect on the machine.

[21] DUAL_EXEC_EL0_RD_VAL: When the ACTLR_EL2.DUAL_EXEC_EL0_OVR bit is set, the value of this bit is

returned on a Read of ACTLR_EL1.DUAL_EXEC_EL0 in non-secure EL1. Additionally, when a Write to ACTLR_EL1.

DUAL_EXEC_EL0 occurs in non-secure EL1, if the value to be written does not match the value of this bit, there is a

trap to EL2.

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[22] DUAL_EXEC_EL1_OVR: When set, the ACTLR_EL1.DUAL_EXEC_EL1 bit does not control whether optimized

translations are executed in dual execution mode in EL1. Instead, the ACTLR_EL2.DUAL_EXEC_EL1_HW_VAL bit

controls this functionality. When clear, the ACTLR_EL1.DUAL_EXEC_EL1 bit has its defined behavior.

[23] DUAL_EXEC_EL1_HW_VAL: When the ACTLR_EL2.DUAL_EXEC_EL1_OVR bit is set, this bit controls whether

optimized translations are executed in dual execution mode in EL1 (1: dual execution mode, 0: normal). When the

ACTLR_EL2.DUAL_EXEC_EL1_OVR bit is cleared, this bit has no functional affect on the machine.

[24] DUAL_EXEC_EL1_RD_VAL: When the ACTLR_EL2.DUAL_EXEC_EL1_OVR bit is set, the value of this bit is

returned on a Read of ACTLR_EL1.DUAL_EXEC_EL1 in non-secure EL1. Additionally, when a Write to ACTLR_EL1.

DUAL_EXEC_EL1 occurs in non-secure EL1, if the value to be written does not match the value of this bit, there is a

trap to EL2.

[25] EL1_PMSTATE_IGNORE_WRITE: When set, direct Writes to ACTLR_EL1.PMSTATE in non-secure EL1 are

ignored (the value of PMSTATE is not changed). When clear, direct Writes to ACTLR_EL1.PMSTATE in non-secure

EL1 occur normally.

[26] DIS_MD_EL2: When set, speculative memory disambiguation is disabled at EL2. When cleared, memory

disambiguation operates normally in EL2.

[27] DIS_MD_EL0_OVERRIDE: When set, the ACTLR_EL0.DIS_MD_EL0 bit does not control whether speculative

memory disambiguation is used in non-secure EL0. Instead, the ACTLR_EL2.DIS_MD_EL0_HW_VAL bit controls

this functionality. When clear, the ACTLR_EL0.DIS_MD_EL0 bit has its defined behavior.

[28] DIS_MD_EL0_HW_VAL: When the ACTLR_EL2.DIS_MD_EL0_OVERRIDE bit is set, this bit controls whether

speculative memory disambiguation is used in non-secure EL0 (1 – no MD, 0 – normal). When the ACTLR_EL2.

DIS_MD_EL0_OVERRIDE bit is cleared, this bit has no functional affect on the machine.

[29] DIS_MD_EL0_READ_VAL: When the ACTLR_EL2.DIS_MD_EL0_OVERRIDE bit is set, the value of this bit is

returned on a read of ACTLR_EL0.DIS_MD_EL0 in non-secure EL0. Additionally, when a write to ACTLR_EL0.

DIS_MD_EL0 occurs in non-secure EL0, if the value to be written does not match the value of this bit, there is a trap

to EL2.

[30] DIS_MD_EL1_OVERRIDE: When set, the ACTLR_EL1.DIS_MD_EL1 bit does not control whether speculative

memory disambiguation is used in non-secure EL1. Instead, the ACTLR_EL2.DIS_MD_EL1_HW_VAL bit controls

this functionality. When clear, the ACTLR_EL1.DIS_MD_EL1 bit has its defined behavior.

[31] DIS_MD_EL1_HW_VAL: When the ACTLR_EL2.DIS_MD_EL1_OVERRIDE bit is set, this bit controls whether

speculative memory disambiguation is used in non-secure EL1 (1 – no MD, 0 – normal). When the ACTLR_EL2.

DIS_MD_EL1_OVERRIDE bit is cleared, this bit has no functional affect on the machine.

[32] DIS_MD_EL1_READ_VAL: When the ACTLR_EL2.DIS_MD_EL1_OVERRIDE bit is set, the value of this bit is

returned on a read of ACTLR_EL1.DIS_MD_EL1 in non-secure EL1. Additionally, when a write to ACTLR_EL1.

DIS_MD_EL1 occurs in non-secure EL1, if the value to be written does not match the value of this bit, there is a trap

to EL2.

[33] DIS_SSB_EL2: When set, speculative store buffering is disabled at EL2. When cleared, speculative store

buffering operates normally in EL2.

[34] DIS_SSB_EL0_OVERRIDE: When set, the ACTLR_EL0.DIS_SSB_EL0 bit does not control whether speculative

store buffering is used in non-secure EL0. Instead, the ACTLR_EL2.DIS_SSB_EL0_HW_VAL bit controls this

functionality. When clear, the ACTLR_EL0.DIS_SSB_EL0 bit has its defined behavior.

[35] DIS_SSB_EL0_HW_VAL: When the ACTLR_EL2.DIS_SSB_EL0_OVERRIDE bit is set, this bit controls whether

speculative store buffering is used in non-secure EL0 (1 – no SSB, 0 – normal). When the ACTLR_EL2.

DIS_SSB_EL0_OVERRIDE bit is cleared, this bit has no functional affect on the machine.

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[36] DIS_SSB_EL0_READ_VAL: When the ACTLR_EL2.DIS_SSB_EL0_OVERRIDE bit is set, the value of this bit is

returned on a read of ACTLR_EL0.DIS_SSB_EL0 in non-secure EL0. Additionally, when a write to ACTLR_EL0.

DIS_SSB_EL0 occurs in non-secure EL0, if the value to be written does not match the value of this bit, there is a trap

to EL2.

[37] DIS_SSB_EL1_OVERRIDE: When set, the ACTLR_EL1.DIS_SSB_EL1 bit does not control whether speculative

store buffering is used in non-secure EL1. Instead, the ACTLR_EL2.DIS_SSB_EL1_HW_VAL bit controls this

functionality. When clear, the ACTLR_EL1.DIS_SSB_EL1 bit has its defined behavior.

[38] DIS_SSB_EL1_HW_VAL: When the ACTLR_EL2.DIS_SSB_EL1_OVERRIDE bit is set, this bit controls whether

speculative store buffering is used in non-secure EL1 (1 – no SSB, 0 – normal). When the ACTLR_EL2.

DIS_SSB_EL1_OVERRIDE bit is cleared, this bit has no functional affect on the machine.

[39] DIS_SSB_EL1_READ_VAL: When the ACTLR_EL2.DIS_SSB_EL1_OVERRIDE bit is set, the value of this bit is

returned on a read of ACTLR_EL1.DIS_SSB_EL1 in non-secure EL1. Additionally, when a write to ACTLR_EL1.

DIS_SSB_EL1 occurs in non-secure EL1, if the value to be written does not match the value of this bit, there is a trap

to EL2.

For details on PMSTATE, see the ACTLR_EL1 definition.

HACR_EL2

The Carmel processor implements HACR_EL2 as Read-as-zero, Write-ignored.

ACTLR_EL3

The Carmel processor has the following definition for ACTLR_EL3:

[3:0] PMSTATE: Software-requested core power management state to be used at the next WFI instruction

[5:4] Reserved

[6] NV_MDCR_EL3_SPME: When set, events are allowed to be counted in the NVIDIA-specific Performance

Monitors extension.

[7] TRAP_UCODE_STAT_REGS: When set, an attempt to read/write the microcode activity and control registers in

EL1/2 causes a trap to EL3.

[8] TRAP_NVG_XFACE: When set, an attempt to access the NVIDIA System register generic interface in any mode

other than EL3T/EL3H traps to EL3

[9] DUAL_EXEC_EL3: When set, only dual execution dynamic code sequences are executed at EL3.

[10] TRAP_NVLINK_CFG: When set, attempts to access the NV_NVLINK_CFG system register in any mode other

than EL3T/EL3H traps to EL3.

[11] TRAP_FREQ_INFO: When set, attempts to access the frequency request and feedback system registers in any

mode other than EL3T/EL3H traps to EL3.

[12] TRAP_ERX_REGS: When set, attempts to access the NV_ERXPFGCTL_EL1, NV_ERXPFGF_EL1, and

NV_ERXPFGCDN_EL1 system registers in any mode other than EL3T/EL3H traps to EL3.

[13] RESET_RAS_FMON: A write of 1 to this write-only bit re-enables checking for RAS cluster frequency monitoring

errors which are temporarily disabled when detected. A write of 0 is ignored.

[14] TRAP_NV_PERFMON: When set, attempts to access system registers associated with the NVIDIA Performance

Monitoring Extension in any mode other than EL3T/EL3H traps to EL3.

[15] TRAP_PM_INFO: When set, attempts to access system registers associated with power management state

information in any mode other than EL3T/EL3H traps to EL3.

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[16] TRAP_NV_Cache_OP: When set, attempts to access system registers associated with the NVIDIA Cache

operations in any mode other than EL3T/EL3H traps to EL3.

[17] DIS_MD_EL3: When set, speculative memory disambiguation is disabled at EL3. When cleared, speculative

memory disambiguation operates normally in EL3.

[18] DIS_SSB_EL3: When set, speculative store buffering is disabled at EL3. When cleared, speculative store

buffering operates normally in EL3.

AFSR0_EL1 and AFSR1_EL1

The Carmel processor implements AFSR0_EL1 and AFSR1_EL1 as Read-as-zero, Write-ignored.

AFSR0_EL3 and AFSR1_EL3

The Carmel processor implements AFSR0_EL3 and AFSR1_EL3 as Read-as-zero, Write-ignored.

ESR_EL1 and ESR_EL3

The Carmel processor implements ESR_EL1 and ESR_EL3 as specified in the ARMv8 architecture.

Note that for external aborts, the ISS contains the EA field which can be used to differentiate between external

aborts. The Carmel processor does not use this bit to differentiate between external aborts and so it is always 0

on an external abort.

IFSR32_EL2

The Carmel processor implements IFSR32_EL2 as specified in the ARMv8 architecture.

Note that for external aborts, the ExT field is defined which can be used to differentiate between external aborts.

The Carmel processor does not use this bit to differentiate between external aborts and so it is always 0 on an

external abort.

AFSR0_EL2 and AFSR1_EL2

The Carmel processor implements AFSR0_EL2 and AFSR1_EL2 as Read-as-zero, Write-ignored.

ESR_EL2

The Carmel processor implements ESR_EL2 as specified in the ARMv8 architecture.

Note that for external aborts, the ISS contains the EA field which can be used to differentiate between external

aborts. The Carmel processor does not use this bit to differentiate between external aborts and so it is always 0

on an external abort.

AMAIR_EL1, AMAIR_EL2, and AMAIR_EL3

The Carmel processor implements AMAIR0_EL1, AMAIR0_EL2, and AMAIR_EL3 as read-as-zero, Write

ignored.

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NVCCSIDR0_EL1 and NVCCSIDR1_EL1

The Carmel processor Caches are not able to be enumerated correctly in the ARMv8 defined CCSIDR_EL1

The NVCCSIDR0_EL1 register has the following format:

[2:0] Reserved: Read-as-0

[12:3] Associativity: Number of ways in the "temporal" Cache structure minus 1

[27:13] NumSets: Number of sets in the "temporal" Cache structure minus 1

[31:28] Reserved: Read-as-0

The NVCCSIDR1_EL1 register has the following format:

[0] Implemented: When set, there are "temporal" and "non-temporal" Cache structures from a Cache blocking

perspective. When cleared, only the "temporal" Cache structure are relevant from a Cache blocking perspective.

[1] Common: When set, the "non-temporal" Cache structure is physically a subset of the sets/ways in the "temporal"

Cache structure. When cleared, the "non-temporal" Cache structure is physically separate from the "temporal" Cache

structure

[2] Reserved: Read-as-0

[12:3] Associativity: Number of ways in the "non-temporal" Cache structure minus 1

[27:13] NumSets: Number of sets in the "non-temporal" Cache structure minus 1

[31:28] Reserved: Read-as-0

Similar to the CCSIDR_EL1 register, the Cache level is selected through the value in the CSSELR_EL1

NVCCSIDR0_EL1 is read using MRS 3, 0, C15, C1, 0.

NVCCSIDR1_EL1 is read using MRS 3, 0, C15, C1, 1.

These registers are accessible at EL1/2/3 and Read-only.

CSSELR 1 (L1 I-Cache) NVCCSIDR0_EL1 NVCCSIDR1_EL1

NumSets 0x1ff (512 sets) 0x0

Associativity 0x3 (4 ways) 0x0

Common N/A 0x0

Implemented N/A 0x0

CSSELR 0 (L1 D-Cache) NVCCSIDR0_EL1 NVCCSIDR1_EL1

NumSets 0xff (256 sets) 0xf (16 sets)

Associativity 0x3 (4 ways) 0x3 (4 ways)

Common N/A 0x0

Implemented N/A 0x1

CSSELR 2 (L2 Cache) NVCCSIDR0_EL1 NVCCSIDR1_EL1

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CSSELR 1 (L1 I-Cache) NVCCSIDR0_EL1 NVCCSIDR1_EL1

NumSets 0x7ff (2048 sets) 0x0 (1 set)

Associativity 0xf (16 ways) 0x7f (128 ways)

Common N/A 0x0

Implemented N/A 0x1

CSSELR 4 (L3 Cache) NVCCSIDR0_EL1 NVCCSIDR1_EL1

NumSets 0xffff (4096 sets) 0x0

Associativity 0xf (16 ways) 0x0

Common N/A 0x0

Implemented N/A 0x0

CSSELR 3,5-15 0x0 0x0

NVMSTAT0_EL1, NVMSTAT1_EL1, and NVBGALLOWED_EL1

The Carmel processor has a microcode layer that can work either by pre-empting the current ARM instruction

execution ("foreground execution") or by delaying entry into a requested power state ("background execution").

The NVMSTAT0_EL1 and NVMSTAT1_EL1 registers allow ARM software to determine how much time the

microcode layer is spending in foreground execution and background execution. The NVBGALLOWED_EL1

basis.

Note: The NVBGALLOWED_EL1 register is shared across all Carmel cores, so ARM software must handle the

coordination of accesses among the eight cores. The NVMSTAT0_EL1 and NVMSTAT1_EL1 registers are per

core.

In the following definitions, time is measured in system counter cycles (12 MHz ~ 48 MHz).

A Read of the register causes the related values to be "snapshot" into the NVMSTAT1_EL1 NVMSTAT0_EL1

NVMSTAT1_EL1 to be reset back to 0 and counting immediately begins again.

The register is defined as follows:NVMSTAT0_EL1

[31:0] PG: Time spent physically power gated for this core since the last statistics register reset.

[63:32] Total: Total elapsed time for this core since the last statistics register reset.

The register is defined as follows:NVMSTAT1_EL1

[31:0] BG: Time spent doing microcode background execution for this core since the last statistics register reset.

[63:32] FG: Time spent doing microcode foreground execution for this core since the last statistics register reset.

The register is defined as follows:NVBGALLOWED_EL1

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[0] BG_ALLOWED_SET_CORE0: When a 1 is written to this Write-only bit, background execution is requested to be

allowed on core 0.

[1] BG_ALLOWED_SET_CORE1: When a 1 is written to this Write-only bit, background execution is requested to be

allowed on core 1.

[2] BG_ALLOWED_SET_CORE2: When a 1 is written to this Write-only bit, background execution is requested to be

allowed on core 2.

[3] BG_ALLOWED_SET_CORE3: When a 1 is written to this Write-only bit, background execution is requested to be

allowed on core 3.

[4] BG_ALLOWED_SET_CORE4: When a 1 is written to this Write-only bit, background execution is requested to be

allowed on core 4.

[5] BG_ALLOWED_SET_CORE5: When a 1 is written to this Write-only bit, background execution is requested to be

allowed on core 5.

[6] BG_ALLOWED_SET_CORE6: When a 1 is written to this Write-only bit, background execution is requested to be

allowed on core 6.

[7] BG_ALLOWED_SET_CORE7: When a 1 is written to this Write-only bit, background execution is requested to be

allowed on core 7.

[15:8] Reserved: Read-as-0, Writes-ignored.

[16] BG_ALLOWED_CLR_CORE0: When a 1 is written to this Write-only bit, background execution is requested to be

disallowed on core 0.

[17] BG_ALLOWED_CLR_CORE1: When a 1 is written to this Write-only bit, background execution is requested to be

disallowed on core 1.

[18] BG_ALLOWED_CLR_CORE2: When a 1 is written to this Write-only bit, background execution is requested to be

disallowed on core 2.

[19] BG_ALLOWED_CLR_CORE3: When a 1 is written to this Write-only bit, background execution is requested to be

disallowed on core 3.

[20] BG_ALLOWED_CLR_CORE4: When a 1 is written to this Write-only bit, background execution is requested to be

disallowed on core 4.

[21] BG_ALLOWED_CLR_CORE5: When a 1 is written to this Write-only bit, background execution is requested to be

disallowed on core 5.

[22] BG_ALLOWED_CLR_CORE6: When a 1 is written to this Write-only bit, background execution is requested to be

disallowed on core 6.

[23] BG_ALLOWED_CLR_CORE7: When a 1 is written to this Write-only bit, background execution is requested to be

disallowed on core 7.

[31:24] Reserved: Read-as-0, Writes-ignored.

[32:32] BG_ALLOWED_CORE0: When 1, this read-only status bit indicates that core 0 is currently allowed to perform

background execution. When 0, core 0 is not currently allowed to perform background execution.

[33:33] BG_ALLOWED_CORE1: When 1, this Read-only status bit indicates that core 1 is currently allowed to

perform background execution. When 0, core 1 is not currently allowed to perform background execution.

[34:34] BG_ALLOWED_CORE2: When 1, this Read-only status bit indicates that core 2 is currently allowed to

perform background execution. When 0, core 2 is not currently allowed to perform background execution.

[35:35] BG_ALLOWED_CORE3: When 1, this Read-only status bit indicates that core 3 is currently allowed to

perform background execution. When 0, core 3 is not currently allowed to perform background execution.

[36:36] BG_ALLOWED_CORE4: When 1, this Read-only status bit indicates that core 4 is currently allowed to

perform background execution. When 0, core 4 is not currently allowed to perform background execution.

[37:37] BG_ALLOWED_CORE5: When 1, this Read-only status bit indicates that core 5 is currently allowed to

perform background execution. When 0, core 5 is not currently allowed to perform background execution.

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[38:38] BG_ALLOWED_CORE6: When 1, this Read-only status bit indicates that core 6 is currently allowed to

perform background execution. When 0, core 6 is not currently allowed to perform background execution.

[39:39] BG_ALLOWED_CORE7: When 1, this Read-only status bit indicates that core 7 is currently allowed to

perform background execution. When 0, core 7 is not currently allowed to perform background execution.

[63:34] Reserved: Read-as-0, Writes-ignored.

These registers are accessed as follows:

NVMSTAT0_EL1: MRS/MSR 3, 0, C15, C0, 0

NVMSTAT1_EL1: MRS/MSR 3, 0, C15, C0, 1

NVBGALLOWED_EL1: MRS/MSR 3, 0, C15, C0, 2

NV_NVLINK_CFG_EL1

This system register is accessed via MRS/MSR 3, 0, C15, C0, 3. This Read/Write register is used to configure

the NVLink aperture. This register is shared between all cores in the CCPLEX.

[19:0] Specifies the top of the NVLink address range in MiB. (a value of 0x1 would map to an address of

0x100000)

[31] Enable: 1 - NVLink address range is enabled, 0 - NVLink address range is disabled.

The bottom of the NVLink address range is 0x20_0000_0000. The value for the top of the range must be

greater than the bottom of the range. Additionally, the range specified must not overlap with any of the other

address ranges specified in the system. An attempt to write the top of the NVLink address range to a value

which does not meet these criteria will cause an UNDEFINED fault.

NVFREQ_REQ_EL1

This system register is accessed via MRS/MSR 3, 0, C15, C0, 4. This per-core Read/Write register is used to

make frequency requests for the core.

[8:0] NDIV request value

When the clocking switches to the Closed Frequency, Closed Voltage mode, this register is updated with a

value representing the current frequency.

NVFREQ_FEEDBACK_EL1

This system register is accessed via MRS/MSR 3, 0 C15, C0, 5. This per-core Read-only register provides

frequency feedback information, which allows ARM software to determine the average actual frequency a core

has run at over a period of time.

[31:0] PLLP counter: This counter counts at a fixed frequency (408 MHz). This counter wraps on overflow.

[63:32] Core clock counter: This counter counts on every core clock cycle where the core is architecturally

clocking. This counter wraps on overflow.

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ARM software can determine average core frequency by reading this register at the start and end of a time

period, then computing the following:

Time (seconds) = (PLLP_end: PLLP_start) * 408 M

Core cycles = (Core_clk_counter_end: Core_clk_counter_start)

Core frequency = Core cycles/Time (seconds)

Note that due to wrap, the start and end values may have to be adjusted.

NV_CLUSTER_COUNT_EL1

This system register is accessed via MRS/MSR 3, 0 C15, C0, 7. This per-core Read-only register provides

frequency feedback information for the cluster.

[31:0] Cluster clock counter: This counter counts as long as the cluster clock is counting, wraps on overflow,

and resets when the cluster is reset.

[63:32] PLLP counter: This counter counts at a fixed frequency (408 MHz). This counter wraps on overflow.

NVGINDEX_EL1 and NVGDATA_EL1

Carmel has an NVIDIA-specific generic indirect system register interface to allow ARM software to provide

information/commands to the processor hardware/microcode and receive information back from the processor

hardware/microcode. NVGINDEX_EL1 is a 32-bit register which specifies which type of information/command is

being read/written. Reads from and Writes to NVGDATA_EL1 operate on the information/command specified by

NVGINDEX_EL1. NVGINDEX_EL1 values not listed in the table below are reserved. Bits in NVGDATA_EL1 not

specified below are reserved and should not be written to any value other than 0.

NVGINDEX_E

Name NVGDATA_EL1 Description

0 VERSION [31:0]

Holds the major version of the NVG interface.

Differing major versions are not guaranteed to be backwards compatible.

[63:32]

Holds the minor version of the NVG interface.

Increments of the minor version indicate new functionality, but no fundamental change to existing

behavior.

1 POWER_P

ERF

[0]

Performance Per Watt Mode.

0: optimize for the best absolute performance.

1: optimize for the best performance per watt.

The recommended usage is to set this bit to 0 when running at Fmax and set it to 1 otherwise. Resets to

0. This setting is per-core.

POWER_M

ODES

[0]

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NVGINDEX_E

Name NVGDATA_EL1 Description

Low Battery.

When set, provides a hint to optimize for low battery.

[2]

Battery Save.

When set, provides a hint to save battery.

Use of this channel is currently deprecated on Xavier.

3 WAKE_TIM

[31:0]

Time in TSC ticks until the core gets a wake event.

0x0000_0000: The core wakes immediately.

0xffff_ffff: The core does not get a wake event.

This channel information is used with the crossover values and allowed power states to choose a final

power state to be entered during WFI.

CSTATE_I

NFO

For a Write:

[2:0]

CLUSTER_CSTATE.

Specifies the deepest allowed power state for a cluster.

0: CC0 (reset value).

6: CC6.

[6:3]

Reserved.

[7]

UPDATE_CLUSTER.

Set when the CLUSTER_CSTATE value should be updated on an NVGDATA Write.

[15:8]

Reserved.

[19:16]

SYSTEM_CSTATE.

Specifies the deepest allowed power state for the system.

0: SC0 (reset value).

7: SC7.

[22:20]

Reserved.

[23]

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NVGINDEX_E

Name NVGDATA_EL1 Description

UPDATE_SYSTEM.

Set when SYSTEM_CSTATE and SYSTEM_CSTATE_FORCE need to be updated on an NVGDATA

Write.

[30:24]

Reserved.

[31]

UPDATE_WAKE_MASK.

Set when the WAKE_MASK value should be updated on an NVGDATA Write.

[63:32]

WAKE_MASK.

Specifies the architectural interrupts to bring a core out of certain power management states.

Setting all bits to 0 causes a core to be offlined.

Off-lined cores will not architecturally wake up unless they receive a core online request.

Details of the sub-fields of WAKE_MASK are given below.

[63:45]

Reserved.

[44]

IRQOUT.

[43]

FIQOUT.

[42:37]

Reserved.

[36]

SERROR.

[35]

IRQ.

[34]

FIQ.

[33]

vIRQ.

[32]

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NVGINDEX_E

Name NVGDATA_EL1 Description

vFIQ.

For a Read:

[2:0]

CLUSTER_CSTATE.

Update value.

[19:16]

SYSTEM_CSTATE.

Update value.

[63:32]

WAKE_MASK.

Update value.

All other bits in NVGDATA are reserved.

5 CROSSOV

ER_C6_LO

WER_BOU

[31:0]

Expected idle time in TSC ticks where using C6 becomes power efficient.

6 CROSSOV

ER_CC6_L

OWER_BO

UND

[31:0]

Expected idle time in TSC ticks where using CC6 becomes power efficient.

Shared between 2 cores in a cluster.

10 CSTATE_S

TAT_QUER

Y_REQUE

This channel holds the index to the value read in the CSTATE_STAT_QUERY_VALUE channel.

[3:0] Unit ID. One of core or cluster.

[15:4] Statistic ID.

1: SC7 entries (Unit ID is ignored)

6: CC6 entries (Unit ID holds the cluster ID)

10: C6 entries (Unit ID holds the core ID)

14: C7 entries (Unit ID holds the core ID)

32: SC7 residency sum (Unit ID is ignored)

41: CC6 residency sum (Unit ID holds the cluster ID)

51: C6 residency sum (Unit ID holds the core ID)

56: C7 residency sum (Unit ID holds the core ID)

"residency sum" is the total time spent in the power state.

11 CSTATE_S

TAT_QUER

Y_VALUE

[63:0]

Read-only counter selected by CSTATE_STAT_QUERY_REQUEST

20 NUM_COR

[3:0]

Read-only value describing the number of cores which can be enabled in the current SKU.

[2:0]

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NVGINDEX_E

Name NVGDATA_EL1 Description

UNIQUE_L

OGICAL_ID

The logical ID number of the core which makes the request.

22 LOGICAL_

TO_PHYSI

CAL_MAPP

ING

[3:0]

LCORE0_PCORE_ID.

The physical core number of logical core 0.

[7:4]

LCORE1_PCORE_ID.

The physical core number of logical core 1.

[11:8]

LCORE2_PCORE_ID.

The physical core number of logical core 2.

[15:12]

LCORE3_PCORE_ID.

The physical core number of logical core 3.

[19:16]

LCORE4_PCORE_ID.

The physical core number of logical core 4.

[23:20]

LCORE5_PCORE_ID.

The physical core number of logical core 5.

[27:24]

LCORE6_PCORE_ID.

The physical core number of logical core 6.

[31:28]

LCORE7_PCORE_ID.

The physical core number of logical core 7.

23 LOGICAL_

TO_MPIDR

On write:

[2:0]

LCORE_ID.

The logical core in the system for which an MPIDR mapping should be returned on read.

On read:

[31:0]

The value of MPIDR for the LCORE_ID previously written to this register.

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NVGINDEX_E

Name NVGDATA_EL1 Description

42 SHUTDOW

On Write:

[0]

REBOOT.

0: a shutdown message is sent to the BPMP.

1: a reboot message is sent to the BPMP.

Reads always return 0.

43 IS_SC7_AL

LOWED

On read:

[0]

IS_SC7_ALLOWED.

0: The CCPLEX is not ready to enter SC7.

1: The CCPLEX is ready to enter SC7 and puts all other cores but the requesting core into a state where

SC7 can be entered.

In this state, the other cores will not be able to wake up until after SC7 has been entered, so the final

core must enter SC7 for correct system behavior.

44 ONLINE_C

ORE

On Write:

[3:0]

CORE_ID.

Specifies the core to be brought back online (0-7).

Reads from this Write-only channel cause an UNDEFINED fault.

45 CC3_CTRL Enable/Disable Auto-CC3.

[7:0]

Holds the frequency request value when in Auto-CC3.

[31]

Enable bit for Auto-CC3.

CCPLEX_C

ACHE_CO

NTROL

[4:0]

GPU_WAYS.

Specifies the number of ways in the L3 Cache that the GPU can allocate into.

The reset value is 0.

The maximum value is 16.

Writing a value greater than 16 causes a RAS error.

[12:8]

GPU_ONLY_WAYS.

Specifies the number of ways in the L3 Cache that are exclusively reserved for GPU allocation.

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NVGINDEX_E

Name NVGDATA_EL1 Description

The reset value is 0.

The maximum value is 16.

Writing a value greater than 16 or the value specified in bits 4:0 causes a RAS error.

50 UPDATE_C

CPLEX_GS

This Write-only channel causes CCPLEX registers containing memory carveout values to be updated

from the values in the associated Memory Controller registers.

A Read from this channel causes an UNDEFINED fault.

[15:0]

Specifies the memory carveout registers to be updated, with the following values:

0: All CCPLEX memory carveout registers.

1 ~ 31: Individual GSCs.

32: TrustZone DRAM carveout registers.

33: NVLink carveout registers.

34: Sideband Shim (SBS) carveout registers.

35: Video Protection Region (VPR) carveout registers.

53 HSM_ERR

OR_CONT

ROL

On Write:

[0]

UNCORR.

0: No effect.

1: Clears the CCPLEX to HSM uncorrectable error signal.

[1]

CORR.

0: No effect.

1: clears the CCPLEX to HSM correctable error signal.

On Read:

[0]

UNCORR.

CCPLEX to HSM uncorrectable error signal value.

[1]

CORR.

CCPLEX to HSM correctable error signal value.

SECURITY

_CONFIG

There are two modes for secure Write behavior in the CCPLEX:

(1) Secure Writes to write both secure and non-secure address regions (legacy behavior).

(2) Secure Writes to write only secure address regions (strict checking).

On Read:

[0]

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NVGINDEX_E

Name NVGDATA_EL1 Description

Strict checking enabled value.

0: disabled/legacy behavior.

1: enabled.

[1]

Strict checking locked.

0: Writes to this channel take effect.

1: Writes to this channel are ignored.

On Write:

[0]

Enable strict checking.

0: Disabled/legacy behavior.

1: Enabled.

[1]

Lock this channel.

0: No action.

1: Lock.

Note that once this channel is locked, it is only unlocked on a CCPLEX reset. Strict checking is disabled

on a CCPLEX reset.

55 DEBUG_C

ONFIG

[0]

0: A RAS error does not cause entry to Debug state.

1: a RAS error causes entry to Debug state.

This bit resets to 0.

This channel register is shared between all cores in the CCPLEX.

56 DDA_SNO

C_MCF

DDA registers provide quality of service support. Details on the fields and programming model will be

added in a future revision.

57 DDA_MCF_

ORD1

DDA registers provide quality of service support. Details on the fields and programming model will be

added in a future revision.

58 DDA_MCF_

ORD2

DDA registers provide quality of service support. Details on the fields and programming model will be

added in a future revision.

59 DDA_MCF_

ORD3

DDA registers provide quality of service support. Details on the fields and programming model will be

added in a future revision.

60 DDA_MCF_

ISO

DDA registers provide quality of service support. Details on the fields and programming model will be

added in a future revision.

61 DDA_MCF_

SISO

DDA registers provide quality of service support. Details on the fields and programming model will be

added in a future revision.

62 DDA_MCF_

NISO

DDA registers provide quality of service support. Details on the fields and programming model will be

added in a future revision.

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NVGINDEX_E

Name NVGDATA_EL1 Description

63 DDA_MCF_

NISO_REM

OTE

DDA registers provide quality of service support. Details on the fields and programming model will be

added in a future revision.

64 DDA_L3CT

RL_ISO

DDA registers provide quality of service support. Details on the fields and programming model will be

added in a future revision.

65 DDA_L3CT

RL_SISO

DDA registers provide quality of service support. Details on the fields and programming model will be

added in a future revision.

66 DDA_L3CT

RL_NISO

DDA registers provide quality of service support. Details on the fields and programming model will be

added in a future revision.

67 DDA_L3CT

RL_NISO_

REMOTE

DDA registers provide quality of service support. Details on the fields and programming model will be

added in a future revision.

68 DDA_L3CT

RL_L3FILL

DDA registers provide quality of service support. Details on the fields and programming model will be

added in a future revision.

69 DDA_L3CT

RL_L3WR

DDA registers provide quality of service support. Details on the fields and programming model will be

added in a future revision.

70 DDA_L3CT

RL_RSP_L

3RD_DMA

DDA registers provide quality of service support. Details on the fields and programming model will be

added in a future revision.

71 DDA_L3CT

RL_RSP_M

CFRD_DM

DDA registers provide quality of service support. Details on the fields and programming model will be

added in a future revision.

72 DDA_L3CT

RL_GLOBA

DDA registers provide quality of service support. Details on the fields and programming model will be

added in a future revision.

73 DDA_L3CT

RL_LL

DDA registers provide quality of service support. Details on the fields and programming model will be

added in a future revision.

74 DDA_L3CT

RL_L3D

DDA registers provide quality of service support. Details on the fields and programming model will be

added in a future revision.

75 DDA_L3CT

RL_FCM_R

DDA registers provide quality of service support. Details on the fields and programming model will be

added in a future revision.

76 DDA_L3CT

RL_FCM_

DDA registers provide quality of service support. Details on the fields and programming model will be

added in a future revision.

77 DDA_SNO

C_GLOBAL

_CTRL

DDA registers provide quality of service support. Details on the fields and programming model will be

added in a future revision.

DDA registers provide quality of service support. Details on the fields and programming model will be

added in a future revision.

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NVGINDEX_E

Name NVGDATA_EL1 Description

DDA_SNO

C_CLIENT_

REQ_CTRL

79 DDA_SNO

C_CLIENT_

REPLENIS

H_CTRL

DDA registers provide quality of service support. Details on the fields and programming model will be

added in a future revision.

80 RT_SAFE_

MASK

[7:0]

CORE_MASK.

Each bit set in the mask indicates a logical core number which should behave as real-time cores and

obey behavioral limits set by RT_WINDOW_US and RT_FWD_PROGRESS_US. Initial value is 0.

81 RT_WINDO

W_US

[31:0]

Defines a number of microseconds which constitute a “window” which should be monitored for ARM

forward progress.

The window will be subdivided internally by the microcode in an implementation-defined way. When

RT_SAFE_MASK is set to a non-zero value, RT_WINDOW_US must be greater than

RT_FWD_PROGRESS_US. The microcode will enforce that at least RT_FWD_PROGRESS_US of

ARM forward progress occur within every window of size RT_WINDOW_US. Initial value is 0.

82 RT_FWD_P

ROGRESS

_US

[31:0]

On a write, defines a number of microseconds of forward progress which are the minimum amount of

forward progress allowed within the current value of RT_WINDOW_US for any logical core which has a

corresponding bit set in RT_SAFE_MASK. Initial value is 0.

NV_ERXPFGCTL_EL1

This system register is accessed using MRS/MSR 3, 0, C15, C1, 4. This register is used to inject RAS errors for

software testing.

[0] OF: Overflow flag control for the injected error. 1: set ERR<n>STATUS.OF to 1 on an injected error, 0:

Leave ERR<n>STATUS.OF unchanged on an injected error.

[1] UC: Uncontainable error generation enable. 1: an error of this type can be generated, 0: an error of this type

can't be generated.

[6] CE: Corrected error generation enable. 1: an error of this type can be generated, 0: an error of this type can't

be generated.

[30] R: Restart. Controls if the error generation counter restarts from the countdown value or stops upon

reaching 0. 1: On reaching 0, the error generation counter is restarted from the countdown value, 0: On

reaching 0, the error generation counter stops.

[31] CDNEN: Countdown enable. 1: The error generation counter is enabled. On a Write of 1, the error

generation counter is set to the countdown value. 0: The error generation counter is disabled.

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NV_ERXPFGF_EL1

This Read-only system register is accessed using MRS 3, 0, C15, C1, 5. This register documents support for

injecting RAS errors for software testing.

[0] OF: Overflow flag. This bit always returns 1, indicating that the OF flag setting on injected error can be

controlled via NV_ERXPFGCTL_EL1.OF.

[1] UC: Uncontainable error generation. This bit always returns 1, indicating that uncontainable uncorrectable

errors can be generated.

[6] CE: Corrected error generation. This bit always returns 1, indicating that non-specific corrected errors can be

generated.

[30] R: Restart. This bit always returns 1, indicating the error generation counter restart mode is supported.

NV_ERXPFGCDN_EL1

This system register is accessed using MRS/MSR 3, 0, C15, C1, 6. This register is used to inject RAS errors for

software testing.

[31:0] CDN: Countdown value. This register holds the countdown value which is written into the error generation

counter for cases specified in the description of the NV_ERXPFGCTL_EL1 system register.

NV_PMENTRY_START_TS_EL1

This system register is accessed using MRS/MSR 3, 0, C15, C3, 0. This register provides the timestamp

counter value at the start of entry into the last power management state.

[31:0] Timestamp counter value

NV_PMENTRY_END_TS_EL1

This system register is accessed using MRS/MSR 3, 0, C15, C3, 1. This register provides the timestamp

counter value at the completion of entry into the last power management state.

[31:0] Timestamp counter value

NV_PMEXIT_START_TS_EL1

This system register is accessed using MRS/MSR 3, 0, C15, C3, 2. This register provides the timestamp

counter value at the start of exit from the last power management state.

[31:0] Timestamp counter value

NV_PMEXIT_END_TS_EL1

This system register is accessed using MRS/MSR 3, 0, C15, C3, 3. This register provides the timestamp

counter value at the completion of exit from the last power management state.

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[31:0] Timestamp counter value

NV_LAST_PMSTATE_EL1

This system register is accessed using MRS/MSR 3, 0, C15, C3, 4. This per-core register holds information

about the last power management state architecturally entered and exited.

[3:0]: Core entry power state, using the same encoding as ACTLR.PMSTATE

[6:4]: Cluster entry power state, using the same encoding as the CSTATE_INFO channel in the NVGINFO

/NVGDATA interface.

[19:16]: Core exit power state, using the same encoding as ACTLR.PMSTATE

[22:20]: Cluster exit power state, using the same encoding as the CSTATE_INFO channel in the NVGINFO

/NVGDATA interface.

Note that the values for the entry and exit fields may be different. For example, a core may enter the C6 power

state on the architectural WFI instruction, but background work may occur on the core and then put the core

into a C1 state. So the entry power state would be C6, but the exit power state would be C1 because the

latencies being measured are with respect to the architectural entry latency and the architectural exit latency.

NV_Cache_CLEAN_EL1, NV_Cache_INVAL_DATA_EL1, NV_Cache_INVAL_ALL_EL1

These Read-only system registers are accessed using MRS 3, 0, C15, C3, 5/6/7.

These system registers implement the following CCPLEX level Cache flush operations:

Clean

Clean and invalidate data (clean and invalidate the data Caches but not necessarily the instruction Caches)

Clean and invalidate all (clean and invalidate both instruction and data Caches)

Control does not pass to the next instruction unless one of the following occurs:

The requested Cache flush begins and completes. In this case, the destination register gets the value of 1.

An architectural interrupt which is allowed to be taken in the current processor state is seen. In this case, the

destination register gets the value of 0.

This implementation allows these instructions to be interruptible. Note that if ARM software needs to guarantee

that the instruction will complete, it must guarantee that the instruction is executed in a state where no interrupts

can be taken.

Note that there is dedicated hardware per cluster to perform these Cache flush operations. This implies that if

both cores in a cluster request a Cache flush, then one core will have to wait until the other core’s Cache flush

completes before its own can start. However, it is likely that the second Cache flush operation will be

substantially faster than the first because most data will already be cleaned/invalidated.

NV_BRANCH_PRED_FLUSH

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This write-only system register is accessed using MSR 3, 0, C15, c0, 6. Bit 0 is the only bit with defined

functionality. A write of 1 to bit 0 causes the indirect branch predictor and RSB to be flushed. A write of 0 to bit 0

is ignored. All other bits in this register are reserved and must be written to 0. A write of 1 to any bit other than

bit 0 will cause a RAS error.

AArch32 Register Summary

The following subsections summarize the AArch32 registers implemented in the Carmel processor, their type

(Read-only, Write-only, Read-Write), their reset value, and width. For more detailed descriptions, see the

ARMv8-A architecture reference manual. Note that many AArch32 registers are not implemented because

Carmel only supports AArch32 at EL0 and EL1. Note that registers associated with VFP, Advanced SIMD, the

ARMv8.0 Cryptographic Extension, the ARMv8.2-FP16 feature, and ARM Debug are documented in their

various sections in this document. Also the detailed information on the RAS registers can be found in the RAS

Architecture section.

CP15 CRn==0 Registers

Op1 CRm Op2 Name Type Reset

MIDR

0x4e0f0040

1 CTR RO 0x8444c004

2 TCMTR RO 0x00000000

3 TLBTR RO 0x00000000

4,7 MIDR RO 0x4e0f0040

5 MPIDR RO 0x80000000 | (cluster_id << 8) | core_id

6 REVIDR RO 0x00000000

c1 0 ID_PFR0 RO 0x10000131

1 ID_PFR1 RO 0x00011011

2 ID_DFR0 RO 0x04000088

3 ID_AFR0 RO 0x00011030

4 ID_MMFR0 RO 0x10201105

5 ID_MMFR1 RO 0x40000000

6 ID_MMFR2 RO 0x01260000

7 ID_MMFR3 RO 0x02122211

ID_ISAR0

0x02101110

1 ID_ISAR1 RO 0x13112111

2 ID_ISAR2 RO 0x21232042

3 ID_ISAR3 RO 0x01112131

4 ID_ISAR4 RO 0x00011142

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Op1 CRm Op2 Name Type Reset

5 ID_ISAR5 RO 0x01011121

6 ID_MMFR4 RO 0x00021011

1 c0 0 CCSIDR RO 0x70000002 (CSSELR == 0)

0x20000002 (CSSELR == 1)

0x70000002 (CSSELR == 2)

0x00000000 (CSSELR == 3)

0x50000002 (CSSELR == 4)

0x00000000 (CSSELR >= 5)

1 CLIDR RO 0x0b200123

7 AIDR RO (Microcode build number)

2 c0 0 CSSELR RW 0x00000000

4 c0 0 VPIDR RW 0x4e0f0040 (MIDR_EL1 value)

5 VMPIDR RW 0x80000000 | (cluster_id << 8) | core_id

CP15 CRn==1 Registers

Op1 CRm Op2 Name Type Reset

0 c0 0 SCTLR RW 0x03d50820

1 ACTLR RW 0x00000001

2 CPACR RW 0x00000000

c1 1 SDER RW 0x00000000

2 NSACR RW 0x00000000

c3 1 SDCR RW 0x00000000

CP15 CRn==2 Registers

Op1 CRm Op2 Name Type Reset

0 c0 0 TTBR0 RW 0x00000000

1 TTBR1 RW 0x00000000

2 TTBCR RW 0x00000000

CP15 CRn==3 Registers

Op1 CRm Op2 Name Type Reset

0 c0 0 DACR RW 0x00000000

CP15 CRn==5 Registers

Op1 CRm Op2 Name Type Reset

DFSR

0x00000000

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Op1 CRm Op2 Name Type Reset

1 IFSR RW 0x00000000

c1 0 ADFSR RW 0x00000000 (Writes ignored)

1 AIFSR RW 0x00000000 (Writes ignored)

CP15 CRn==6 Registers

Op1 CRm Op2 Name Type Reset

0 c0 0 DFAR RW 0x00000000

2 IFAR RW 0x00000000

CP15 CRn==7 Registers

Op1 CRm Op2 Name Type Reset

0 c4 0 PAR RW 0x00000000

CP15 CRn==7 System Operations

The Carmel processor supports all of the ARMv8.0, ARMv8.1, and ARMv8.2 System operations that can be

executed at EL0 or EL1 when CRn == 7 and the processor is in AArch32 state. For the definition and details of

these operations, see the ARMv8 documentation.

CP15 CRn==8 System Operations

The Carmel processor supports all of the ARMv8.0, ARMv8.1, and ARMv8.2 System operations that can be

executed at EL0 or EL1 when CRn == 8 and the processor is in the AArch32 state. For the definitions and

details of these operations, see the ARMv8 documentation.

CP15 CRn==9 Registers

Op1 CRm Op2 Name Type Reset

c12

PMCR

0x4e023000

1 PMCNTENSET RW 0x00000000

2 PMCNTENCLR RW 0x00000000

3 PMOVSR RW 0x00000000

4 PMSWINC WO N/A

5 PMSELR RW 0x00000000

6 PMCEID0 RO 0x143f0f3f

7 PMCEID1 RO 0x0000001e

c13

PMCCNTR

0x00000000

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Op1 CRm Op2 Name Type Reset

PMXEVTYPER

PMCCFILTR

0x00000000

2 PMXEVCNTR RW 0x00000000

c14 0 PMUSERENR RW 0x00000000

1 PMINTENSET RW 0x00000000

2 PMINTENCLR RW 0x00000000

3 PMOVSSET RW 0x00000000

CP15 CRn==10 Registers

Op1 CRm Op2 Name Type Reset

0 c2 0 PRRR

MAIR0

0x00000000

1 NMRR

MAIR1

0x00000000

c3 0 AMAIR0 RW 0x00000000 (Writes ignored)

1 AMAIR1 RW 0x00000000 (Writes ignored)

CP15 CRn==12 Registers

Op1 CRm Op2 Name Type Reset

0 c0 0 VBAR RW 0x00000000

c1 0 ISR RO 0x00000000

CP15 CRn==13 Registers

Op1 CRm Op2 Name Type Reset

0 c0 0 FCSEIDR RW 0x00000000

1 CONTEXTIDR RW 0x00000000

2 TPIDRURW RW 0x00000000

3 TPIDRURO RW 0x00000000

4 TPIDRPRW RW 0x00000000

CP15 CRn==14 Registers

Op1 CRm Op2 Name Type Reset

CNTFRQ

0x00000000

c1 0 CNTKCTL RW 0x00000000

CNTP_TVAL

0x00000000

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Op1 CRm Op2 Name Type Reset

1 CNTP_CTL RW 0x00000000

c3 0 CNTV_TVAL RW 0x00000000

1 CNTV_CTL RW 0x00000000

c8 0 PMEVCNTR0 RW 0x00000000

1 PMEVCNTR1 RW 0x00000000

2 PMEVCNTR2 RW 0x00000000

3 PMEVCNTR3 RW 0x00000000

4 PMEVCNTR4 RW 0x00000000

5 PMEVCNTR5 RW 0x00000000

c12 0 PMEVTYPER0 RW 0x00000000

1 PMEVTYPER1 RW 0x00000000

2 PMEVTYPER2 RW 0x00000000

3 PMEVTYPER3 RW 0x00000000

4 PMEVTYPER4 RW 0x00000000

5 PMEVTYPER5 RW 0x00000000

c15 7 PMCCFILTR RW 0x00000000

CP15 CRn==15 Registers

Op1 CRm Op2 Name Type Reset

NV_NVLINK_CFG

0x00000000

4 NVFREQ_REQ RW 0x00000000

5 NVFREQ_FEEDBACK_CORE RO 0x00000000

6 NVFREQ_FEEDBACK_FIXED RO 0x00000000

7 NV_CLUSTER_COUNT RO 0x00000000

C1 0 NVCCSIDR0 RO 0x001fe018 (CSSELR == 0)

0x003fe018 (CSSELR == 1)

0x00ffe078 (CSSELR == 2)

0x00000000 (CSSELR == 3)

0x001fe078 (CSSELR == 4)

0x00000000 (CSSELR >= 5)

1 NVCCSIDR1 RO 0x0001e019 (CSSELR == 0)

0x00000000 (CSSELR == 1)

0x000003f9 (CSSELR == 2)

0x00000000 (CSSELR >= 3)

2 NVGINDEX RW 0x00000000

3 NV_BRANCH_PRED_FLUSH WO N/A

NV_PMENTRY_START_TS

0x00000000

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Op1 CRm Op2 Name Type Reset

1 NV_PMENTRY_END_TS RO 0x00000000

2 NV_PMEXIT_START_TS RO 0x00000000

3 NV_PMEXIT_END_TS RO 0x00000000

4 NV_LAST_PMSTATE RO 0x00000000

5 NV_Cache_CLEAN RO N/A

6 NV_Cache_INVAL_DATA RO N/A

7 NV_Cache_INVAL_ALL RO N/A

64-Bit System Registers

CRm Op1 Name Type Reset

c2 0 TTBR0 RW 0x0000000000000000

1 TTBR1 RW 0x0000000000000000

c7 0 PAR RW 0x0000000000000000

c9 0 PMCCNTR RW 0x0000000000000000

c14 0 CNTPCT RO 0x0000000000000000

1 CNTVCT RO 0x0000000000000000

2 CNTP_CVAL RW 0x0000000000000000

3 CNTV_CVAL RW 0x0000000000000000

4 CNTVOFF RW 0x0000000000000000

c15 0 NVMSTAT0 RW 0x0000000000000000

1 NVMSTAT1 RW 0x0000000000000000

2 NVBGALLOWED RW 0x0000000300000000

3 NVGDATA RW 0x0000000000000000

AArch32 Register Descriptions

For the most part, System registers when the Carmel processor is in the AArch32 state are defined in the

ARMv8 documentation. Note that the Carmel processor does not implement support for EL2 and EL3, and the

ARMv8 documentation specifies registers which are not accessible/implemented unless AArch32 is supported

at EL2 or EL3. This subsection provides further information on Carmel processor System registers, which are

unspecified in the ARMv8 documentation. Additionally, the IMPLEMENTATION defined registers and fields in

registers are specified here.

TCMTR

The Carmel processor in the Xavier series SoC does not implement Tightly Coupled Memory (TCM); thus this

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TLBTR

The TLB implementation in the Carmel processor falls under the definition of a unified TLB, so this register

always returns 0.

MIDR

The Carmel processor has the following MIDR field values:

Implementer: 0x4E ('N')

Variant: 0x0 (This field changes values when programmer visible ISA changes have been added to a product)

Architecture: 0xF (defined by the CPUID scheme)

Primary Part Number: 0x4

Revision: 0x0 (This number reflects the silicon base layer revision)

MPIDR

The Carmel processor has the following MPIDR field values:

U: 0 (multiprocessor system)

MT: 0 (no multi-threading approach)

AFF2: 0

AFF1: Cluster number (0,1, 2, or 3)

AFF0: Core number (0 or 1)

REVIDR

The Carmel processor uses the REVIDR register to specify the metal layer version associated with the silicon

base layer version specified in MIDR.

[7:0] Metal layer version (starts with 0 and increments)

AIDR

The Carmel processor returns a value for AIDR which indicates the microcode revision. All microcode revisions

are unique and a higher value indicates a more recent microcode revision.

CCSIDR

The Carmel processor has the following CCSIDR field values:

CSSELR 0 (L1 Data Cache)

WT/WB/RA/WA: 0x7

NumSets: 0x0

Associativity: 0x0

Linesize: 0x2 (64 byte Cache line)

CSSELR 1 (L1 Instruction Cache)

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WT/WB/RA/WA: 0x2

NumSets: 0x0

Associativity: 0x0

Linesize: 0x2 (64 byte Cache line)

CSSELR 2 (L2 Cache)

WT/WB/RA/WA: 0x7

NumSets: 0x0

Associativity: 0x0

Linesize: 0x2 (64 byte Cache line)

CSSELR 3 (Reserved)

0x00000000

CSSELR 4 (L3 Cache)

WT/WB/RA/WA: 0x5

NumSets: 0x0

Associativity: 0x0

Linesize: 0x2 (64 byte Cache line)

CSSELR >= 5 (Reserved: no further Caches enumerated)

0x00000000

Note that the number of sets and associativity are reported as 1 and 1, respectively, to allow the Cache

manipulation by set/way instructions to work correctly.

CLIDR

The Carmel processor has the following CLIDR field values:

ICB: 0x0 (not disclosed in this mechanism)

LoUU: 0x1 (IL1 and DL1 need to be flushed for self-modifying code to work)

LoC: 0x3 (non-snooping DMA needs to flush through the L3)

LoUIS: 0x1 (IL1 and DL1 need to be flushed for self-modifying code to work)

Ctype4 ~ Ctype7: 0x0 (No Cache)

Ctype3: 0x4 (Unified Cache)

Ctype2: 0x4 (Unified Cache)

Ctype1: 0x3 (Separate instruction and data Caches)

CTR

The Carmel processor has the following CTR field values:

CWG: 0x4 (16 words * 4 bytes/word = 64-byte Cache lines)

ERG: 0x4 (16 words * 4 bytes/word = 64-byte Cache lines)

DminLine: 0x4 (16 words * 4 bytes/word = 64-byte L1 Cache lines)

L1Ip: 0x3 (Physical Index, Physical Tag)

IminLine: 0x4 (16 words * 4 bytes/word = 64-byte L1 Cache lines)

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ID_PFR0

The Carmel processor has the following ID_PFR0 field values:

RAS Extensions Version: 0x1 (Version 1 of RAS extensions present)

State3: 0x0 (No ThumbEE support)

State2: 0x1 (Trivial implementation of Jazelle)

State1: 0x3 (Support Thumb, Thumb2)

State0: 0x1 (ARM support)

ID_PFR1

The Carmel processor has the following ID_PFR1 field values:

GIC cp15 Interface: 0x0 (not supported)

Virtualization Extensions Fractional Field: 0x0 (the Carmel processor implements the full Virtualization Extensions)

Security Extensions Fractional Field: 0x0 (the Carmel processor implements the full Security Extensions)

Generic Timer Support: 0x1 (supported)

Virtualization Extensions: 0x1 (supported)

M profile programmers' model: 0x0 (not supported)

Security Extensions: 0x1 (supports Monitor mode and SMC)

Programmers' model: 0x1 (standard programmers' model supported)

ID_DFR0

The Carmel processor has the following ID_DFR0 field values:

Performance Monitor model, A and R Profiles: 0x4 (support for performance monitor features, version 3 with 16-bit

evtCount field)

Debug model, M profile: 0x0 (not supported)

Memory-mapped trace model: 0x0 (not compatible with v7-A memory map, and memory mapped trace model is not

supported in the Carmel processor)

Coprocessor trace model: 0x0 (not supported)

Memory-mapped debug model, A and R profiles: 0x0 (not supported)

Coprocessor Secure debug model: 0x8 (support for ARMv8.2 Debug architecture with CP14 access)

Coprocessor debug model: 0x8 (support for ARMv8.2 Debug architecture with CP14 access)

ID_AFR0

The Carmel processor defines the ID_AFR0 register as follows:

[3:0] SERROR support: 0x0 (Does not support the SERROR control and logging registers as implemented in the

Carmel processor)

[7:4] Performance monitoring extension: 0x3 (Supports the Performance monitoring extension registers as

implemented in the Carmel processor)

[11:8] NVIDIA Cache Operations: 0x0 (Does not support the NVIDIA-specific Cache flush extension)

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[15:12] NVIDIA Interruptible Cache Operations: 0x1 (Supports the NVIDIA-specific Interruptible Cache Operations

extension)

[19:16] NVIDIA Branch Predictor Operations support: 0x1 (NVIDIA Branch Predictor Operations extension supported,

including the NV_BRANCH_PRED_FLUSH coprocessor register and ACTLR_EL2 trap support)

[31:20] Reserved, Read-as-0

ID_MMFR0

The Carmel processor has the following ID_MMFR0 field values:

Innermost shareability: 0x1 (Implemented with hardware coherency support)

FCSE Support: 0x0 (Not Supported)

Auxiliary registers: 0x2 (ACTLR, AIFSR, and ADFSR are supported)

TCM support: 0x0 (Not Supported)

Shareability levels: 0x1 (Two levels of shareability implemented)

Outermost shareability: 0x1 (Implemented with hardware coherency support)

PMSA support: 0x0 (Not supported)

VMSA support: 0x5 (Support for VMSAv7, including remapping and the access flag, PXN in first level descriptors, and

64-bit translation descriptors)

ID_MMFR1

The Carmel processor has the following ID_MMFR1 field values:

Branch Predictor: 0x4 (For execution correctness, branch predictor requires no flushing at any time)

L1 Cache Test and Clean: 0x0 (None supported)

L1 Unified Cache: 0x0 (None supported)

L1 Harvard Cache: 0x0 (None supported)

L1 Unified Cache Set/Way: 0x0 (None supported)

L1 Harvard Cache Set/Way: 0x0 (None supported)

L1 Unified Cache VA: 0x0 (None supported)

L1 Harvard Cache VA: 0x0 (None supported)

ID_MMFR2

The Carmel processor has the following ID_MMFR2 field values:

Hardware Access Flag: 0x0 (Not supported)

WFI stall: 0x1 (Support for WFI stalling)

Mem barrier: 0x2 (Support for CP15 DSB, ISB, and DMB)

Unified TLB: 0x6 (Support for invalidate all, invalidate by MVA, invalidate by ASID, invalidate by MVA all ASID,

invalidate Hyp entry by MVA, invalidate entire non-secure, non-Hyp, invalidate entire Hyp, TLBIMVALIS,

TLBIMVAALIS, TLBIMVALHIS, TLBIMVAL, TLBIMVAAL, TLBIMVALH, TLBIIPAS2IS, TLBIIPAS2LIS, TLBIIPAS2,

TLBIIPAS2L)

Harvard TLB: 0x0 (Not supported)

L1 Harvard range: 0x0 (Not supported)

L1 Harvard bg prefetch: 0x0 (Not supported)

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L1 Harvard fg prefetch: 0x0 (Not supported)

ID_MMFR3

The Carmel processor has the following ID_MMFR3 field values:

Supersection support: 0x0 (Supersections supported)

Physical memory size (4 bits): 0x2 (40 bits)

Coherent walk: 0x1 (Updates to the translation tables do not require a clean to the point of unification to ensure

visibility by subsequent translation table walks)

Privileged Access Never: 0x2 (Privileged Access Never and AT S1E1RP/S1E1WP instructions supported)

Maintenance broadcast: 0x2 (Cache, TLB and branch predictor operations affect structures according to shareability

and defined behavior of instructions)

BP maintain: 0x2 (Supported branch predictor maintenance operations are Invalidate all branch predictors and

Invalidate branch predictors by MVA)

Cache maintain set/way: 0x1 (Invalidate by set/way, clean by set/way, clean and invalidate by set/way supported)

Cache maintain MVA: 0x1 (invalidate data Cache by MVA, clean data Cache by MVA, clean and invalidate data

Cache by MVA, invalidate instruction Cache by MVA, invalidate all instruction Cache entries)

ID_MMFR4

The Carmel processor has the following ID_MMFR4 field values:

LDM/STM Ordering Behavior Control: 0x0 (LSMAOE and nTLSMD bits not supported)

Hierarchical Permission Disables: 0x2 (Hierarchical Permission Disables supported and Hardware allocation of bits

[62:59] supported)

Common not Private: 0x1 (Common Not Private bit supported)

EL0/1 Execute Never Control at Stage 2: 0x1 (EL0/EL1 execute control distinction at stage2 bit supported)

ACTLR2/HACTLR2: 0x1 (ACTLR2/HACTLR2 supported)

SERROR Interrupt on Speculative Reads: 0x1 (Carmel might generate an SERROR interrupt due to an external abort

on a speculative read)

ID_ISAR0

The Carmel processor has the following ID_ISAR0 field values:

Divide instructions: 0x2 (SDIV and UDIV are supported in Thumb and ARM ISAs)

Debug instructions: 0x1 (BKPT supported)

Coproc Instructions: 0x0 (None implemented, except for instructions separately attributed by the architecture,

including CP15, CP14, Advanced SIMD Extension, and the Floating-point Extension)

CmpBranch Instructions: 0x1 (CBNZ and CBZ are supported)

Bitfield instructions: 0x1 (BFC, BFI, SBFX, and UBFX are supported)

Bitcount instructions: 0x1 (CLZ is supported)

Swap instructions: 0x0 (None supported)

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ID_ISAR1

The Carmel processor has the following ID_ISAR1 field values:

Jazelle instructions: 0x1 (BXJ and the J-bit are supported: trivial implementation of Jazelle)

Interwork instructions: 0x3 (BX, BLX instructions supported, T-bit is supported in PSR, data processing instructions in

ARM ISA with PC as dest and S-bit clear have BX-like behavior)

Immediate instructions: 0x1 (MOVT, MOV with zero-extended 16-bit immediates, Thumb ADD/SUB with zero-

extended 12-bit immediates are supported)

IfThen instructions: 0x1 (IT instructions and the IT bits in the PSRs are supported)

Extend instructions: 0x2 (SXTB, SXTH, UXTB, UXTH, SXTB16, SXTAB, SXTAB16, SXTAH, UXTB16, UXTAB,

UXTAB16, and UXTAH are supported)

Except AR instructions: 0x1 (SRS, RFE, and CPS are supported)

Except instructions: 0x1 (LDM (exception return), LDM (user registers), and STM (user registers) are supported)

Endian instructions: 0x1 (SETEND and the E bit in the PSRs are supported)

ID_ISAR2

The Carmel processor has the following ID_ISAR2 field values:

Reversal instructions: 0x2 (REV, REV16, REVSH, RBIT instructions supported)

PSR AR instructions: 0x1 (MRS/MSR to PSR and exception return forms of data processing instructions supported)

MultU instructions: 0x2 (UMULL, UMLAL, and UMAAL instructions supported)

MultS instructions: 0x3 (SMULL, SMLAL, SMLABB, SMLABT, SMLALBB, SMLALBT, SMLALTB, SMLALTT,

SMLATB, SMLATT, SMLAWB, SMLAWT, SMULBB, SMULBT, SMULTB, SMULTT, SMULSB, SMULWT, SMLAD,

SMLADX, SMLALD, SMLALDX, SMLSD, SMLSDX, SMLSLD, SMLSLDX, SMMLA, SMMLAR, SMMLS, SMMLSR,

SMMUL, SMMULR, SMUAD, SMUADX, SMUSD, and SMUXDX instructions are supported along with the Q bit in the

PSRs)

Mult instructions: 0x2 (MLA and MLS are supported)

MultiAccess instructions: 0x0 (LDM and STM are not interruptible)

MemHint instructions: 0x4 (PLD, PLI, and PLDW supported)

LoadStore instructions: 0x2 (LDRD, STRD, and load-acquire/store-release instructions supported)

ID_ISAR3

The Carmel processor has the following ID_ISAR3 field values:

ThumbEE Extn instructions: 0x0 (None supported)

TrueNOP instructions: 0x1 (True NOP instructions are supported for Thumb/ARM ISAs along with additional NOP-

compatible hints)

ThumbCopy instructions: 0x1 (T1 encoding of the MOV (register) instruction supports a copy from a low register to a

low register)

TabBranch instructions: 0x1 (TBB and TBH are supported)

SynchPrim instructions: 0x2 (LDREX, STREX, CLREX, LDREXB, LDREXH, STREXB, STREXH, LDREXD, and

STREXD instructions are supported)

SVC instructions: 0x1 (SVC is supported)

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SIMD instructions: 0x3 (SSAT, USAT, PKHBT, PKHTB, QADD16, QADD8, QASX, QSUB16,

QSUB8, QSAX, SADD16, SADD8, SASX, SEL, SHADD16, SHADD8, SHASX, HSUB16, SHSUB8, SHSAX, SSAT16,

SSUB16, SSUB8, SSAX, SXTAB16, SXTB16, UADD16, UADD8, UASX, UHADD16, UHADD8, UHASX, UHSUB16,

UHSUB8, UHSAX, UQADD16, UQADD8, UQASX, UQSUB16, UQSUB8, UQSAX, USAD8, USADA8, USAT16,

USUB16, USUB8, USAX, UXTAB16, and UXTB16 instructions are supported and GE[3:0] bits in the PSRs are

supported)

Saturate instructions: 0x1 (QADD, QDADD, QDSUB, and QSUB instructions are supported and the Q bit in the PSRs

is implemented)

ID_ISAR4

The Carmel processor has the following ID_ISAR4 field values:

SWP frac: 0x0 (SWP/SWPB not supported)

PSR M instructions: 0x0 (None supported)

SynchPrim instructions Frac: 0x0 (LDREX, STREX, CLREX, LDREXB, LDREXH, STREXB, STREXH, LDREXD, and

STREXD instructions are supported)

Barriers instructions: 0x1 (DMB, DSB, and ISB instructions supported)

SMC instructions: 0x1 (SMC instruction supported)

Writeback instructions: 0x1 (All write back addressing modes in ARMv7 supported)

WithShifts instructions: 0x4 (All forms of shift options supported)

Unpriv instructions: 0x2 (LDRBT, LDRT, STRBT, STRT, LDRHT, LDRSBT, LDRSHT, and STRHT instructions

supported)

ID_ISAR5

The Carmel processor has the following ID_ISAR5 field values:

RDM: 0x1 (SQRDMLAH and SQRDMLSH supported in AArch32)

CRC32: 0x1 (CRC32/CRC32C instructions implemented)

SHA2: 0x1 (SHA256H, SHA256H2, SHA256SU0, and SHA256SU1 instructions implemented)

SHA1: 0x1 (SHA1C, SHA1P, SHA1M, SHA1H, SHA1SU0, and SHA1SU1 instructions implemented)

AES: 0x2 (AESE, AESD, AESMC, AESIMC, PMULL, and PMULL2 instructions implemented)

SEVL: 0x1 (SEVL implemented to send event local)

CPACR

The Carmel processor implements the following fields in CPACR:

ASEDIS

CP11

CP10

NSACR

The Carmel processor effectively hardcodes the NSACR value as 0x00000C00 since AArch32 is not supported

at EL2 and EL3

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TTBR0/TTBR1

The Carmel processor does not have any IMPLEMENTATION defined functionality associated with the TTBR0.

IMP/TTBR1.IMP bits.

TTBCR

The Carmel processor does not have any IMPLEMENTATION DEFINED functionality associated with bit 30.

DFSR

The Carmel processor does not use the DFSR.ExT bit to differentiate between different types of external abort

errors and will always set this bit to 0 on an external abort.

FCSEIDR

The Carmel processor does not implement Fast Context Switch Extension (FCSE), so this register is Read-as-

zero, Writes ignored.

ACTLR

The Carmel processor implements the following fields in the ACTLR register: