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8 System Components

8.1 Clock and Reset Controller (CAR)

The Clock and Reset Controller (CAR) block contains all the logic needed to control most of the clocks and

resets to the NVIDIA® Xavier series System-on-Chip. The CAR block provides the registers to program the

PLLs and controls most of the clock source programming and clock dividers.

For Xavier clocks and resets are controlled by NVIDIA provided firmware running on BPMP. This

hardware is not documented, and the software documentation should be consulted for details of how

these are controlled.

8.1.1 Reset Controller

Overview

This section describes the reset architecture for the NVIDIA Xavier series System-on-Chip (SoC), including the

reset-associated logic and the system-level reset domains. Asserting any of these domains results in a reset of

the majority of VDD_CORE, CV, CCPLEX and GPU rail logic and, potentially, some or all of the VDD_RTC

logic.

This reset architecture spans multiple modules, such as PMC, CAR, Timers, and BPMP. It also includes the

requirements of the downstream units. This chapter also includes details of unit-level reset generation from

these system-level resets and unit-level reset sources, such as software resets and resets for various power-

management states.

The high-level block diagram for the reset generation logic is shown in the figure below. The reset generation

logic is contained both in PMC and CAR and is a subset of those units.

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Figure 8.1 High Level Reset Diagram

The reset logic has one main input from the external PMIC and one main output back to the external PMIC.

SYS_RESET_N is the reset input to the Xavier from the external PMIC. This reset is asserted when all of the

pre-boot core logic rails from the PMIC are enabled and stable and deasserted when the pre-boot I/O and PLL

rails from the PMIC, the 32-kHz clock, and reference clocks are enabled and stable. This is the only reset

source that asserts all resets from the PMC and CAR. Some register state can persist through the other internal

reset sources. Distribution of SYS_RESET_N is shown in the diagram above. SYS_RESET_N becomes

reset_IB_at the output of the pads block. It is distributed to the PMC for further system reset generation.

Also available on this interface are the watch-dog reset WDT_RESET_OUT* pads. These are sideband reset

request outputs for PMICs that support such a feature. These pads are pin-muxed and are only used one at a

time. By asserting one of these active low outputs (or sending an I C SFT_RST request for PMICs that do not

support this sideband input), it results in the assertion of the SYS_RESET_N to the Xavier.

8.1.2 Clock Controller

Overview

The clocking logic makes use of the following to provide the various clocks in the system, including the

frequency of operation, clock quality, spread, clock gating:

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Sources capable of generating frequencies independently or based on a reference clock – External oscillators, Phase-

Locked Loops (PLLs), and Noise-Aware Frequency Locked Loops (NAFLLs).

Clock manipulation elements – switches, dividers, gates, skippers, trimmers, shapers, etc.

The controls for these elements are present in the clock controller module. These controls may need to be

sequenced in an appropriate manner to ensure that there are no glitches or other clock artifacts in the system.

Features

Key features include the following:

Clock generation for all functional blocks

ASIL-C Clock Monitoring for safety-related clocks

LUT RAM parity for safety-related NAFLL LUTs

8.2 Interrupt Controllers

8.2.1 Overview

This chapter discusses the Xavier Series SoC Interrupt controllers with focus on the mapping of all Interrupts

and the architecture for routing and handling of these Interrupts.

From the perspective of Interrupts, devices like the GPU, Memory Controller, Video Encode/Decode Engines,

functional blocks/clusters, and various I/O modules are the sources of Interrupts; and processors are the sinks

of Interrupts. From the Interrupt source, Interrupts go to the Interrupt controllers, receive prioritization, then get

routed to the appropriate target processor according to the software-defined configuration.

Multiple types of Interrupt controllers are used in Xavier:

ARM GIC-400 for the Carmel cores

for the Cortex-R class coresPL192

Central Legacy Interrupt Controller (LIC).

Masking of the Interrupts is always done at the source of Interrupts whereas removal of Interrupts is performed

at end of the appropriate Interrupt Service Routine (ISR) running on the target processor. This chapter does not

discuss the details related to the masking and removal of Interrupts.

Note: For masking (enabling and disabling) of Interrupts, refer to the individual ARM architecture documents.

Conventions of Units

This TRM chapter follows the IEEE and NIST conventions for multiplying prefixes.

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Among other things, this convention uses an 'i' to indicate the binary convention, and its absence to indicate

decimal. So, 1 KiB is 2 or 1,024 bytes, and 1 KB is 10 or 1,000 bytes. Similarly it uses:

10 3

Mi for 2 and M for 10

20 6

Gi for 2 and G for 10

30 9

Ti for 2 and T for 10

40 12

List of References

This chapter makes the implicit use of the following document available from ARM based on the assumption

that readers are familiar with the ARM Architecture and have access to the documents for reference. Refer to

the ARM website to download the document.

ARM CoreLink GIC-400 Generic Interrupt controller Technical Reference Manual (version r0p1)

http://infocenter.arm.com/help/help/index.jsp?topic=/com.arm.doc.ddi0471b

ARM PrimeCell Vectored Interrupt controller (PL192) Technical Reference Manual

http://infocenter.arm.com/help/topic/com.arm.doc.ddi0273a/DDI0273.pdf

ARM Architecture Reference Manual ARMv8

http://developer.arm.com/docs/ddi0487/latest/arm-architecture-reference-manual-armv8-for-armv8-a-architecture-

profile

Note: ARM refers to the as VIC, but it is always termed as AVIC in this document to avoid confusion with PL192

the VIC (Video Image Compositor) block.

Glossary

Note that different names may end up in the same acronym when the entire Xavier TRM is put in perspective.

The acronyms listed here are within the context of the Interrupt controllers chapter.

Term Definition

AGIC APE GIC (referring to the vGIC in APE)

AON Always ON

APE Audio Processing Engine

AVIC ARM VIC (ARM Cortex-R5 specific)

(Multiple AVIC units can be daisy-chained together to handle more Interrupts than one AVIC unit can.)

AVIC Chain Multiple AVIC units in daisy chain

(The AVIC chains in Xavier's Cortex-R5 clusters all comprise of two AVIC units, namely AVIC0 and AVIC1.)

BPMP Boot and Power management Processor

CIDR CCPLEX Interrupt Disable Register

CTI Cross Trigger Interface

FIR Force Interrupt Register

GIC Generic Interrupt controller (ARM specific)

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Term Definition

GTE Generic Timestamping Engine

HSP Hardware Synchronization Primitives

IH Interrupt Handler (in CCPLEX, including vGIC and Floor-sweeping Redirection logic)

IPI Inter-Process Interrupt

ISR Interrupt Service Routine

LIC Legacy Interrupt Controller, serving only as an aggregator offering no service of any Interrupts

PPI Private Peripheral Interrupt

RAS Reliability, Availability, Serviceability

RCE Real-time Camera Engine

REI RAM Error Interrupt

SBE Single-Bit Error

SCE Safety Cluster Engine

SEI System Error Interrupt

SGI Software Generated Interrupts

SPE Sensor Processing Engine

SPI Shared Peripheral Interrupt

vGIC Virtual Generic Interrupt controller (ARM specific)

VIC Vectored Interrupt controller (ARM specific naming, referred to as AVIC in this document)

Relevant Chapters in the TRM

Address Map

Always-On (AON) Cluster and SPE

Audio Processing Engine (APE)

Boot and Power Management Processor (BPMP)

Clock Controller and Reset (CAR)

CPU Complex (CCPLEX)

Real-time Camera Engine (RCE)

Safety Cluster Engine (SCE)

Specifics in Reading This Chapter

There are eight UART units in Xavier. These eight units are dubbed with either an alphabetical suffix (A, B, C,

D, E, F, G, H) or a numerical suffix (1, 2, 3, 4, 5, 6, 7, 8) throughout its design specification and documentation.

For consistency and the sake of eliminating unnecessary confusion, this chapter uses only the alphabetical

suffix for these UART units, i.e., UARTA, UARTB, UARTC, UARTD, UARTE, UARTF, UARTG, UARTH (which

may be referred to as UART1, UART2, UART3, UART4, UART5, UART6, UART7, UART8 in other specification

and documentation including other parts of this TRM).

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8.2.2 Functional Description

Interrupt Handling Mechanism

There are different types of Interrupt controllers (GIC, vGIC, AVIC, LIC) which receive Interrupts from devices (i.

e., hardware Interrupts) or processors (i.e., software Interrupts including IPI). These different Interrupts are

arbitrated then sent to appropriate target processor(s). For software-related Interrupts, there are different types

of processors:

The Carmel CPU cores in the CCPLEX, receiving their Interrupts from the vGIC (in CCPLEX), an instance of the GIC-

400.

The Cortex-A9 core in the APE, receiving its Interrupts from the AGIC, an instance of the GIC-400.

The Cortex-R5 cores in each of AON, BPMP, RCE, and SCE, receiving their Interrupts from a daisy chain of two ARM

Vectored Interrupt controllers (AVIC), referred to AVIC Chain.

There is distinction between shared and local Interrupts as well. Xavier, however, doesn't make the distinction

between the two. Some Interrupts in Cortex-R5 clusters are local, and have strong affinity with their associated

processors therefore not directly visible outside of the processors clusters.

Shared Interrupts always use the LIC as the first-level routing. And any processor can also initiate by software a

shared Interrupt via a LIC register.

There are a total of 416 hardware Interrupts in Xavier. Interrupt sources are allocated one or more Interrupt

signals based on their requirement. The mapping of sources to Interrupts is specified in the address map for

both local and shared Interrupts.

All Xavier Interrupt controllers support a statically configurable number of Interrupts in steps of 32. The sizes for

the different instances, together with some of their other attributes are shown in the table below.

Table 8.1 Interrupt Controllers and Their Characteristics

Location Type IP

[1]

[2]

Size

[3]

Description

Top LIC - Yes 8 352 The timestamping (TS) of the top Interrupts as shared

between LIC and GIC.

CCPLEX vGIC

GIC-400

[4]

PI 416 Extra local SPI (32) and 32 always reserved for SGI and

PPI.

AON

(SPE)

BPMP,

RCE,

SCE

AVIC PL192 Yes 1 64 All Cortex-R5 clusters use two daisy-chained AVICs.

APE AGIC

GIC-400

[4]

No 5 128 Four channels route aggregated signals to LIC, with more

than one supporting Virtualization by mapping a given

channel to a separate Virtual Machine.

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Location Type IP

[1]

[2]

Size

[3]

Description

[1] TS: TimeStamping

Ch: Channel[2]

Size: Number of Interrupts[3]

GIC-400 is implemented with different configurations to use in CCPLEX and APE for different number of Interrupts to support.[4]

Note: For SPI, the CCPLEX GIC has no direct timestamping engine implemented, only the subset of SPI

coming from the LIC are timestamped. The PPI, SGI, and SPI are locally generated inside the CCPLEX are not

hardware timestamped.

The LIC uses the notion of a channel (the Ch column above), where a channel is essentially the logic required

to mask, demux, and aggregate a set of shared Interrupts into one pair of output signals (see the figure below).

The two aggregated signals in a channel are always routed as a pair. These two signals are typically identified

as IRQ and FIQ, and can be used in a more generic fashion in Xavier.

Channels are normally connected to a CPU core except for LIC where the channels are forwarded to local

Interrupt controllers. For LIC more than one channel can be forwarded to a given local Interrupt controller.

The CCPLEX is an exception as it gets all these Interrupts in non-aggregated fashion. The eight channels of

LIC are connected as shown in the table below.

Table 8.2 LIC Channel Mapping

LIC Channel Name LIC Channel Number IRQ / FIQ Connected to IRQ / FIQ Name

BPMP 0 AVIC's in BPMP lic2bpmp_intr[0] / lic2bpmp_intr[1]

APE 1 AGIC in APE LIC2APE_INT[0] / LIC2APE_INT[1]

AON (SPE) [1:0] 3,2 AVIC's in AON (SPE) lic2aon_int[0],[2] / lic2aon_int[1],[3]

SCE[1:0] 5,4 AVIC's in SCE sce_lic_irq[0],[2] / sce_lic_irq[1],[3]

RCE[1:0] 7,6 AVIC's in RCE rce_lic_irq[0],[2] / rce_lic_irq[1],[3]

The figure below shows where the different Interrupt controllers are and how Interrupts are routed.

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Figure 8.2 Interrupt Routing (Top-Level View)

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ARM Processor's IRQ and FIQ

Processors implementing the ARMv8 architecture handle three types of Interrupts coming in from outside the

processor: System Error, IRQ, and FIQ. When the system signals an IRQ to the processor, the processor

switches to IRQ mode and jumps to the IRQ exception vector. FIQ is handled similarly. Traditionally, systems

have used FIQ for Interrupts which are time critical. In TrustZone capable processors, FIQ is generally used

for Interrupts directed to the secure world and IRQ is used for Interrupts to the non-secure world.

Most ARM processors include nIRQ and nFIQ input ports. The system tells the processor that an IRQ or FIQ

Interrupt is pending by asserting the appropriate input. Recent ARM processors add extra Interrupt inputs. The

list below applies to CCPLEX processors in Xavier:

nVIRQ and nVFIQ are virtual versions of nIRQ and nFIQ. These signals act as standard Interrupts for a VM, they are

injected by the Hypervisor through the GIC.

nSEI (System Error Interrupt) requests indicate errors and are designed to help support RAS features, and help

support server and other high reliability applications.

nVSEI is the virtual counterpart of nSEI

Note: For details of RAS features, refer to the RAS section of CCPLEX chapter of this TRM.

Interrupt Controllers

The Interrupt Controller receives Interrupts from a large number of sources. The Interrupt sources can be

assigned a target processor, a type (IRQ versus FIQ), priority levels, etc., by configuring Interrupt controller

registers. The Interrupt controller arbitrates among different incoming Interrupts and informs the target

processor of a pending Interrupt by asserting one or more of the signals described above.

LIC

The LIC is a simple Interrupt controller performing the following functions:

Routing all received (352) Interrupt signals through Force Interrupt Register (FIR) for potential forced Interrupts and

CCPLEX Interrupt Disable Register (CIDR) for potential disabled Interrupts then to Interrupt signals #0 through #351

of the vGIC in CCPLEX

Routing shared Interrupts to Cortex-R5 clusters, in aggregated form (i.e. via channels)

Timestamping of shared Interrupts

Security features

Note: The LIC does not service any of its received Interrupts, as there is no processor inside or associated with

the LIC.

The LIC can be extended in steps of 32 Interrupts, each group of 32 is called a slice. The input Interrupt signals

are combined with software set/clear bits (per Interrupt). This allows software to be able to set/clear individual

Interrupts (provided corresponding Interrupt is not asserted by hardware). The signals are further aggregated

using a channel structure, with two output signals per channel using masking and classification stages, followed

by a reduce operation.

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vGIC in APE (AGIC)

APE contains one instance of GICv2 (often referred to as vGIC for Virtual Generic Interrupt controller), called

AGIC (APE GIC) to support more channels than the built-in GIC in the Cortex-A9 MP. The AGIC is an SMP

Interrupt controller with five channels (0 through 4). Specifically, Channel 4 is routed to the APE's Cortex-A9

Interrupt controller (GIC) and Channel 0 through 3 are routed to the LIC. See the APE Interrupts diagram below.

Note that the Cortex-A9 core does not support virtualization.

vGIC in CCPLEX

The Interrupt controller used for the CCPLEX cluster is a GICv2, often referred to as vGIC (Virtual Generic

Interrupt controller) as it supports virtualization. The vGIC is an SMP Interrupt controller with eight channels

(one per CPU core in the CCPLEX) and receiving Interrupts targeted to (any) one or more of the CPUs in the

CCPLEX.

AVIC in Cortex-R5 Processor Complexes

The AVIC is an Interrupt controller that supports vectorized and prioritized operation for IRQs, i.e., hardware

selects the pending Interrupt of the highest priority, then sends an Interrupt request and its associated entry

address to the Cortex-R5 CPU core.

GIC in APE

The Interrupt controller in the Cortex-A9 multiprocessor logic in APE is an instance of the GICv1 (Generic

Interrupt controller). The AGIC in APE needs an external vGIC to allow for more channels. See section vGIC in

APE (AGIC). This GIC is used in a reduced functionality mode to handle the one channel of legacy IRQ/FIQ

from AGIC and timer Interrupts inside the Cortex-A9.

GIC Interrupt Classes

A GIC (either version 1 or version 2) can support a large number of Interrupts, with each Interrupt identified by

its unique ID. A GIC supports different classes of Interrupts. The rest of the discussion only presents the GICv2

(vGIC) operations.

Software Generated Interrupts

Software Generated Interrupts (SGIs) are software Interrupts which are generated by writing to the Software

Generated Interrupt register (GICD_SGIR). Each CPU interface can generate a maximum of 16 SGIs, with ID0-

15 for each target processor. The SGIs are also referred to as Inter Processor Interrupts (IPIs).

Private Peripheral Interrupts

Private Peripheral Interrupts (PPIs) are Interrupts generated by a peripheral that is specific to a single

processor.

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There are seven PPIs for each Carmel processor:

Virtual Maintenance Interrupt (ID25)

Hypervisor Timer Interrupt (ID26)

Virtual Timer Interrupt (ID27)

Legacy nFIQ (ID28)

Secure Physical Timer Interrupt (ID29)

Non-secure Physical Timer Interrupt (ID30)

Legacy nIRQ (ID31).

Note that the (Virtual) Maintenance Interrupt is not associated with a peripheral, but normally software

generated and used as a way to signal an Interrupt targeting explicitly the Hypervisor.

Shared Peripheral Interrupts

Shared Peripheral Interrupts (SPI's) are external hardware Interrupts generated by asserting signals on GIC or

vGIC input pins (called IRQs). From the Xavier hardware perspective, these are peripheral Interrupts. All shared

Interrupts are first routed to the LIC in Xavier. SPI IDs start at ID32. The SPIs can be configured to be edge-

triggered or level-sensitive (active-high), the vast majority of Xavier Interrupts are level, with some minor

exceptions.

Interrupt Routing

Every hardware Interrupt within Xavier is driven by a hardware module within the SoC. Some of those modules

may generate a hardware Interrupt in response to an external event (e.g., a GPIO assertion, a MSI received at

a PCIe root port, etc.). However, these external causes are outside the scope of this TRM chapter.

All of these hardware Interrupts are routed through side-band active-high level-sensitive signals either to LIC

(shared Interrupts) or to a local Interrupt controller (i.e., an Interrupt controller inside a processor cluster). The

general routing of Interrupt is illustrated in the figure above.

Interrupt Handling Targeting a Powered Off Processor

When an Interrupt controller asserts an Interrupt to a processor which is in a less-than-fully-powered state,

wake logic associated with the processor is responsible for transitioning the CPU back to a state in which the

CPU can handle the Interrupt. This is particularly relevant for processors within the CCPLEX. The exact details

of the wake logic are specific to the relevant processor complex.

Interrupts Used for Processors Power Up

In Xavier, the IRQ/FIQ associated with a given core are inactive while that core is in a low-power mode. The

GIC is on VDD_SOC power rail and remains active even when the CPU power is removed. The wake signal is

the IRQ/FIQ double, IRQOUT/FIQOUT, also generated by the GIC but only during sleep for wakeup.

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LIC Functional Description

The LIC handles a configurable number of Interrupts, using 32-bit slices. The LIC synchronizes the incoming

hardware Interrupt requests and combines (bitwise OR) them with the FIR register. The FIR allows software to

force the assertion of a particular Interrupt, using set/clear register. The combined software/hardware Interrupt

signals are forwarded to the CCPLEX GIC and to the LIC channels.

The rest of the logic is duplicated per channel, with each channel configured via Interrupt Disable (IDR),

Interrupt Enable (IER) and Interrupt Class Registers (IEP_CLASS). When a 1 is set in the proper bit position in

the IER/IDR register of a channel, that particular source is enabled/disabled for that channel. The class is set in

the proper bit position of IEP_CLASS for the corresponding source to be routed as IRQ or FIQ.

The Interrupt status register (ISR) allows the processor to view the state of the pending hardware Interrupt

requests regardless of the bit enables programmed in IER. The forced Interrupt status register (FIR) allows the

software to selectively force set or clear specific Interrupts. The read-only VIRQ/VFIQ allows the processor to

determine the source of the Interrupt request(s) causing the processor to enter the Interrupt service routine.

The individual nIRQ/nFIQ signals generated by all slices are combined (logical AND) in the combiner to

generate final nIRQ/nFIQ for the given channel.

The LIC in Xavier contains two security-related mechanisms:

the standard security model for registers, with each channel forming a security register group, and shared registers

forming also a security register group.

disable bitmaps per channel, in a specific security group, to control the visibility of certain signals across security

domains.

LIC Registers Description

Each channel is split into slices of 32 bits; the set of slices form a wide bitmap, with as many bits as there are

Interrupt signals (similar to the way the GIC uses multiple registers to construct wide configuration or status

registers). There are also a set of shared registers, i.e. outside of any channel. The set of bitmap registers are:

Shared registers:

Forcing active (FIR), with associated Set/Clr access registers

Interrupt status register (G ISR ), showing the input to LIC (before FIR and CIDR)

CCPLEX Interrupt Disable register (CIDR), allowing to block specific Interrupt in CCPLEX path

Per channel registers, for channel <c>:

Disable register (IDR<c>), with associated Set/Clr access registers, in a separate security register group.

Enable register (IER<c>), with associated Set/Clr access registers

Class register (IEP_CLASS<c>)

Valid Interrupt Status Register (VIRQ<c>) and Valid FIQ Status Register (VFIQ<c>) indicate the currently

active Interrupts that are valid on the respective pins (nIRQ or nFIQ) for that channel, that is after the enable

and class register for that channel

VIRQ<c> = (~IEP_CLASS<c>) & IER<c> & !IDR<c> & (G ISR | FIR)

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VFIQ<c> = (IEP_CLASS<c>) & IER<c> & !IDR<c> & (G ISR | FIR)

Interrupt Timestamping

Shared Interrupts (as connected between LIC and CCPLEX GIC) are fed into two generic timestamping engines

(two to allow for differentiated security domains).

Interrupt Mapping

This section presents the mapping of the Interrupts from system devices to the Interrupt ID's in the different

Xavier Interrupt controllers.

Interrupt Mapping by LIC

The following table shows the mapping of the Interrupts to the LIC, which serves only as an aggregator offering

no service of any Interrupts.

Table 8.3 LIC Interrupt Mapping

Source Module Interrupt Number Interrupt Name Interrupt Description

Top TKE 0 TOP_TKE_SHARED_0 Shared timer Interrupt from top TKE (1 of 10 total)

Top TKE 1 TOP_TKE_SHARED_1 Shared timer Interrupt from top TKE (1 of 10 total)

Top TKE 2 TOP_TKE_SHARED_2 Shared timer Interrupt from top TKE (1 of 10 total)

Top TKE 3 TOP_TKE_SHARED_3 Shared timer Interrupt from top TKE (1 of 10 total)

Top TKE 4 TOP_TKE_SHARED_4 Shared timer Interrupt from top TKE (1 of 10 total)

Top TKE 5 TOP_TKE_SHARED_5 Shared timer Interrupt from top TKE (1 of 10 total)

Top TKE 6 TOP_TKE_SHARED_6 Shared timer Interrupt from top TKE (1 of 10 total)

Top TKE 7 TOP_TKE_SHARED_7 Shared timer Interrupt from top TKE (1 of 10 total)

Top TKE 8 TOP_TKE_SHARED_8 Shared timer Interrupt from top TKE (1 of 10 total)

Top TKE 9 TOP_TKE_SHARED_9 Shared timer Interrupt from top TKE (1 of 10 total)

AON - RTC 10 RTC RTC Interrupt

LIC - GTE 11 LIC_GTE_0 Interrupt reflecting occupancy of FIFO in a Generic

Timestamp Engine; here a GTE coupled with LIC

LIC - GTE 12 LIC_GTE_1 Interrupt reflecting occupancy of FIFO in a Generic

Timestamp Engine; here a GTE coupled with LIC

AON - GTE 13 AON_GTE Interrupt reflecting occupancy of FIFO in a Generic

Timestamp Engine; here a GTE coupled with the

AON AVIC

BPMP - TKE 14 BPMP_WDT_REMOTE Remote Interrupt associated with a given WDT;

associated cluster probably down if risen (1 of 7

total)

AON - TKE

SPE_WDT_REMOTE

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Source Module Interrupt Number Interrupt Name Interrupt Description

Remote Interrupt associated with a given WDT;

associated cluster probably down if risen (1 of 7

total)

SCE - TKE 16 SCE_WDT_REMOTE Remote Interrupt associated with a given WDT;

associated cluster probably down if risen (1 of 7

total)

Top TKE 17 TOP_WDT_REMOTE Remote Interrupt associated with a given WDT;

associated cluster probably down if risen (1 of 7

total)

AON - RTC 18 AOWDT_REMOTE Remote Interrupt associated with a given WDT; this

one is the AON WDT with no direct hardware

association with a specific core (some affinity with

SPE in AON) (1 of 7 total)

RCE - TKE 19 RCE_WDT_REMOTE Remote Interrupt associated with a given WDT;

associated cluster probably down if risen (1 of 7

total)

APE 20 APE_WDT_REMOTE Remote Interrupt associated with a given WDT;

associated cluster probably down if risen (1 of 7

total)

XUSB - HOST 21 USB3_HOST_VF0 XUSB Interrupt (1 of 11 total)

XUSB - HOST 22 USB3_HOST_VF1 XUSB Interrupt (1 of 11 total)

XUSB - OST 23 USB3_HOST_VF2 XUSB Interrupt (1 of 11 total)

XUSB - HOST 24 USB3_HOST_VF3 XUSB Interrupt (1 of 11 total)

I C1

25 I2C1

I C Interrupt (1 of 10 total)

I C2 (in AON)

26 I2C2

I C Interrupt (1 of 10 total); from AON

I C3

27 I2C3

I C Interrupt (1 of 10 total)

I C4

28 I2C4

I C Interrupt (1 of 10 total)

I C5

29 I2C5

I C Interrupt (1 of 10 total)

I C6

30 I2C6

I C Interrupt (1 of 10 total

I C7

31 I2C7

I C Interrupt (1 of 10 total)

I C8 (in AON)

32 I2C8

I C Interrupt (1 of 10 total); from AON

I2C9 33 I2C9

I C Interrupt (1 of 10 total)

I C10 (in AON)

34 I2C10

I C Interrupt (1 of 10 total); from AON

QSPI0 35 QSPI0 QSPI Interrupt (1 of 2 total)

SPI1 36 SPI1 SPI Interrupt (1 of 3 total)

SPI2 (in AON) 37 SPI2 SPI Interrupt (1 of 3 total); from AON

SPI3 38 SPI3 SPI Interrupt (1 of 3 total)

QSPI1 39 QSPI1 QSPI Interrupt (1 of 2 total)

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Source Module Interrupt Number Interrupt Name Interrupt Description

AON - CAN1 40 CAN1_0 CAN Interrupt (1 of 4 total); in pair with CAN1_1

AON - CAN1 41 CAN1_1 CAN Interrupt (1 of 4 total); in pair with CAN1_0

AON - CAN2 42 CAN2_0 CAN Interrupt (1 of 4 total); in pair with CAN2_1

AON - CAN2 43 CAN2_1 CAN Interrupt (1 of 4 total); in pair with CAN2_0

UFSHC 44 UFSHC UFS Host Controller Interrupt

PCIE1 45 PCIE1_INT PCIe Interrupt (1 of 6 pairs, PCIE_INT and

PCIE_MSI)

PCIE1 46 PCIE1_MSI PCIe Interrupt (1 of 6 pairs, PCIE_INT and

PCIE_MSI)

PCIE2 47 PCIE2_INT PCIe Interrupt (1 of 6 pairs, PCIE_INT and

PCIE_MSI)

PCIE2 48 PCIE2_MSI PCIe Interrupt (1 of 6 pairs, PCIE_INT and

PCIE_MSI)

PCIE3 49 PCIE3_INT PCIe Interrupt (1 of 6 pairs, PCIE_INT and

PCIE_MSI)

PCIE3 50 PCIE3_MSI PCIe Interrupt (1 of 6 pairs, PCIE_INT and

PCIE_MSI)

PCIE4 51 PCIE4_INT PCIe Interrupt (1 of 6 pairs, PCIE_INT and

PCIE_MSI)

PCIE4 52 PCIE4_MSI PCIe Interrupt (1 of 6 pairs, PCIE_INT and

PCIE_MSI)

PCIE5 53 PCIE5_INT PCIe Interrupt (1 of 6 pairs, PCIE_INT and

PCIE_MSI)

PCIE5 54 PCIE5_MSI PCIe Interrupt (1 of 6 pairs, PCIE_INT and

PCIE_MSI)

NVDEC1 55 NVDEC1 NVDEC General Interrupt (1 of 2 total); 1 per

NVDEC

AON - GPIO 56 AON_GPIO_0 GPIO Interrupt (1 of 52 total); from AON GPIO

AON - GPIO 57 AON_GPIO_1 GPIO Interrupt (1 of 52 total); from AON GPIO

AON - GPIO 58 AON_GPIO_2 GPIO Interrupt (1 of 52 total); from AON GPIO

AON - GPIO 59 AON_GPIO_3 GPIO Interrupt (1 of 52 total); from AON GPIO

RESERVED 60 RESERVED (not used)

RESERVED 61 RESERVED (not used)

SDMMC1 62 SDMMC1 SDMMC Interrupt (1 of 6 total); in pair with

SDMMC1_SYS (SDMMC1_SYS required for

Windows standard driver operation)

RESERVED 63 RESERVED (not used)

SDMMC3

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Source Module Interrupt Number Interrupt Name Interrupt Description

SDMMC Interrupt (1 of 6 total); in pair with

SDMMC3_SYS (SDMMC3_SYS required for

Windows standard driver operation)

SDMMC4 65 SDMMC4 SDMMC Interrupt (1 of 6 total); in pair with

SDMMC4_SYS (SDMMC4_SYS required for

Windows standard driver operation)

SDMMC1 66 SDMMC1_SYS SDMMC Interrupt (1 of 6 total); in pair with

SDMMC1

RESERVED 67 RESERVED (not used)

SDMMC3 68 SDMMC3_SYS SDMMC Interrupt (1 of 6 total); in pair with

SDMMC3

SDMMC4 69 SDMMC4_SYS SDMMC Interrupt (1 of 6 total); in pair with

SDMMC4

GPU 70 GPU_STALL GPU Interrupt; two for different levels of criticality

GPU 71 GPU_NONSTALL GPU Interrupt; two for different levels of criticality

PCIE0 72 PCIE_INT PCIe Interrupt (1 of 6 pairs, PCIE_INT and

PCIE_MSI)

PCIE0 73 PCIE_MSI PCIe Interrupt (1 of 6 pairs, PCIE_INT and

PCIE_MSI)

SLVSEC 74 SLVSEC SLVSEC Interrupt (1 total)

Central DMA 75 CENTRAL_DMA_CH0 Central DMA channel Interrupt (1 of 32 total)

Central DMA 76 CENTRAL_DMA_CH1 Central DMA channel Interrupt (1 of 32 total)

Central DMA 77 CENTRAL_DMA_CH2 Central DMA channel Interrupt (1 of 32 total)

Central DMA 78 CENTRAL_DMA_CH3 Central DMA channel Interrupt (1 of 32 total)

Central DMA 79 CENTRAL_DMA_CH4 Central DMA channel Interrupt (1 of 32 total)

Central DMA 80 CENTRAL_DMA_CH5 Central DMA channel Interrupt (1 of 32 total)

Central DMA 81 CENTRAL_DMA_CH6 Central DMA channel Interrupt (1 of 32 total)

Central DMA 82 CENTRAL_DMA_CH7 Central DMA channel Interrupt (1 of 32 total)

Central DMA 83 CENTRAL_DMA_CH8 Central DMA channel Interrupt (1 of 32 total)

Central DMA 84 CENTRAL_DMA_CH9 Central DMA channel Interrupt (1 of 32 total)

Central DMA 85 CENTRAL_DMA_CH10 Central DMA channel Interrupt (1 of 32 total)

Central DMA 86 CENTRAL_DMA_CH11 Central DMA channel Interrupt (1 of 32 total)

Central DMA 87 CENTRAL_DMA_CH12 Central DMA channel Interrupt (1 of 32 total)

Central DMA 88 CENTRAL_DMA_CH13 Central DMA channel Interrupt (1 of 32 total)

Central DMA 89 CENTRAL_DMA_CH14 Central DMA channel Interrupt (1 of 32 total)

Central DMA 90 CENTRAL_DMA_CH15 Central DMA channel Interrupt (1 of 32 total)

Central DMA 91 CENTRAL_DMA_CH16 Central DMA channel Interrupt (1 of 32 total)

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Source Module Interrupt Number Interrupt Name Interrupt Description

Central DMA 92 CENTRAL_DMA_CH17 Central DMA channel Interrupt (1 of 32 total)

Central DMA 93 CENTRAL_DMA_CH18 Central DMA channel Interrupt (1 of 32 total)

Central DMA 94 CENTRAL_DMA_CH19 Central DMA channel Interrupt (1 of 32 total)

Central DMA 95 CENTRAL_DMA_CH20 Central DMA channel Interrupt (1 of 32 total)

Central DMA 96 CENTRAL_DMA_CH21 Central DMA channel Interrupt (1 of 32 total)

Central DMA 97 CENTRAL_DMA_CH22 Central DMA channel Interrupt (1 of 32 total)

Central DMA 98 CENTRAL_DMA_CH23 Central DMA channel Interrupt (1 of 32 total)

Central DMA 99 CENTRAL_DMA_CH24 Central DMA channel Interrupt (1 of 32 total)

Central DMA 100 CENTRAL_DMA_CH25 Central DMA channel Interrupt (1 of 32 total)

Central DMA 101 CENTRAL_DMA_CH26 Central DMA channel Interrupt (1 of 32 total)

Central DMA 102 CENTRAL_DMA_CH27 Central DMA channel Interrupt (1 of 32 total)

Central DMA 103 CENTRAL_DMA_CH28 Central DMA channel Interrupt (1 of 32 total)

Central DMA 104 CENTRAL_DMA_CH29 Central DMA channel Interrupt (1 of 32 total)

Central DMA 105 CENTRAL_DMA_CH30 Central DMA channel Interrupt (1 of 32 total)

Central DMA 106 CENTRAL_DMA_CH31 Central DMA channel Interrupt (1 of 32 total)

Central DMA 107 CENTRAL_DMA_COMMON Central DMA common Interrupt

RESERVED 108 RESERVED (not used)

RESERVED 109 RESERVED (not used)

RESERVED 110 RESERVED (not used)

RESERVED 111 RESERVED (not used)

UARTA 112 UARTA UART Interrupt (1 of 8 total)

UARTB 113 UARTB UART Interrupt (1 of 8 total)

UARTC (in AON) 114 UARTC UART Interrupt (1 of 8 total); from AON

UARTD 115 UARTD UART Interrupt (1 of 8 total)

UARTE 116 UARTE UART Interrupt (1 of 8 total)

UARTF 117 UARTF UART Interrupt (1 of 8 total)

ARTG (in AON)U 118 UARTG UART Interrupt (1 of 8 total); from AON

NVCSI 119 NVCSI NVCSI Interrupt

Top HSP0 120 TOP_HSP0_SHARED_0 TOP HSP0 shared Interrupt (1 of 8 total)

Top HSP0 121 TOP_HSP0_SHARED_1 TOP HSP0 shared Interrupt (1 of 8 total)

Top HSP0 122 TOP_HSP0_SHARED_2 TOP HSP0 shared Interrupt (1 of 8 total)

Top HSP0 123 TOP_HSP0_SHARED_3 TOP HSP0 shared Interrupt (1 of 8 total)

Top HSP0 124 TOP_HSP0_SHARED_4 TOP HSP0 shared Interrupt (1 of 8 total)

Top HSP0 125 TOP_HSP0_SHARED_5 TOP HSP0 shared Interrupt (1 of 8 total)

Top HSP0 126 TOP_HSP0_SHARED_6 TOP HSP0 shared Interrupt (1 of 8 total)

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Source Module Interrupt Number Interrupt Name Interrupt Description

Top HSP0 127 TOP_HSP0_SHARED_7 TOP HSP0 shared Interrupt (1 of 8 total)

Top HSP1 128 TOP_HSP1_SHARED_0 TOP HSP1 shared Interrupt (1 of 5 total)

Top HSP1 129 TOP_HSP1_SHARED_1 TOP HSP1 shared Interrupt (1 of 5 total)

Top HSP1 130 TOP_HSP1_SHARED_2 TOP HSP1 shared Interrupt (1 of 5 total)

Top HSP1 131 TOP_HSP1_SHARED_3 TOP HSP1 shared Interrupt (1 of 5 total)

Top HSP1 132 TOP_HSP1_SHARED_4 TOP HSP1 shared Interrupt (1 of 5 total)

AON - HSP 133 AON_MBOX_OUT_0 AON MBOX Interrupt (1 of 4 total)

AON - HSP 134 AON_MBOX_OUT_1 AON MBOX Interrupt (1 of 4 total)

AON - HSP 135 AON_MBOX_OUT_2 AON MBOX Interrupt (1 of 4 total)

AON - HSP 136 AON_MBOX_OUT_3 AON MBOX Interrupt (1 of 4 total)

BPMP - HSP 137 BPMP_HSP_SHARED_1 BPMP HSP shared Interrupt (1 of 4 total)

BPMP - HSP 138 BPMP_HSP_SHARED_2 BPMP HSP shared Interrupt (1 of 4 total)

BPMP - HSP 139 BPMP_HSP_SHARED_3 BPMP HSP shared Interrupt (1 of 4 total)

BPMP - HSP 140 BPMP_HSP_SHARED_4 BPMP HSP shared Interrupt (1 of 4 total)

SCE - HSP 141 SCE_MBOX_OUT_0 SCE MBOX Interrupt (1 of 4 total)

SCE - HSP 142 SCE_MBOX_OUT_1 SCE MBOX Interrupt (1 of 4 total)

SCE - HSP 143 SCE_MBOX_OUT_2 SCE MBOX Interrupt (1 of 4 total)

SCE - HSP 144 SCE_MBOX_OUT_3 SCE MBOX Interrupt (1 of 4 total)

APE 145 APE_IRQ0 APE Interrupt (1 of 8 total); in pair with APE_FIQ0

APE 146 APE_IRQ1 APE Interrupt (1 of 8 total); in pair with APE_FIQ1

APE 147 APE_IRQ2 APE Interrupt (1 of 8 total); in pair with APE_FIQ2

APE 148 APE_IRQ3 APE Interrupt (1 of 8 total); in pair with APE_FIQ3

APE 149 APE_FIQ0 APE Interrupt (1 of 8 total); in pair with APE_IRQ0

APE 150 APE_FIQ1 APE Interrupt (1 of 8 total); in pair with APE_IRQ1

APE 151 APE_FIQ2 APE Interrupt (1 of 8 total); in pair with APE_IRQ2

APE 152 APE_FIQ3 APE Interrupt (1 of 8 total); in pair with APE_IRQ3

DISPLAY 153 DISPLAY_HEAD0 Display Interrupt (1 of 5 total)

DISPLAY 154 DISPLAY_HEAD1 Display Interrupt (1 of 5 total)

DISPLAY 155 DISPLAY_HEAD2 Display Interrupt (1 of 5 total)

DISPLAY 156 DISPLAY_TZ Display Interrupt (1 of 5 total)

SOR 157 SOR SOR Interrupt (1 of 4 total)

SOR1 158 SOR1 SOR Interrupt (1 of 4 total)

DPAUX 159 DPAUX DPAUX Interrupt (1 of 4 total)

DPAUX1 160 DPAUX1 DPAUX Interrupt (1 of 4 total)

HDA 161 HDA High Definition Audio Interrupt

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Source Module Interrupt Number Interrupt Name Interrupt Description

CEC 162 CEC CEC Interrupt

XUSB - HOST 163 USB3_HOST_INT XUSB Interrupt (1 of 11 total)

XUSB - HOST 164 USB3_HOST_SMI XUSB Interrupt (1 of 11 total)

XUSB - HOST 165 USB3_HOST_PME XUSB Interrupt (1 of 11 total)

XUSB - DEV 166 USB3_DEV_INT XUSB Interrupt (1 of 11 total)

XUSB - PADCTL 167 XUSB_PADCTL XUSB Interrupt (1 of 11 total); specifically targeting

wakeup

XUSB - DEV 168 USB3_DEV_SMI XUSB Interrupt (1 of 11 total)

XUSB - DEV 169 USB3_DEV_PME XUSB Interrupt (1 of 11 total)

SMMU0 170 SMMU_COMBINED_NS ARM SMMU combined non-secure Interrupt (global,

context, and TBU perf) (1 of 6 total)

SMMU0 171 SMMU_COMBINED_S ARM SMMU combined secure Interrupt (global and

context) (1 of 6 total)

AON Cluster 172 SECURE_AON_FABRIC Secure AON fabric Interrupt

SCE Cluster 173 SECURE_SCE_FABRIC Secure SCE fabric Interrupt

BPMP Cluster 174 SECURE_BPMP_FABRIC Secure BPMP fabric Interrupt

RCE Cluster 175 SECURE_RCE_FABRIC Secure RCE fabric Interrupt

Top HSP0 176 DOORBELL_CCPLEX_NOT_SE

CURE

Doorbell for CCPLEX via LIC (1 of 2 total)

Top HSP0 177 DOORBELL_CCPLEX_SECURE Doorbell for CCPLEX via LIC (1 of 2 total)

NVLINK 178 NVLINK2HOST NVLink Interrupt (1 total)

RESERVED 179 RESERVED (not used)

RESERVED 180 RESERVED (not used)

RESERVED 181 RESERVED (not used)

RCE - HSP 182 RCE_MBOX_OUT_0 RCE MBOX Interrupt (1 of 4 total)

RCE - SP 183 RCE_MBOX_OUT_1 RCE MBOX Interrupt (1 of 4 total)

RCE - HSP 184 RCE_MBOX_OUT_2 RCE MBOX Interrupt (1 of 4 total)

RCE - HSP 185 RCE_MBOX_OUT_3 RCE MBOX Interrupt (1 of 4 total)

EQOS 186 EQOS_TX_0 EAVB Interrupt (1 of 10 total); in pair with

EQOS_RX_0

EQOS 187 EQOS_TX_1 EAVB Interrupt (1 of 10 total); in pair with

EQOS_RX_1

EQOS 188 EQOS_TX_2 EAVB Interrupt (1 of 10 total); in pair with

EQOS_RX_2

EQOS 189 EQOS_TX_3 EAVB Interrupt (1 of 10 total); in pair with

EQOS_RX_3

EQOS

190

EQOS_RX_0

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Source Module Interrupt Number Interrupt Name Interrupt Description

EAVB Interrupt (1 of 10 total); in pair with

EQOS_TX_0

EQOS 191 EQOS_RX_1 EAVB Interrupt (1 of 10 total); in pair with

EQOS_TX_1

EQOS 192 EQOS_RX_2 EAVB Interrupt (1 of 10 total); in pair with

EQOS_TX_2

EQOS 193 EQOS_RX_3 EAVB Interrupt (1 of 10 total); in pair with

EQOS_TX_3

EQOS 194 EQOS_COMMON EAVB Interrupt (1 of 10 total)

EQOS 195 EQOS_POWER EAVB Interrupt (1 of 10 total)

SATA 196 SATA_RX_STAT SATA Interrupt (1 of 2 total)

SATA 197 SATA_CTL SATA Interrupt (1 of 2 total)

NVJPG 198 NVJPG NVJPG General Interrupt

NVDEC 199 NVDEC NVDEC General Interrupt (1 of 2 total); 1 per

NVDEC

NVENC 200 NVENC NVENC Interrupt (1 of 2 total); 1 per NVENC

VI 201 VI_THI VI_THI Interrupt

NVENC1 202 NVENC1 NVENC Interrupt (1 of 2 total); 1 per NVENC

PIPE2UPHY_16 203 PIPE2UPHY_16 PIPE2UPHY Interrupt (1 of 20 total)

ISP 204 ISP_1 ISP Interrupt (1 of 2 total)

ISP 205 ISP ISP Interrupt (1 of 2 total)

VIC 206 VIC VIC General Interrupt

UARTH 207 UARTH UART Interrupt (1 of 8 total)

BPMP - CVC 208 CVC Central Voltage Control coming from BPMP

AON - PMC 209 PMIC_EXT External Power Management Chip Intr

BPMP - ACTMON 210 ACTMON This is the Central Actmon Interrupt. Other

ACTMON Interrupts stay inside the individual R5

clusters; only this one from BPMP is exposed to LIC

and called simply ACTMON.

AON - PMC 211 PMC2LIC_INTR PMC Interrupt - pmc2lic_intr

AON - WAKE 212 AON_WAKE_0 Wake Interrupt from AON (1 of 3 total)

AON - WAKE 213 AON_WAKE_1 Wake Interrupt from AON (1 of 3 total)

AON - WAKE 214 AON_WAKE_2 Wake Interrupt from AON (1 of 3 total)

AON - VC 215 AOVC_LIC_INTR AON Voltage Control Interrupt

AON - PM 216 AON_PM AON Power Management Interrupt

BPMP - PM 217 BPMP_PM BPMP Power Management Interrupt

218

THERMAL

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Source Module Interrupt Number Interrupt Name Interrupt Description

BPMP - SoC

Therm

soc_therm Interrupt; for THERMAL event; from

BPMP

BPMP - SoC

Therm

219 EDP soc_therm Interrupt; for EDP event; from BPMP

PIPE2UPHY_17 220 PIPE2UPHY_17 PIPE2UPHY Interrupt (1 of 20 total)

PIPE2UPHY_18 221 PIPE2UPHY_18 PIPE2UPHY Interrupt (1 of 20 total)

PIPE2UPHY_19 222 PIPE2UPHY_19 PIPE2UPHY Interrupt (1 of 20 total)

MCB 223 MC MC General Interrupt

EMCB 224 EMC EMC General Interrupt

RESERVED 225 RESERVED (not used)

AON - CAR 226 AON_CAR Interrupt from CAR logic inside AON

EMCB 227 EMC_CORR_ECC_ERR Correctable ECC error

TSEC 228 TSEC TSEC General Interrupt

TSECB 229 TSECB TSECB General Interrupt

CBB 230 CBB_NONSECURE CBB non-secure Interrupt

CBB 231 CBB_SECURE CBB secure Interrupt

SMMU1 232 SMMU1_COMBINED_NS ARM SMMU combined non-secure Interrupt (global;

context and TBU perf) (1 of 6 total)

SMMU1 233 SMMU1_COMBINED_S ARM SMMU combined secure Interrupt (global and

context) (1 of 6 total)

PVA0 234 PVA0 PVA Interrupt (1 of 2 total); 1 per PVA

PVA1 235 PVA1 PVA Interrupt (1 of 2 total); 1 per PVA

NVDLA0 236 NVDLA0 DLA Interrupt (1 of 2 total); 1 per DLA

NVDLA1 237 NVDLA1 DLA Interrupt (1 of 2 total); 1 per DLA

CVNAS 238 CVNAS_NONSECURE CVNAS Interrupt (1 of 2 total)

CVNAS 239 CVNAS_SECURE CVNAS Interrupt (1 of 2 total)

SMMU2 240 SMMU2_COMBINED_NS ARM SMMU combined non-secure Interrupt (global;

context and TBU perf) (1 of 6 total)

SMMU2 241 SMMU2_COMBINED_S ARM SMMU combined secure Interrupt (global and

context) (1 of 6 total)

DISPLAY 242 DISPLAY_HEAD3 Display Interrupt (1 of 5 total)

SOR2 243 SOR2 SOR Interrupt (1 of 4 total)

SOR3 244 SOR3 SOR Interrupt (1 of 4 total)

DPAUX2 245 DPAUX2 DPAUX Interrupt (1 of 4 total)

DPAUX3 246 DPAUX3 DPAUX Interrupt (1 of 4 total)

VI 247 VI_VMID_0 VI VMID Interrupt (1 of 9 total)

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Source Module Interrupt Number Interrupt Name Interrupt Description

VI 248 VI_VMID_1 VI VMID Interrupt (1 of 9 total)

VI 249 VI_VMID_2 VI VMID Interrupt (1 of 9 total)

VI 250 VI_VMID_3 VI VMID Interrupt (1 of 9 total)

VI 251 VI_VMID_4 VI VMID Interrupt (1 of 9 total)

VI 252 VI_VMID_5 VI VMID Interrupt (1 of 9 total)

VI 253 VI_VMID_6 VI VMID Interrupt (1 of 9 total)

VI 254 VI_VMID_7 VI VMID Interrupt (1 of 9 total)

VI 255 VI_VMID_8 VI VMID Interrupt (1 of 9 total)

RESERVED 256 RESERVED (not used)

RESERVED 257 RESERVED (not used)

RESERVED 258 RESERVED (not used)

RCE Cluster 259 RCE_FABRIC RCE fabric Interrupt

AON Cluster 260 AON_FABRIC AON fabric Interrupt

SCE Cluster 261 SCE_FABRIC SCE fabric Interrupt

BPMP Cluster 262 BPMP_FABRIC BPMP fabric Interrupt

HOST Controller 263 HOST1X_GEN_CPU Host Controller general Interrupt

HOST Controller 264 HOST1X_SYNCPT_CPU Host Controller syncpt Interrupt (1 of 9 total) for

virtualization

HOST Controller 265 HOST1X_SYNCPT_CPUOS0 Host Controller syncpt Interrupt (1 of 9 total) for

virtualization

HOST Controller 266 HOST1X_SYNCPT_CPUOS1 Host Controller syncpt Interrupt (1 of 9 total) for

virtualization

HOST Controller 267 HOST1X_SYNCPT_CPUOS2 Host Controller syncpt Interrupt (1 of 9 total) for

virtualization

HOST Controller 268 HOST1X_SYNCPT_CPUOS3 Host Controller syncpt Interrupt (1 of 9 total) for

virtualization

HOST Controller 269 HOST1X_SYNCPT_CPUOS4 Host Controller syncpt Interrupt (1 of 9 total) for

virtualization

HOSTController 270 HOST1X_SYNCPT_CPUOS5 Host Controller syncpt Interrupt (1 of 9 total) for

virtualization

Host Controller 271 HOST1X_SYNCPT_CPUOS6 Host Controller syncpt Interrupt (1 of 9 total) for

virtualization

Host Controller 272 HOST1X_SYNCPT_CPUOS7 Host Controller syncpt Interrupt (1 of 9 total) for

virtualization

Host Controller 273 HOST1X_TZ_GEN_CPU Host Controller secure Interrupt (1 of 2 total)

Host Controller 274 HOST1X_TZ_SYNCPT_CPU Host Controller secure Interrupt (1 of 2 total)

Host Controller 275 HOST1X_GEN_BPMP Host Controller general Interrupt for BPMP

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Source Module Interrupt Number Interrupt Name Interrupt Description

Host Controller 276 HOST1X_SYNCPT_CAMERAPR

OC_0

Host Controller syncpt for camera processing (1 of 2

total)

Host Controller 277 HOST1X_SYNCPT_CAMERAPR

OC_1

Host Controller syncpt for camera processing (1 of 2

total)

GPU 278 GPMU GPU PMU Interrupt; also routed directly to BPMP

AON - PMC

AOTAG

279 AOTAG_INTR AON Thermal Alarm Generator Interrupt

AON - PMC 280 VFMON_INTR AON Voltage/Frequency Monitor Interrupt

SE0 281 SE_APB SE APB programming Interrupt

SE0 282 SE_HOST1X SE Interrupt from Host Controller programming

interface and only for NVIDIA engines

SE0 283 SE_ELPPKA SE Interrupt for Elliptic PKA module (PKA1 in SE)

SE0 284 SE_ELPRNG SE Interrupt for Elliptic RNG module (RNG1 in SE)

SCE - PM 285 SCE_PM SCE Power Management Interrupt

RCE - PM 286 RCE_PM RCE Power Management Interrupt

RESERVED 287 RESERVED (not used)

GPIO - CTL0 288 GPIO0_0 GPIO Interrupt (1 of 52 total)

GPIO - CTL0 289 GPIO0_1 GPIO Interrupt (1 of 52 total)

GPIO - CTL0 290 GPIO0_2 GPIO Interrupt (1 of 52 total)

GPIO - CTL0 291 GPIO0_3 GPIO Interrupt (1 of 52 total)

GPIO - CTL0 292 GPIO0_4 GPIO Interrupt (1 of 52 total)

GPIO - CTL0 293 GPIO0_5 GPIO Interrupt (1 of 52 total)

GPIO - CTL0 294 GPIO0_6 GPIO Interrupt (1 of 52 total)

GPIO - CTL0 295 GPIO0_7 GPIO Interrupt (1 of 52 total)

GPIO - CTL1 296 GPIO1_0 GPIO Interrupt (1 of 52 total)

GPIO - CTL1 297 GPIO1_1 GPIO Interrupt (1 of 52 total)

GPIO - CTL1 298 GPIO1_2 GPIO Interrupt (1 of 52 total)

GPIO - CTL1 299 GPIO1_3 GPIO Interrupt (1 of 52 total)

GPIO - CTL1 300 GPIO1_4 GPIO Interrupt (1 of 52 total)

GPIO - CTL1 301 GPIO1_5 GPIO Interrupt (1 of 52 total)

GPIO - CTL1 302 GPIO1_6 GPIO Interrupt (1 of 52 total)

GPIO - CTL1 303 GPIO1_7 GPIO Interrupt (1 of 52 total)

GPIO - CTL2 304 GPIO2_0 GPIO Interrupt (1 of 52 total)

GPIO - CTL2 305 GPIO2_1 GPIO Interrupt (1 of 52 total)

GPIO - CTL2 306 GPIO2_2 GPIO Interrupt (1 of 52 total)

GPIO - CTL2 307 GPIO2_3 GPIO Interrupt (1 of 52 total)

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Source Module Interrupt Number Interrupt Name Interrupt Description

GPIO - CTL2 308 GPIO2_4 GPIO Interrupt (1 of 52 total)

GPIO - CTL2 309 GPIO2_5 GPIO Interrupt (1 of 52 total)

GPIO - CTL2 310 GPIO2_6 GPIO Interrupt (1 of 52 total)

GPIO - CTL2 311 GPIO2_7 GPIO Interrupt (1 of 52 total)

GPIO - CTL3 312 GPIO3_0 GPIO Interrupt (1 of 52 total)

GPIO - CTL3 313 GPIO3_1 GPIO Interrupt (1 of 52 total)

GPIO - CTL3 314 GPIO3_2 GPIO Interrupt (1 of 52 total)

GPIO - CTL3 315 GPIO3_3 GPIO Interrupt (1 of 52 total)

GPIO - CTL3 316 GPIO3_4 GPIO Interrupt (1 of 52 total)

GPIO - CTL3 317 GPIO3_5 GPIO Interrupt (1 of 52 total)

GPIO - CTL3 318 GPIO3_6 GPIO Interrupt (1 of 52 total)

GPIO - CTL3 319 GPIO3_7 GPIO Interrupt (1 of 52 total)

GPIO - CTL4 320 GPIO4_0 GPIO Interrupt (1 of 52 total)

GPIO - CTL4 321 GPIO4_1 GPIO Interrupt (1 of 52 total)

GPIO - CTL4 322 GPIO4_2 GPIO Interrupt (1 of 52 total)

GPIO - CTL4 323 GPIO4_3 GPIO Interrupt (1 of 52 total)

GPIO - CTL4 324 GPIO4_4 GPIO Interrupt (1 of 52 total)

GPIO - CTL4 325 GPIO4_5 GPIO Interrupt (1 of 52 total)

GPIO - CTL4 326 GPIO4_6 GPIO Interrupt (1 of 52 total)

GPIO - CTL4 327 GPIO4_7 GPIO Interrupt (1 of 52 total)

GPIO - CTL5 328 GPIO5_0 GPIO Interrupt (1 of 52 total)

GPIO - CTL5 329 GPIO5_1 GPIO Interrupt (1 of 52 total)

GPIO - CTL5 330 GPIO5_2 GPIO Interrupt (1 of 52 total)

GPIO - CTL5 331 GPIO5_3 GPIO Interrupt (1 of 52 total)

GPIO - CTL5 332 GPIO5_4 GPIO Interrupt (1 of 52 total)

GPIO - CTL5 333 GPIO5_5 GPIO Interrupt (1 of 52 total)

GPIO - CTL5 334 GPIO5_6 GPIO Interrupt (1 of 52 total)

GPIO - CTL5 335 GPIO5_7 GPIO Interrupt (1 of 52 total)

PIPE2UPHY_0 336 PIPE2UPHY_0 PIPE2UPHY Interrupt (1 of 20 total)

PIPE2UPHY_1 337 PIPE2UPHY_1 PIPE2UPHY Interrupt (1 of 20 total)

PIPE2UPHY_2 338 PIPE2UPHY_2 PIPE2UPHY Interrupt (1 of 20 total)

PIPE2UPHY_3 339 PIPE2UPHY_3 PIPE2UPHY Interrupt (1 of 20 total)

PIPE2UPHY_4 340 PIPE2UPHY_4 PIPE2UPHY Interrupt (1 of 20 total)

PIPE2UPHY_5 341 PIPE2UPHY_5 PIPE2UPHY Interrupt (1 of 20 total)

PIPE2UPHY_6 342 PIPE2UPHY_6 PIPE2UPHY Interrupt (1 of 20 total)

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Source Module Interrupt Number Interrupt Name Interrupt Description

PIPE2UPHY_7 343 PIPE2UPHY_7 PIPE2UPHY Interrupt (1 of 20 total)

PIPE2UPHY_8 344 PIPE2UPHY_8 PIPE2UPHY Interrupt (1 of 20 total)

PIPE2UPHY_9 345 PIPE2UPHY_9 PIPE2UPHY Interrupt (1 of 20 total)

PIPE2UPHY_10 346 PIPE2UPHY_10 PIPE2UPHY Interrupt (1 of 20 total)

PIPE2UPHY_11 347 PIPE2UPHY_11 PIPE2UPHY Interrupt (1 of 20 total)

PIPE2UPHY_12 348 PIPE2UPHY_12 PIPE2UPHY Interrupt (1 of 20 total)

PIPE2UPHY_13 349 PIPE2UPHY_13 PIPE2UPHY Interrupt (1 of 20 total)

PIPE2UPHY_14 350 PIPE2UPHY_14 PIPE2UPHY Interrupt (1 of 20 total)

PIPE2UPHY_15 351 PIPE2UPHY_15 PIPE2UPHY Interrupt (1 of 20 total)

Interrupt Handling by CCPLEX via vGIC

The 352 Interrupt signals that are routed to the LIC (as listed in the table above) are sent from the LIC to the

vGIC in CCPLEX and joined by another 64 Interrupt signals, totaling 416 Interrupt signals to the vGIC. The

additional 64 Interrupt signals are listed in the table below.

Table 8.4 vGIC Interrupts Mapping

Source Interrupt Number Interrupt Name Interrupt Description

(See table above.) 351:0 (See table above.) (See table above.)

CCPLEX 352 CTI[0] Cross Trigger Interrupt

CCPLEX 353 CTI[1] Cross Trigger Interrupt

CCPLEX 354 CTI[2] Cross Trigger Interrupt

CCPLEX 355 CTI[3] Cross Trigger Interrupt

RESERVED 364:356 RESERVED (not used)

CCPLEX 365 Uncore Perfmon Overflow Uncore Perfmon Overflow Interrupt

(OR of 4 L2 and 1 SNOC perfmon overflow)

RESERVED 381:366 RESERVED (not used)

CCPLEX 382 WDT_IRQ Connected to WDT at SoC level

CCPLEX 383 WDT_FIQ Connected to WDT at SoC level

CCPLEX 384 PMUIRQ[0] Architectural Perfmon Interrupt

CCPLEX 385 PMUIRQ[1] Architectural Perfmon Interrupt

CCPLEX 386 PMUIRQ[2] Architectural Perfmon Interrupt

CCPLEX 387 PMUIRQ[3] Architectural Perfmon Interrupt

CCPLEX 388 PMUIRQ[4] Architectural Perfmon Interrupt

CCPLEX 389 PMUIRQ[5] Architectural Perfmon Interrupt

CCPLEX 390 PMUIRQ[6] Architectural Perfmon Interrupt

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Source Interrupt Number Interrupt Name Interrupt Description

CCPLEX 391 PMUIRQ[7] Architectural Perfmon Interrupt

CCPLEX 392 RAS FHI[0] ARM RAS Fault Handling Interrupt

CCPLEX 393 RAS FHI[1] ARM RAS Fault Handling Interrupt

CCPLEX 394 RAS FHI[2] ARM RAS Fault Handling Interrupt

CCPLEX 395 RAS FHI[3] ARM RAS Fault Handling Interrupt

CCPLEX 396 RAS FHI[4] ARM RAS Fault Handling Interrupt

CCPLEX 397 RAS FHI[5] ARM RAS Fault Handling Interrupt

CCPLEX 398 RAS FHI[6] ARM RAS Fault Handling Interrupt

CCPLEX 399 RAS FHI[7] ARM RAS Fault Handling Interrupt

RESERVED 401:400 RESERVED (not used)

CCPLEX 402 RAS ERI[0] ARM RAS Error Recover Interrupt

CCPLEX 403 RAS ERI[1] ARM RAS Error Recover Interrupt

CCPLEX 404 RAS ERI[2] ARM RAS Error Recover Interrupt

CCPLEX 405 RAS ERI[3] ARM RAS Error Recover Interrupt

CCPLEX 406 RAS ERI[4] ARM RAS Error Recover Interrupt

CCPLEX 407 RAS ERI[5] ARM RAS Error Recover Interrupt

CCPLEX 408 RAS ERI[6] ARM RAS Error Recover Interrupt

CCPLEX 409 RAS ERI[7] ARM RAS Error Recover Interrupt

RESERVED 415:410 RESERVED (not used)

Interrupt Handling by Different Cortex-R5 Clusters

ARM Vectored Interrupt Controller Chain (AVIC Chain)

The Cortex-R5 cluster employs two ARM Vectored Interrupt controllers, AVIC0 and AVIC1, in daisy chain,

referred to as AVIC Chain, to handle two types of Interrupts:

Local Interrupts internal to the Cortex-R5 cluster

External Interrupts from the Legacy Interrupt controller (LIC) and other SoC functional modules

The AVIC Chain is located off the Cortex-R5 Cluster NoC whose firewall protects accesses to AVIC

configuration space.

The Cortex-R5 interfaces to performs the following functions in hardware to minimize AVIC0 in AVIC Chain and

the software overheads of servicing Interrupt.

Determine which Interrupt source is requesting service.

Determine where the Interrupt Service Routine (ISR) for the Interrupt source is located.

Disable the Interrupt source, before re-enabling processor Interrupts to permit another Interrupt to be taken.

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The two types of Interrupts are connected to the AVIC Chain as follows:

Local Interrupts to AVIC0 or AVIC1, where they get vectored (identified with the corresponding ISR's starting address)

then serviced by Cortex-R5 with low Interrupt latency.

One or two pairs of external Interrupts, LIC_IRQ and LIC_FIQ (from LIC to AVIC0), that are the aggregation from a

subset of global Interrupts. Services to these aggregated Interrupts are expected to have high latency.

Note: There is one pair of IRQ/FIQ from LIC to BPMP, while two pairs of IRQ/FIQ are sent from LIC to AON,

RCE, and SCE respectively. (See the Interrupt Routing (Top-Level View) diagram above.)

Xavier comprises four Cortex-R5 clusters.

AON (SPE) cluster

BPMP cluster

RCE cluster

SCE cluster

AON Cluster Interrupt Controller

The AON Cluster Interrupt controller with its AVIC Chain is shown in the diagram below.

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Figure 8.3 AON Cluster Interrupt Structure

All the AON-related Interrupts are listed in the table below.

Table 8.5 AON Interrupts Connection

Source Interrupt Name (Software Name) AVIC Connection LIC Connection

AON - TKE aon_tke_wdt_fiq_

( AON_INTERRUPT_WDTFIQ )

0 - 0 none

AON - TKE aon_tke_wdt_irq

( AON_INTERRUPT_WDTIRQ )

0 - 1 none

AON - TKE aon_tke_tmr_irq[0]

( AON_INTERRUPT_TIMER0 )

0 - 2 none

AON - TKE aon_tke_tmr_irq[1]

( AON_INTERRUPT_TIMER1 )

0 - 3 none

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Source Interrupt Name (Software Name) AVIC Connection LIC Connection

AON - TKE aon_tke_tmr_irq[2]

( AON_INTERRUPT_TIMER2 )

0 - 4 none

AON - TKE aon_tke_tmr_irq[3]

( AON_INTERRUPT_TIMER3 )

0 - 5 none

AON - TKE aon_tke_wdt_remoteinterrupt

( SPE_WDT_REMOTE )

none 15

AON - HSP Mbox aon_hsp_shrd_intr[0]

( AON_INTERRUPT_MBOX )

0 - 6 none

AON - HSP Mbox aon2licmbox_int_out[0]

( AON_MBOX_OUT_0 )

none 133

AON - HSP Mbox aon2licmbox_int_out[1]

( AON_MBOX_OUT_1 )

none 134

AON - HSP Mbox aon2licmbox_int_out[2]

( AON_MBOX_OUT_2 )

none 135

AON - HSP Mbox aon2licmbox_int_out[3]

( AON_MBOX_OUT_3 )

none 136

AON - GTE aon_gte_interrupt

( AON_INTERRUPT_GTE )

0 - 7 none

AON - GTE aon2lic_gteint

( AON_GTE )

none 13

AON - R5 aon_int_npmuirq

( AON_INTERRUPT_PMU )

0 - 8 none

AON - DMA dma_intr[0]

( AON_INTERRUPT_DMA0 )

0 - 9 none

AON - DMA dma_intr[1]

( AON_INTERRUPT_DMA1 )

0 - 10 none

AON - DMA dma_intr[2]

( AON_INTERRUPT_DMA2 )

0 - 11 none

AON - DMA dma_intr[3]

( AON_INTERRUPT_DMA3 )

0 - 12 none

AON - DMA dma_intr[4]

( AON_INTERRUPT_DMA4 )

0 - 13 none

AON - DMA dma_intr[5]

( AON_INTERRUPT_DMA5 )

0 - 14 none

AON - DMA dma_intr[6]

( AON_INTERRUPT_DMA6 )

0 - 15 none

AON - DMA dma_intr[7]

( AON_INTERRUPT_DMA7 )

0 - 16 none

AON - I C10

aon_i2c1_rupt (AVIC) / aon2lic_i2c1int (LIC)

( AON_INTERRUPT_I2C1 (AVIC) / I2C10 (LIC) )

0 - 17 34

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Source Interrupt Name (Software Name) AVIC Connection LIC Connection

AON - I C2

aon_i2c2_rupt (AVIC) / aon2lic_i2c2int (LIC)

( AON_INTERRUPT_I2C2 (AVIC) / I2C2 (LIC) )

0 - 18 26

AON - I C8

aon_i2c3_rupt (AVIC) / aon2lic_i2c3int (LIC)

( AON_INTERRUPT_I2C3 (AVIC) / I2C8 (LIC) )

0 - 19 32

AON - SPI2 aon_spi_intr (AVIC) / aon2lic_spiint (LIC)

( AON_INTERRUPT_SPI (AVIC) / SPI2 (LIC) )

0 - 20 37

AON - DMIC aon_dmic_intr

( AON_INTERRUPT_DMIC )

0 - 21 none

AON - UARTC aon_uart1_intr (AVIC) / aon2lic_uartgint (LIC)

( AON_INTERRUPT_UART_1 (AVIC) / UARTC (LIC) )

0 - 22 114

AON - UARTG aon_uart2_intr (AVIC) / aon2lic_uartcint (LIC)

( AON_INTERRUPT_UART_2 (AVIC) / UARTG (LIC) )

0 - 23 118

AON - CAN1 aon_can1_intr[0] (AVIC) / aon2lic_can1int[0] (LIC)

( AON_INTERRUPT_CAN1_0 (AVIC) / CAN1_0 (LIC) )

0 - 24 40

AON - CAN1 aon_can1_intr[1] (AVIC) / aon2lic_can1int[1] (LIC)

( AON_INTERRUPT_CAN1_1 (AVIC) / CAN1_1 (LIC) )

0 - 25 41

AON - CAN2 aon_can2_intr[0] (AVIC) / aon2lic_can2int[0] (LIC)

( AON_INTERRUPT_CAN2_0 (AVIC) / CAN2_0 (LIC) )

0 - 26 42

AON - CAN2 aon_can2_intr[1] (AVIC) / aon2lic_can2int[1] (LIC)

( AON_INTERRUPT_CAN2_1 (AVIC) / CAN2_1 (LIC) )

0 - 27 43

LIC lic2aon_int[0]

( AON_INTERRUPT_LIC0 )

0 - 28 none

LIC lic2aon_int[1]

( AON_INTERRUPT_LIC1 )

0 - 29 none

LIC lic2aon_int[2]

( AON_INTERRUPT_LIC2 )

0 - 30 none

LIC lic2aon_int[3]

( AON_INTERRUPT_LIC3 )

0 - 31 none

AON - NOC aon_noc_non_secure_intr (AVIC) / aon2lic_fabric_error_intr (LIC)

( AON_INTERRUPT_NOC_NON_SECURE (AVIC) / AON_FABRIC

(LIC) )

1 - 0 260

AON - GPIO gpioaon_spe_rupt[0]

( AON_INTERRUPT_GPIO )

1 - 1 none

AON - GPIO gpioaon_lic_rupt[0]

( AON_GPIO_0 )

none 56

AON - GPIO gpioaon_lic_rupt[1]

( AON_GPIO_1 )

none 57

AON - GPIO gpioaon_lic_rupt[2]

( AON_GPIO_2 )

none 58

AON - GPIO gpioaon_lic_rupt[3]

( AON_GPIO_3 )

none 59

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Source Interrupt Name (Software Name) AVIC Connection LIC Connection

AON - Wake wake_tier0 (AVIC) / aon2lic_tier0wake_int (LIC)

( AON_INTERRUPT_WAKE0 (AVIC) / AON_WAKE_0 (LIC) )

1 - 2 212

AON - Wake wake_tier0 / aon2lic_tier0wake_int

( AON_WAKE_1 )

none 213

AON - Wake wake_tier0 / aon2lic_tier0wake_int

( AON_WAKE_2 )

none 214

AON - PMC pmc2vic_intr

( AON_INTERRUPT_PMC )

1 - 3 none

AON - PMC pmc_pwr_intr

( PMIC_EXT )

none 209

AON - PMC pmc2lic_intr

( PMC2LIC_INTR )

none 211

AON - PMC aon2lic_aotag_int

( AOTAG_INTR )

none 279

AON - PMC aon2lic_vfmon_int

( VFMON_INTR )

none 280

AON - PM pm2vic_intr

( AON_INTERRUPT_PM )

1 - 5 none

AON - PM aon2lic_pmint

( AON_PM )

none 216

AON - R5 FPU cpu2vic_fpuint

( AON_INTERRUPT_FPUINT )

1 - 6 none

AON - AOVC aovc2vic_intr

( AON_INTERRUPT_AOVC )

1 - 7 none

AON - AOVC aon2lic_aovcint

( AOVC_LIC_INTR )

none 215

AON - PM pm_actmon_intr

( AON_INTERRUPT_ACTMON )

1 - 8 none

AON - RTC aowdt_irq

( AON_INTERRUPT_AOWDT )

1 - 9 none

AON - RTC aon2lic_rtcint

( RTC )

none 10

AON - RTC aon2lic_aowdt_wakecold_intr

( AOWDT_REMOTE )

none 18

top HSP shsp2spe_db

( AON_INTERRUPT_TOP0_HSP_DB )

1 - 10 none

AON - CTI aon_cpu_csite_nctiirq

( AON_INTERRUPT_CTIIRQ )

1 - 11 none

AON - NOC aon_noc_secure_intr (AVIC) / aon2lic_fabric_sec_intr (LIC)

( AON_INTERRUPT_NOC_SECURE (AVIC) /

SECURE_AON_FABRIC (LIC) )

1 - 12 172

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Source Interrupt Name (Software Name) AVIC Connection LIC Connection

AON - CAR aon_car_interrupt (AVIC) / aon_car_interrupt (LIC)

( AON_INTERRUPT_CAR (AVIC) / AON_CAR (LIC) )

1 - 13 226

UARTF uart_f_uart_intr

( AON_INTERRUPT_UART6 )

1 - 14 none

UARTH uart_h_uart_intr

( AON_INTERRUPT_UART8 )

1 - 15 none

AON - GPIO gpioaon_spe_rupt[1]

( AON_INTERRUPT_GPIO_3 )

1 - 16 none

For further information of the AON Cluster Interrupt controller, refer to the Always-On (AON) Cluster and SPE

chapter of this TRM.

BPMP Cluster Interrupt Controller

The BPMP Cluster Interrupt controller with its AVIC Chain is shown in the diagram below.

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Figure 8.4 BPMP Cluster Interrupt Structure

All the BPMP-related Interrupts are listed in the table below.

Table 8.6 BPMP Interrupts Connection

Source Interrupt Name (Software Name) AVIC Connection LIC Connection

BPMP - TKE tke_wdt_irq

( BPMP_INTERRUPT_WDTIRQ )

0 - 0 none

BPMP - TKE tke_timer_intr[0]

( BPMP_INTERRUPT_TIMER0 )

0 - 1 none

BPMP - TKE tke_timer_intr[1]

( BPMP_INTERRUPT_TIMER1 )

0 - 2 none

BPMP - TKE

0 - 3

none

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Source Interrupt Name (Software Name) AVIC Connection LIC Connection

tke_timer_intr[2]

( BPMP_INTERRUPT_TIMER2 )

BPMP - TKE tke_timer_intr[3]

( BPMP_INTERRUPT_TIMER3 )

0 - 4 none

BPMP - TKE tke_wdt_fiq

( BPMP_INTERRUPT_WDTFIQ )

0 - 5 none

BPMP - TKE watchdog_remoteinterrupt_bpmp

( BPMP_WDT_REMOTE )

none 14

top HSP shsp2bpmp_db_intr

( BPMP_INTERRUPT_HSP_DB )

0 - 6 none

BPMP - PM pm2vic_intr

( BPMP_INTERRUPT_PM )

0 - 8 none

BPMP - PM bpmp_pm2lic_intr

( BPMP_PM )

none 217

BPMP - CVC cvc2bpmp_intr

( BPMP_INTERRUPT_CVC )

0 - 9 none

BPMP - CVC bpmp2lic_cvc_intr

( CVC )

none 208

Host Controller host1x_intr

( BPMP_INTERRUPT_H1XSNC )

0 - 10 none

AON - PMC wake_tier[0]

( BPMP_INTERRUPT_WAKE0 )

0 - 13 none

AON - PMC wake_tier[1]

( BPMP_INTERRUPT_WAKE1 )

0 - 14 none

AON - PMC wake_tier[2]

( BPMP_INTERRUPT_WAKE2 )

0 - 15 none

LIC lic2bpmp_intr[0]

( BPMP_INTERRUPT_LIC0 )

0 - 16 none

LIC lic2bpmp_intr[1]

( BPMP_INTERRUPT_LIC1 )

0 - 17 none

BPMP - DMA bpmp_dma_intr[0]

( BPMP_INTERRUPT_DMA0 )

0 - 20 none

BPMP - DMA bpmp_dma_intr[1]

( BPMP_INTERRUPT_DMA1 )

0 - 21 none

BPMP - DMA bpmp_dma_intr[2]

( BPMP_INTERRUPT_DMA2 )

0 - 22 none

BPMP - DMA bpmp_dma_intr[3]

( BPMP_INTERRUPT_DMA3 )

0 - 23 none

BPMP - HSP hsp_shrd_intr[0]

( BPMP_INTERRUPT_HSP_SI_0 )

0 - 24 none

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Source Interrupt Name (Software Name) AVIC Connection LIC Connection

BPMP - HSP bpmp2lic_hsp_si[0]

( BPMP_HSP_SHARED_1 )

none 137

BPMP - HSP bpmp2lic_hsp_si[1]

( BPMP_HSP_SHARED_2 )

none 138

BPMP - HSP bpmp2lic_hsp_si[2]

( BPMP_HSP_SHARED_3 )

none 139

BPMP - HSP bpmp2lic_hsp_si[3]

( BPMP_HSP_SHARED_4 )

none 140

BPMP - R5 FPU cpu2vic_fpu_intr

( BPMP_INTERRUPT_FPUINT

0 - 25 none

GPU gpmu2bpmp_intr (AVIC) / gpmu2bpmp_intr (LIC)

( BPMP_INTERRUPT_GPMU (AVIC) / GPMU (LIC) )

0 - 26 278

BPMP - SoC Therm edp_irq (AVIC) / edp_irq (LIC)

( BPMP_INTERRUPT_EDP (AVIC) / EDP (LIC) )

0 - 27 219

BPMP - SoC Therm thermal_irq (AVIC) / thermal_irq (LIC)

( BPMP_INTERRUPT_SCTHRM (AVIC) / THERMAL (LIC) )

0 - 28 218

AON - I2C10 aon2lic_i2c1int

( BPMP_INTERRUPT_AONPWRI2C (AVIC) / I2C10 (LIC) )

0 - 30 34

I2C5 dvc_intr

( BPMP_INTERRUPT_SOCPWRI2C (AVIC) / I2C5 (LIC) )

0 - 31 29

QSPI1 bpmp_qspi1_intr

( BPMP_INTERRUPT_QSPI1 (AVIC) / QSPI1 (LIC) )

1 - 5 39

AON - UARTC bpmp_uart_intr (AVIC) / aon2lic_uartcint (LIC)

( BPMP_INTERRUPT_UART (AVIC) / UARTC (LIC) )

1 - 6 114

QSPI0 bpmp_qspi0_intr

( BPMP_INTERRUPT_QSPI0 (AVIC) / QSPI0 (LIC) )

1 - 7 35

BPMP - R5 nPMUIRQ0

( BPMP_INTERRUPT_PMUIRQ )

1 - 8 none

BPMP - ACTMON actmon_intr

( BPMP_INTERRUPT_CNTRL_ACTMON )

1 - 9 none

BPMP - PM pm_actmon_intr

( BPMP_INTERRUPT_BPMP_ACTMON )

1 - 10 none

BPMP - ACTMON bpmp2lic_cactmon_intr

( ACTMON )

none 210

BPMP - NOC noc_non_sec_intr (AVIC) / bpmp2lic_noc_non_secure_intr (LIC)

( BPMP_INTERRUPT_NOC_NON_SECURE (AVIC) / BPMP_FABRIC

(LIC) )

1 - 15 262

BPMP - GTE bpmp_gte_intr

( BPMP_INTERRUPT_GTE )

1 - 16 none

BPMP - NOC

1 - 17

174

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Source Interrupt Name (Software Name) AVIC Connection LIC Connection

noc_sec_intr (AVIC) / bpmp2lic_noc_secure_intr (LIC)

( BPMP_INTERRUPT_NOC_SECURE (AVIC) /

SECURE_BPMP_FABRIC (LIC) )

BPMP - CTI csite_nctiirq

( BPMP_INTERRUPT_CTIIRQ )

1 - 18 none

BPMP - HSP hsp_shrd_intr[1]

( BPMP_INTERRUPT_HSP_SI_1 )

1 - 19 none

BPMP - HSP hsp_shrd_intr[2]

( BPMP_INTERRUPT_HSP_SI_2 )

1 - 20 none

BPMP - HSP hsp_shrd_intr[3]

( BPMP_INTERRUPT_HSP_SI_3 )

1 - 21 none

BPMP - HSP hsp_shrd_intr[4]

( BPMP_INTERRUPT_HSP_SI_4 )

1 - 22 none

CAR bpmp_car_intr

( BPMP_INTERRUPT_CAR )

1 - 23 none

For further information of the BPMP Cluster Interrupt controller, refer to the Boot and Power Management

Processor chapter of this TRM.

RCE Cluster Interrupt Controller

The RCE Cluster Interrupt controller with its AVIC Chain is shown in the diagram below.

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Figure 8.5 RCE Cluster Interrupt Structure

All the RCE-related Interrupts are listed in the table below.

Table 8.7 RCE Interrupts Connection

Source Interrupt Name (Software Name) AVIC Connection LIC Connection

RCE - TKE tke_wdt_nfiq

( RCE_INTERRUPT_WDTFIQ )

0 - 0 none

RCE - TKE tke_wdt_irq

( RCE_INTERRUPT_WDTIRQ )

0 - 1 none

RCE - TKE tke_timer_intr[0]

( RCE_INTERRUPT_TIMER0 )

0 - 2 none

RCE - TKE tke_timer_intr[1]

( RCE_INTERRUPT_TIMER1 )

0 - 3 none

RCE - TKE

0 - 4

none

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Source Interrupt Name (Software Name) AVIC Connection LIC Connection

tke_timer_intr[2]

( RCE_INTERRUPT_TIMER2 )

RCE - TKE tke_timer_intr[3]

( RCE_INTERRUPT_TIMER3 )

0 - 5 none

RCE - TKE rce_tke_wdt_remoteinterrupt

( RCE_WDT_REMOTE )

none 19

RCE - HSP hsp_shrd_intr

( RCE_INTERRUPT_MBOX )

0 - 6 none

RCE - HSP rce2licmbox_int_out[0]

( RCE_MBOX_OUT_0 )

none 182

RCE - HSP rce2licmbox_int_out[1]

( RCE_MBOX_OUT_1 )

none 183

RCE - HSP rce2licmbox_int_out[2]

( RCE_MBOX_OUT_2 )

none 184

RCE - HSP rce2licmbox_int_out[3]

( RCE_MBOX_OUT_3 )

none 185

RCE - GTE gte_intr

( RCE_INTERRUPT_GTE )

0 - 7 none

RCE - R5 PMU nPMUIRQ0

( RCE_INTERRUPT_PMU )

0 - 8 none

RCE - DMA dma_intr[0]

( RCE_INTERRUPT_DMA0 )

0 - 9 none

RCE - DMA dma_intr[1]

( RCE_INTERRUPT_DMA1 )

0 - 10 none

RCE - DMA dma_intr[2]

( RCE_INTERRUPT_DMA2 )

0 - 11 none

RCE - DMA dma_intr[3]

( RCE_INTERRUPT_DMA3 )

0 - 12 none

RCE - DMA dma_intr[4]

( RCE_INTERRUPT_DMA4 )

0 - 13 none

RCE - DMA dma_intr[5]

( RCE_INTERRUPT_DMA5 )

0 - 14 none

RCE - DMA dma_intr[6]

( RCE_INTERRUPT_DMA6 )

0 - 15 none

RCE - DMA dma_intr[7]

( RCE_INTERRUPT_DMA7 )

0 - 16 none

LIC rce_lic_irq[0]

( RCE_INTERRUPT_LIC0 )

0 - 17 none

LIC rce_lic_irq[1]

( RCE_INTERRUPT_LIC1 )

0 - 18 none

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Source Interrupt Name (Software Name) AVIC Connection LIC Connection

LIC rce_lic_irq[2]

( RCE_INTERRUPT_LIC2 )

0 - 19 none

LIC rce_lic_irq[3]

( RCE_INTERRUPT_LIC3 )

0 - 20 none

RCE - HSM hsm_intr[0]

( RCE_INTERRUPT_HSM_CRITICAL_ERR )

0 - 22 none

VI vi2rtcpu_intr

( RCE_INTERRUPT_VI_HP (AVIC) / VI_THI (LIC) )

0 - 23 201

RCE - HSM hsm_intr[1]

( RCE_INTERRUPT_HSM_HP )

0 - 25 none

RCE - HSM hsm_intr[2]

( RCE_INTERRUPT_HSM_LP )

0 - 26 none

RCE - NOC noc_non_sec_intr (AVIC) / noc_non_sec_intr (LIC)

( RCE_INTERRUPT_NOC_NON_SECURE (AVIC) / RCE_FABRIC

(LIC) )

1 - 0 259

RCE - PM pm_actmon_intr

( RCE_INTERRUPT_ACTMON )

1 - 1 none

RCE - R5 FPU cpu2vic_fpu_intr

( RCE_INTERRUPT_FPUINT )

1 - 2 none

RCE - PM pm2vic_intr

( RCE_INTERRUPT_PM )

1 - 3 none

MC - SBE mc2rce_sbe_intr

( RCE_INTERRUPT_MC_SBE )

1 - 4 none

RCE - NOC noc_sec_intr (AVIC) / noc_sec_intr (LIC)

( RCE_INTERRUPT_NOC_SECURE ( AVIC / SECURE_RCE_FABRIC

(LIC) )

1 - 5 175

RCE - PM rce2lic_pmint

( RCE_PM )

none 286

CAR rce_car_intr

( RCE_INTERRUPT_CAR )

1 - 6 none

HSP shsp2rce_db_intr

( RCE_INTERRUPT_TOP0_HSP_DB )

1 - 14 none

RCE - CTI csite_nctiirq

( RCE_INTERRUPT_CTIIRQ )

1 - 17 none

I2C1 i2c1_intr (AVIC) / i2c1_rupt (LIC)

( RCE_INTERRUPT_I2C1 (AVIC) / I2C1 (LIC) )

1 - 19 25

I2C3 i2c3_intr (AVIC) / i2c3_rupt (LIC)

( RCE_INTERRUPT_I2C3 (AVIC) / I2C3 (LIC) )

1 - 20 27

AON - I2C8 i2c8_intr (AVIC) / aon2lic_i2c3int (LIC)

( RCE_INTERRUPT_I2C8 (AVIC) / I2C8 (LIC) )

1 - 21 32

AON - UARTG

1 - 22

118

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Source Interrupt Name (Software Name) AVIC Connection LIC Connection

uart7_intr

(RCE_INTERRUPT_UART7 (AVIC) / UARTG (LIC))

For further information of the RCE Cluster Interrupt controller, refer to the RCE chapter of this TRM.

SCE Cluster Interrupt Controller

The SCE Cluster Interrupt controller with its AVIC Chain is shown in the diagram below.

Figure 8.6 SCE Cluster Interrupt Structure

All the SCE-related Interrupts are listed in the table below.

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Table 8.8 SCE Interrupts Connection

Source Interrupt Name (Software Name) AVIC Connection LIC Connection

SCE - TKE tke_wdt_nfiq

( SCE_INTERRUPT_WDTFIQ )

0 - 0 none

SCE - TKE tke_wdt_irq

(SCE_INTERRUPT_WDTIRQ )

0 - 1 none

SCE - TKE tke_timer_intr[0]

( SCE_INTERRUPT_TIMER0 )

0 - 2 none

SCE - TKE tke_timer_intr[1]

( SCE_INTERRUPT_TIMER1 )

0 - 3 none

SCE - TKE tke_timer_intr[2]

( SCE_INTERRUPT_TIMER2 )

0 - 4 none

SCE - TKE tke_timer_intr[3]

( SCE_INTERRUPT_TIMER3 )

0 - 5 none

SCE - TKE sce_tke_wdt_remoteinterrupt

( SCE_WDT_REMOTE )

none 16

SCE - HSP hsp_shrd_intr

( SCE_INTERRUPT_MBOX )

0 - 6 none

SCE - HSP sce2licmbox_int_out[0]

( SCE_MBOX_OUT_0 )

none 141

SCE - HSP sce2licmbox_int_out[1]

( SCE_MBOX_OUT_1 )

none 142

SCE - HSP sce2licmbox_int_out[2]

( SCE_MBOX_OUT_2 )

none 143

SCE - HSP sce2licmbox_int_out[3]

( SCE_MBOX_OUT_3 )

none 144

SCE - GTE gte_intr

( SCE_INTERRUPT_GTE )

0 - 7 none

SCE - R5 PMU nPMUIRQ0

( SCE_INTERRUPT_PMU )

0 - 8 none

SCE - DMA dma_intr[0]

( SCE_INTERRUPT_DMA0 )

0 - 9 none

SCE - DMA dma_intr[1]

( SCE_INTERRUPT_DMA1 )

0 - 10 none

SCE - DMA dma_intr[2]

( SCE_INTERRUPT_DMA2 )

0 - 11 none

SCE - DMA dma_intr[3]

( SCE_INTERRUPT_DMA3 )

0 - 12 none

SCE - DMA dma_intr[4]

( SCE_INTERRUPT_DMA4 )

0 - 13 none

SCE - DMA

0 - 14

none

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Source Interrupt Name (Software Name) AVIC Connection LIC Connection

dma_intr[5]

( SCE_INTERRUPT_DMA5 )

SCE - DMA dma_intr[6]

( SCE_INTERRUPT_DMA6)

0 - 15 none

SCE - DMA dma_intr[7]

( SCE_INTERRUPT_DMA7 )

0 - 16 none

LIC sce_lic_irq[0]

( SCE_INTERRUPT_LIC0 )

0 - 17 none

LIC sce_lic_irq[1]

( SCE_INTERRUPT_LIC1 )

0 - 18 none

LIC sce_lic_irq[2]

( SCE_INTERRUPT_LIC2 )

0 - 19 none

LIC sce_lic_irq[3]

( SCE_INTERRUPT_LIC3 )

0 - 20 none

SCE - HSM hsm_intr[0]

( SCE_INTERRUPT_HSM_CRITICAL_ERR )

0 - 22 none

VI vi2rtcpu_intr

( SCE_INTERRUPT_VI_HP (AVIC) / VI_THI (LIC) )

0 - 23 201

SCE - HSM hsm_intr[1]

( SCE_INTERRUPT_HSM_HP )

0 - 25 none

SCE - HSM hsm_intr[2]

( SCE_INTERRUPT_HSM_LP )

0 - 26 none

SCE - NOC noc_non_sec_intr (AVIC) / noc_non_sec_intr (LIC)

( SCE_INTERRUPT_NOC_NON_SECURE (AVIC) / SCE_FABRIC

(LIC) )

1 - 0 261

SCE - PM pm_actmon_intr

( SCE_INTERRUPT_ACTMON )

1 - 1 none

SCE - R5 FPU cpu2vic_fpu_intr

( SCE_INTERRUPT_FPUINT )

1 - 2 none

SCE - PM pm2vic_intr

( SCE_INTERRUPT_PM )

1 - 3 none

MC - SBE mc2sce_sbe_intr

( SCE_INTERRUPT_MC_SBE )

1 - 4 none

SCE - NOC noc_sec_intr (AVIC) / noc_sec_intr (LIC)

( SCE_INTERRUPT_NOC_SECURE (AVIC) / SECURE_SCE_FABRIC

(LIC) )

1 - 5 173

SCE - PM sce2lic_pmint

( SCE_PM )

none 285

CAR sce_car_intr

( SCE_INTERRUPT_CAR )

1 - 6 none

HSP

1 - 14

none

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Source Interrupt Name (Software Name) AVIC Connection LIC Connection

shsp2sce_db_intr

( SCE_INTERRUPT_TOP0_HSP_DB )

SCE - CTI csite_nctiirq

( SCE_INTERRUPT_CTIIRQ )

1 - 17 none

I2C1 i2c1_intr (AVIC) / i2c1_rupt (LIC)

( SCE_INTERRUPT_I2C1 (AVIC) / I2C1 (LIC) )

1 - 19 25

I2C3 i2c3_intr (AVIC) / i2c3_rupt (LIC)

( SCE_INTERRUPT_I2C3 (AVIC) / I2C3 (LIC) )

1 - 20 27

AON - I2C8 i2c8_intr (AVIC) / aon2lic_i2c3int (LIC)

( SCE_INTERRUPT_I2C8 (AVIC) / I2C8 (LIC) )

1 - 21 32

AON - UARTG uart7_intr

( SCE_INTERRUPT_UART7 (AVIC) / UARTG (LIC) )

1 - 22 118

For further information of the SCE Cluster Interrupt controller, refer to the Safety Cluster Engine (SCE) chapter

of this TRM.

APE Interrupt Controller

The APE Interrupt controllers together with Interrupt signals routing are shown in the diagram below.

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Figure 8.7 APE Interrupts

There are two Interrupt controllers in the APE, the local Interrupt controller in ADSP and the APE Generic

Interrupt controller (AGIC). The APE Interrupts are routed to AGIC then aggregated to irq and fiq that get sent to

the ADSP local Interrupt controller's IRQ/FIQ input. The signals are configured as legacy mode, i.e. IRQ as PPI

(4) and FIQ as PPI(1). Other Interrupts in the ADSP local Interrupt controller are global timer PPI(0), private

timer PPI(1), and watchdog timer PPI(3). The ADSP local Interrupt controller does not have any SGI or SPI

Interrupts configured.

ADSP Interrupt Handling

ADSP's global timer PPI(0), private timer PPI(1), and watchdog timer PPI(3) Interrupts are not sent to the AGIC

or CCPLEX. To service these Interrupts, the ADSP only needs to access the registers within the local Interrupt

controller.

ADSP IRQ/FIQ Interrupts involve two Interrupt controllers, the ADSP local Interrupt controller and AGIC. ADSP

reads from its local Interrupt controller then from AGIC to determine the Interrupt source. If the Interrupt source

can be identified as from AGIC Interrupt acknowledge register, ADSP starts servicing the Interrupt. Some

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Interrupts, such as AHUB error Interrupt, require more Interrupt status access before the source can be

identified. After servicing the Interrupts, ADSP writes end of Interrupt to AGIC and the local Interrupt controller

to signal the completion of an Interrupt.

CCPLEX Interrupt Handling

There are four sets of AVIC-aggregated IRQ and FIQ Interrupt signals (IRQ[3:0] and FIQ[3:0]) from APE to

CCPLEX. While the CCPLEX has no access to the ADSP local Interrupt controller, the Interrupt service by the

Carmel processors (in CCPLEX) Interrupt service is similar to the ADSP's Interrupt handling, with the exception

that they first read from the vGIC in CCPLEX and LIC to determine if a particular Interrupt is coming from APE.

All the APE-related Interrupts are listed in the table below.

Table 8.9 APE Interrupts Connection

Source Interrupt Name GIC Connection LIC Connection

Processors in Xavier for Software-Generated Interrupts (SGI) 0 ~ 15 none

APE - ADMA adma_eot[0] 32 none

APE - ADMA adma_eot[1] 33 none

APE - ADMA adma_eot[2] 34 none

APE - ADMA adma_eot[3] 35 none

APE - ADMA adma_eot[4] 36 none

APE - ADMA adma_eot[5] 37 none

APE - ADMA adma_eot[6] 38 none

APE - ADMA adma_eot[7] 39 none

APE - ADMA adma_eot[8] 40 none

APE - ADMA adma_eot[9] 41 none

APE - ADMA adma_eot[10] 42 none

APE - ADMA adma_eot[11] 43 none

APE - ADMA adma_eot[12] 44 none

APE - ADMA adma_eot[13] 45 none

APE - ADMA adma_eot[14] 46 none

APE - ADMA adma_eot[15] 47 none

APE - ADMA adma_eot[16] 48 none

APE - ADMA adma_eot[17] 49 none

APE - ADMA adma_eot[18] 50 none

APE - ADMA adma_eot[19] 51 none

APE - ADMA adma_eot[20] 52 none

APE - ADMA adma_eot[21] 53 none

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Source Interrupt Name GIC Connection LIC Connection

APE - ADMA adma_eot[22] 54 none

APE - ADMA adma_eot[23] 55 none

APE - ADMA adma_eot[24] 56 none

APE - ADMA adma_eot[25] 57 none

APE - ADMA adma_eot[26] 58 none

APE - ADMA adma_eot[27] 59 none

APE - ADMA adma_eot[28] 60 none

APE - ADMA adma_eot[29] 61 none

APE - ADMA adma_eot[30] 62 none

APE - ADMA adma_eot[31] 63 none

APE - AHSP ahsp_mbox_full[0] 64 none

APE - AHSP ahsp_mbox_full[1] 65 none

APE - AHSP ahsp_mbox_full[2] 66 none

APE - AHSP ahsp_mbox_full[3] 67 none

APE - AHSP ahsp_mbox_full[4] 68 none

APE - AHSP ahsp_mbox_full[5] 69 none

APE - AHSP ahsp_mbox_full[6] 70 none

APE - AHSP ahsp_mbox_full[7] 71 none

APE - AHSP ahsp_mbox_empty[0] 72 none

APE - AHSP ahsp_mbox_empty[1] 73 none

APE - AHSP ahsp_mbox_empty[2] 74 none

APE - AHSP ahsp_mbox_empty[3] 75 none

APE - AHSP ahsp_mbox_empty[4] 76 none

APE - AHSP ahsp_mbox_empty[5] 77 none

APE - AHSP ahsp_mbox_empty[6] 78 none

APE - AHSP ahsp_mbox_empty[7] 79 none

APE - AHSP ashp_shrd_intr[0] 80 none

APE - AHSP ashp_shrd_intr[1] 81 none

APE - AHSP ashp_shrd_intr[2] 82 none

APE - AHSP ashp_shrd_intr[3] 83 none

APE - AHSP ashp_shrd_intr[4] 84 none

APE - ADSP adsp_pmuirq 85 none

APE - ADSP adsp_wdresetreq 86 none

APE - ADSP L2CC adsp_l2ccintr 87 none

APE - AHUB ahub_err 88 none

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Source Interrupt Name GIC Connection LIC Connection

APE - AMC amc_err 89 none

APE - ADMA adma_err[0] 90 none

APE - ADMA adma_err[1] 91 none

APE - ADMA adma_err[2] 92 none

APE - ADMA adma_err[3] 93 none

APE - ADSP adsp_standbywfi 94 none

APE - ADSP adsp_standbywfe 95 none

APE - ADSP adsp_ctiirq 96 none

APE - AMISC ape_actmon 97 none

LIC Lic2ape_int[0] 100 none

LIC Lic2ape_int[1] 101 none

I2C1 i2c1_rupt 104 25

I2C3 i2c3_rupt 105 27

AON - I2C8 aon2lic_i2c3int 106 32

top HSP shsp2ape_db 107 none

top WDT top_wdt_fiq 108 none

top WDT top_wdt_irq 109 none

APE - ATKE atke_tmr_irq[0] 110 none

APE - ATKE atke_tmr_irq[1] 111 none

APE - ATKE atke_tmr_irq[2] 112 none

APE - ATKE atke_tmr_irq[3] 113 none

APE - ATKE atke_wdt_fiq 114 201

APE - ATKE atke_wdt_irq 115 none

APE - ATKE atke_wdt_error 116 none

APE - AGIC IRQ[0] none 145

APE - AGIC IRQ[1] none 146

APE - AGIC IRQ[2] none 147

APE - AGIC IRQ[3] none 148

APE - AGIC FIQ[0] none 149

APE - AGIC FIQ[1] none 150

APE - AGIC FIQ[2] none 151

APE - AGIC FIQ[3] none 152

For further information of the APE Interrupt controllers, refer to the Audio Processing Engine (APE) chapter of

this TRM.

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8.2.3 Interrupt Registers

LIC Registers

Note: The Interrupt controller register descriptions do not follow the standard register table protocol described in

"Reading Register Tables" in the Introduction chapter. Each register's relative offset, access type, and power-on

reset value are listed in the table below.

There are eleven slices numbered 0 to 10, each with eight channels numbered from 0 to 7. In particular, the

slice <s> is associated with the Interrupts numbered between <s>*32 and <s>*32 + 31. And each slice has:

Eight sets of 10 registers with names using the form < >_ < >_0, where

CHANNEL <SLICE>_ FUNCTION

< > (= 0, 1, ..., 7) specifies which of the eight ( 0, 1, ..., 7) channels.

CHANNEL

< > (= 0, 1, ..., 10) specifies which of the eleven (0, 1, ..., 10) slices.

SLICE

< > is the name of the register. In particular,

FUNCTION

VIRQ and VFIQ: indicate the Valid status, as an IRQ or FIQ, respectively, for this channel.

IER (Interrupt Enable Register): indicates that the corresponding Interrupt is enabled for the channel.

IER_SET and IER_CLR: to control IER, bits equal to 1 are set or cleared, respectively, in the IER

IEP_CLASS: Interrupt Enable Priority Class. A bit set to 0 indicates IRQ, and a bit set to 1 indicates FIQ.

ISR: indicates the current value of the inputs to the channel after IDR.

IDR (Interrupt Disable Register): indicates that the corresponding Interrupt is disabled for the channel.

IDR_SET and IDR_CLR: to control IDR, bits equal to 1 are set or cleared, respectively, in the IDR

Seven additional registers with names COMMON_< >_< >_0, where

SLICE FUNCTION

< > specifies which of the eleven (0, 1, ..., 10) slices.

SLICE

< > is the name of the register. In particular,

FUNCTION

GISR (Global Interrupt Status Register): indicates the status of the shared Interrupt inputs as they enter

the LIC.

FIR: indicates Force Interrupt

FIR_SET and FIR_CLR: to control FIR, bits set to 1 are set or cleared, respectively, in the FIR. The use

of SET and CLR registers avoids the need for a Read-Modify-Write operation.

CIDR (CCPLEX Interrupt Disable Register): indicates which shared Interrupts do not propagate towards

the CCPLEX.

CIDR_SET and CIDR_CLR: to control CIDR, bits set to 1 are set or cleared, respectively, in the CIDR.

The use of SET and CLR registers avoids the need for a Read-Modify-Write operation.

Common Registers per Slice and Channel

The table below summarizes each < >/< > register set in its base offset and Interrupt mapping

SLICE CHANNEL

reference.

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Table 8.10 < > > Mapping

CHANNEL /<SLICE

CHANNEL SLICE

Base Offset Mapping (Interrupt Number)

0 0 0x0000 0 to 31

1 0x0040 32 to 63 (60, 61, 63 reserved)

2 0x0080 64 to 95 (67 reserved)

3 0x00c0 96 to 127 (108, 109, 110, 111 reserved)

4 0x0100 128 to 159

5 0x0140 160 to 191 (179, 180, 181 reserved)

6 0x0180 192 to 223

7 0x01c0 224 to 255 (225 reserved)

8 0x0200 256 to 287 (256, 257, 258, 287 reserved)

9 0x0240 288 to 319

10 0x0280 320 to 351

1 0 0x0800 0 to 31

1 0x0840 32 to 63 (60, 61, 63 reserved)

2 0x0880 64 to 95 (67 reserved)

3 0x08c0 96 to 127 (108, 109, 110, 111 reserved)

4 0x0900 128 to 159

5 0x0940 160 to 191 (179, 180, 181 reserved)

6 0x0980 192 to 223

7 0x09c0 224 to 255 (225 reserved)

8 0x0a00 256 to 287 (256, 257, 258, 287 reserved)

9 0x0a40 288 to 319

10 0x0a80 320 to 351

2 0 0x1000 0 to 31

1 0x1040 32 to 63 (60, 61, 63 reserved)

2 0x1080 64 to 95 (67 reserved)

3 0x10c0 96 to 127 (108, 109, 110, 111 reserved)

4 0x1100 128 to 159

5 0x1140 160 to 191 (179, 180, 181 reserved)

6 0x1180 192 to 223

7 0x11c0 224 to 255 (225 reserved)

8 0x1200 256 to 287 (256, 257, 258, 287 reserved)

9 0x1240 288 to 319

10 0x1280 320 to 351

0x1800

0 to 31

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CHANNEL SLICE

Base Offset Mapping (Interrupt Number)

1 0x1840 32 to 63 (60, 61, 63 reserved)

2 0x1880 64 to 95 (67 reserved)

3 0x18c0 96 to 127 (108, 109, 110, 111 reserved)

4 0x1900 128 to 159

5 0x1940 160 to 191 (179, 180, 181 reserved)

6 0x1980 192 to 223

7 0x19c0 224 to 255 (225 reserved)

8 0x2000 256 to 287 (256, 257, 258, 287 reserved)

9 0x2040 288 to 319

10 0x2080 320 to 351

4 0 0x2000 0 to 31

1 0x2040 32 to 63 (60, 61, 63 reserved)

2 0x2080 64 to 95 (67 reserved)

3 0x20c0 96 to 127 (108, 109, 110, 111 reserved)

4 0x2100 128 to 159

5 0x2140 160 to 191 (179, 180, 181 reserved)

6 0x2180 192 to 223

7 0x21c0 224 to 255 (225 reserved)

8 0x2200 256 to 287 (256, 257, 258, 287 reserved)

9 0x2240 288 to 319

10 0x2280 320 to 351

5 0 0x2800 0 to 31

1 0x2840 32 to 63 (60, 61, 63 reserved)

2 0x2880 64 to 95 (67 reserved)

3 0x28c0 96 to 127 (108, 109, 110, 111 reserved)

4 0x2900 128 to 159

5 0x2940 160 to 191 (179, 180, 181 reserved)

6 0x2980 192 to 223

7 0x29c0 224 to 255 (225 reserved)

8 0x2a00 256 to 287 (256, 257, 258, 287 reserved)

9 0x2a40 288 to 319

10 0x2a80 320 to 351

0x3000

0 to 31

1 0x3040 32 to 63 (60, 61, 63 reserved)

2 0x3080 64 to 95 (67 reserved)

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CHANNEL SLICE

Base Offset Mapping (Interrupt Number)

3 0x30c0 96 to 127 (108, 109, 110, 111 reserved)

4 0x3100 128 to 159

5 0x3140 160 to 191 (179, 180, 181 reserved)

6 0x3180 192 to 223

7 0x31c0 224 to 255 (225 reserved)

8 0x3200 256 to 287 (256, 257, 258, 287 reserved)

9 0x3240 288 to 319

10 0x3280 320 to 351

7 0 0x3800 0 to 31

1 0x3840 32 to 63 (60, 61, 63 reserved)

2 0x3880 64 to 95 (67 reserved)

3 0x38c0 96 to 127 (108, 109, 110, 111 reserved)

4 0x3900 128 to 159

5 0x3940 160 to 191 (179, 180, 181 reserved)

6 0x3980 192 to 223

7 0xc39c0 224 to 255 (225 reserved)

8 0x3a00 256 to 287 (256, 257, 258, 287 reserved)

9 0x3a40 288 to 319

10 0x3a80 320 to 351

The table below lists the 10 registers common to each < >/< > combination (i.e. the < >/<

SLICE CHANNEL SLICE

> register set).

CHANNEL

Note: The actual offset for each register is the Base Offset (from the table above) plus the Relative Offset in the

table below.

Table 8.11 Register Set per < >/< >

SLICE CHANNEL

Name Relative

Offset

RD/WR Reset SCR Protection Description

INTR_CTLR_<CHANNEL>_<SLICE>_VI

RQ_0

0x00

<CHANNEL>_SC

RE_0

Valid Interrupt Request

Status Register

INTR_CTLR_<CHANNEL>_<SLICE>_VFI

Q_0

0x04 RO x FIQ Valid Interrupt Request

Status Register

INTR_CTLR_<CHANNEL>_<SLICE>_IE

R_0

0x08 RW 0 Interrupt Enable Register

INTR_CTLR_<CHANNEL>_<SLICE>_IE

R_SET_0

0x0c RW x Set Interrupt Enable Register

0x10

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Name Relative

Offset

RD/WR Reset SCR Protection Description

INTR_CTLR_<CHANNEL>_<SLICE>_IE

R_CLR_0

Clear Interrupt Enable

INTR_CTLR_<CHANNEL>_<SLICE>_IE

P_CLASS_0

0x14 RW 0 Interrupt Enable Priority

Class Register

INTR_CTLR_<CHANNEL>_<SLICE>_IS

R_0

0x18 RO 0 Interrupt Status Register

INTR_CTLR_<CHANNEL>_<SLICE>_ID

R_0

0x1c RW 0 <CHANNEL>_SC

RD_0

Interrupt Disable Register

INTR_CTLR_<CHANNEL>_<SLICE>_ID

R_SET_0

0x20 RW x Set Interrupt Disable Register

INTR_CTLR_<CHANNEL>_<SLICE>_ID

R_CLR_0

0x24 RW x Clear Interrupt Disable

Common Registers per Slice

The table below summarizes each <SLICE> register set in its base offset and Interrupt mapping reference.

Table 8.12 Common < > Mapping

SLICE

Base Offset Mapping (Interrupt Number)

0 0xf800 0 to 31

1 0xf840 32 to 63 (60, 61, 63 reserved)

2 0xf880 64 to 95 (67 reserved)

3 0xf8c0 96 to 127 (108, 109, 110, 111 reserved)

4 0xf900 128 to 159

5 0xf940 160 to 191 (179, 180, 181 reserved)

6 0xf980 192 to 223

7 0xf9c0 224 to 255 (225 reserved)

8 0xfa00 256 to 287 (256, 257, 258, 287 reserved)

9 0xfa40 288 to 319

10 0xfa80 320 to 351

The table below lists the seven common registers for each < >.

SLICE

Note: The actual offset for each register is the Base Offset (from the table above) plus the Relative Offset in the

table below.

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Table 8.13 Common Registers per < >

SLICE

Name Relative

Offset

RD/WR Reset SCR Protection Description

INTR_CTLR_COMMON_<SLICE>_GISR

0x00 RO x

SCR_COMMON_

Global Interrupt Request

Status Register

INTR_CTLR_COMMON_<SLICE>_FIR_0 0x04 RW 0 Force Interrupt Register

INTR_CTLR_COMMON_<SLICE>_FIR_S

ET_0

0x08 RW x Set Force Interrupt Register

INTR_CTLR_COMMON_<SLICE>_FIR_

CLR_0

0x0c RW x Clear Force Interrupt

INTR_CTLR_COMMON_<SLICE>_CIDR

0x10 RW 0 CCPLEX Interrupt Disable

INTR_CTLR_COMMON_<SLICE>_CIDR

_SET_0

0x14 RW x Set CCPLEX Interrupt

Disable Register

INTR_CTLR_COMMON_<SLICE>_CIDR

_CLR_0

0x18 RW x Clear CCPLEX Interrupt

Disable Register

8.2.4 Legacy Interrupt Controller (LIC) Registers

Refer to "Reading Register Tables" in the Introduction chapter for the register table protocol as well as

recommendations for accessing registers. The Base Addresses of the following registers are specified in the

Address Map section of the Xavier TRM.

INTR_CTLR_CHANNEL0_SLICE0_VIRQ_0

Offset: 0x0

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL0_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X VIRQ

INTR_CTLR_CHANNEL0_SLICE0_VFIQ_0

Offset: 0x4

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL0_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

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Bit Reset Description

31:0 X VFIQ

INTR_CTLR_CHANNEL0_SLICE0_IER_0

Offset: 0x8

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL0_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 IER

INTR_CTLR_CHANNEL0_SLICE0_IER_SET_0

Offset: 0xc

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL0_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X IER_SET

INTR_CTLR_CHANNEL0_SLICE0_IER_CLR_0

Offset: 0x10

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL0_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X IER_CLR

INTR_CTLR_CHANNEL0_SLICE0_IEP_CLASS_0

Offset: 0x14

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL0_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

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Bit Reset Description

31:0 0x0 IEP_CLASS

INTR_CTLR_CHANNEL0_SLICE0_ISR_0

Offset: 0x18

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL0_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

ISR

INTR_CTLR_CHANNEL0_SLICE0_IDR_0

Offset: 0x1c

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL0_SCRD_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 IDR

INTR_CTLR_CHANNEL0_SLICE0_IDR_SET_0

Offset: 0x20

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL0_SCRD_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X IDR_SET

INTR_CTLR_CHANNEL0_SLICE0_IDR_CLR_0

Offset: 0x24

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL0_SCRD_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

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Bit Reset Description

31:0 X IDR_CLR

INTR_CTLR_CHANNEL0_SLICE1_VIRQ_0

Offset: 0x40

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL0_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X VIRQ

INTR_CTLR_CHANNEL0_SLICE1_VFIQ_0

Offset: 0x44

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL0_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X

VFIQ

INTR_CTLR_CHANNEL0_SLICE1_IER_0

Offset: 0x48

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL0_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 IER

INTR_CTLR_CHANNEL0_SLICE1_IER_SET_0

Offset: 0x4c

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL0_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

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Bit Reset Description

31:0 X IER_SET

INTR_CTLR_CHANNEL0_SLICE1_IER_CLR_0

Offset: 0x50

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL0_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X IER_CLR

INTR_CTLR_CHANNEL0_SLICE1_IEP_CLASS_0

Offset: 0x54

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL0_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 IEP_CLASS

INTR_CTLR_CHANNEL0_SLICE1_ISR_0

Offset: 0x58

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL0_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

ISR

INTR_CTLR_CHANNEL0_SLICE1_IDR_0

Offset: 0x5c

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL0_SCRD_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

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Bit Reset Description

31:0 0x0

IDR

INTR_CTLR_CHANNEL0_SLICE1_IDR_SET_0

Offset: 0x60

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL0_SCRD_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X IDR_SET

INTR_CTLR_CHANNEL0_SLICE1_IDR_CLR_0

Offset: 0x64

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL0_SCRD_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X IDR_CLR

INTR_CTLR_CHANNEL0_SLICE2_VIRQ_0

Offset: 0x80

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL0_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X VIRQ

INTR_CTLR_CHANNEL0_SLICE2_VFIQ_0

Offset: 0x84

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL0_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

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Bit Reset Description

31:0 X VFIQ

INTR_CTLR_CHANNEL0_SLICE2_IER_0

Offset: 0x88

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL0_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

IER

INTR_CTLR_CHANNEL0_SLICE2_IER_SET_0

Offset: 0x8c

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL0_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X IER_SET

INTR_CTLR_CHANNEL0_SLICE2_IER_CLR_0

Offset: 0x90

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL0_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X IER_CLR

INTR_CTLR_CHANNEL0_SLICE2_IEP_CLASS_0

Offset: 0x94

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL0_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

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Bit Reset Description

31:0 0x0 IEP_CLASS

INTR_CTLR_CHANNEL0_SLICE2_ISR_0

Offset: 0x98

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL0_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 ISR

INTR_CTLR_CHANNEL0_SLICE2_IDR_0

Offset: 0x9c

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL0_SCRD_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

IDR

INTR_CTLR_CHANNEL0_SLICE2_IDR_SET_0

Offset: 0xa0

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL0_SCRD_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X IDR_SET

INTR_CTLR_CHANNEL0_SLICE2_IDR_CLR_0

Offset: 0xa4

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL0_SCRD_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

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Bit Reset Description

31:0 X IDR_CLR

INTR_CTLR_CHANNEL0_SLICE3_VIRQ_0

Offset: 0xc0

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL0_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X VIRQ

INTR_CTLR_CHANNEL0_SLICE3_VFIQ_0

Offset: 0xc4

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL0_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X VFIQ

INTR_CTLR_CHANNEL0_SLICE3_IER_0

Offset: 0xc8

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL0_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

IER

INTR_CTLR_CHANNEL0_SLICE3_IER_SET_0

Offset: 0xcc

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL0_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

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Bit Reset Description

31:0 X

IER_SET

INTR_CTLR_CHANNEL0_SLICE3_IER_CLR_0

Offset: 0xd0

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL0_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X IER_CLR

INTR_CTLR_CHANNEL0_SLICE3_IEP_CLASS_0

Offset: 0xd4

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL0_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 IEP_CLASS

INTR_CTLR_CHANNEL0_SLICE3_ISR_0

Offset: 0xd8

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL0_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 ISR

INTR_CTLR_CHANNEL0_SLICE3_IDR_0

Offset: 0xdc

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL0_SCRD_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

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Bit Reset Description

31:0 0x0 IDR

INTR_CTLR_CHANNEL0_SLICE3_IDR_SET_0

Offset: 0xe0

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL0_SCRD_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X

IDR_SET

INTR_CTLR_CHANNEL0_SLICE3_IDR_CLR_0

Offset: 0xe4

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL0_SCRD_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X IDR_CLR

INTR_CTLR_CHANNEL0_SLICE4_VIRQ_0

Offset: 0x100

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL0_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X VIRQ

INTR_CTLR_CHANNEL0_SLICE4_VFIQ_0

Offset: 0x104

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL0_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

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Bit Reset Description

31:0 X VFIQ

INTR_CTLR_CHANNEL0_SLICE4_IER_0

Offset: 0x108

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL0_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 IER

INTR_CTLR_CHANNEL0_SLICE4_IER_SET_0

Offset: 0x10c

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL0_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X

IER_SET

INTR_CTLR_CHANNEL0_SLICE4_IER_CLR_0

Offset: 0x110

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL0_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X IER_CLR

INTR_CTLR_CHANNEL0_SLICE4_IEP_CLASS_0

Offset: 0x114

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL0_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

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Bit Reset Description

31:0 0x0 IEP_CLASS

INTR_CTLR_CHANNEL0_SLICE4_ISR_0

Offset: 0x118

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL0_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 ISR

INTR_CTLR_CHANNEL0_SLICE4_IDR_0

Offset: 0x11c

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL0_SCRD_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 IDR

INTR_CTLR_CHANNEL0_SLICE4_IDR_SET_0

Offset: 0x120

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL0_SCRD_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X

IDR_SET

INTR_CTLR_CHANNEL0_SLICE4_IDR_CLR_0

Offset: 0x124

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL0_SCRD_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

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Bit Reset Description

31:0 X

IDR_CLR

INTR_CTLR_CHANNEL0_SLICE5_VIRQ_0

Offset: 0x140

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL0_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X VIRQ

INTR_CTLR_CHANNEL0_SLICE5_VFIQ_0

Offset: 0x144

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL0_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X VFIQ

INTR_CTLR_CHANNEL0_SLICE5_IER_0

Offset: 0x148

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL0_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 IER

INTR_CTLR_CHANNEL0_SLICE5_IER_SET_0

Offset: 0x14c

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL0_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

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Bit Reset Description

31:0 X IER_SET

INTR_CTLR_CHANNEL0_SLICE5_IER_CLR_0

Offset: 0x150

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL0_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X

IER_CLR

INTR_CTLR_CHANNEL0_SLICE5_IEP_CLASS_0

Offset: 0x154

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL0_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 IEP_CLASS

INTR_CTLR_CHANNEL0_SLICE5_ISR_0

Offset: 0x158

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL0_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 ISR

INTR_CTLR_CHANNEL0_SLICE5_IDR_0

Offset: 0x15c

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL0_SCRD_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

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Bit Reset Description

31:0 0x0 IDR

INTR_CTLR_CHANNEL0_SLICE5_IDR_SET_0

Offset: 0x160

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL0_SCRD_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X IDR_SET

INTR_CTLR_CHANNEL0_SLICE5_IDR_CLR_0

Offset: 0x164

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL0_SCRD_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X

IDR_CLR

INTR_CTLR_CHANNEL0_SLICE6_VIRQ_0

Offset: 0x180

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL0_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X VIRQ

INTR_CTLR_CHANNEL0_SLICE6_VFIQ_0

Offset: 0x184

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL0_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

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Bit Reset Description

31:0 X VFIQ

INTR_CTLR_CHANNEL0_SLICE6_IER_0

Offset: 0x188

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL0_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 IER

INTR_CTLR_CHANNEL0_SLICE6_IER_SET_0

Offset: 0x18c

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL0_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X IER_SET

INTR_CTLR_CHANNEL0_SLICE6_IER_CLR_0

Offset: 0x190

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL0_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X

IER_CLR

INTR_CTLR_CHANNEL0_SLICE6_IEP_CLASS_0

Offset: 0x194

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL0_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

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Bit Reset Description

31:0 0x0

IEP_CLASS

INTR_CTLR_CHANNEL0_SLICE6_ISR_0

Offset: 0x198

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL0_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 ISR

INTR_CTLR_CHANNEL0_SLICE6_IDR_0

Offset: 0x19c

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL0_SCRD_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 IDR

INTR_CTLR_CHANNEL0_SLICE6_IDR_SET_0

Offset: 0x1a0

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL0_SCRD_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X IDR_SET

INTR_CTLR_CHANNEL0_SLICE6_IDR_CLR_0

Offset: 0x1a4

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL0_SCRD_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

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Bit Reset Description

31:0 X IDR_CLR

INTR_CTLR_CHANNEL0_SLICE7_VIRQ_0

Offset: 0x1c0

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL0_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X

VIRQ

INTR_CTLR_CHANNEL0_SLICE7_VFIQ_0

Offset: 0x1c4

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL0_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X VFIQ

INTR_CTLR_CHANNEL0_SLICE7_IER_0

Offset: 0x1c8

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL0_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 IER

INTR_CTLR_CHANNEL0_SLICE7_IER_SET_0

Offset: 0x1cc

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL0_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

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Bit Reset Description

31:0 X IER_SET

INTR_CTLR_CHANNEL0_SLICE7_IER_CLR_0

Offset: 0x1d0

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL0_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X IER_CLR

INTR_CTLR_CHANNEL0_SLICE7_IEP_CLASS_0

Offset: 0x1d4

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL0_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

IEP_CLASS

INTR_CTLR_CHANNEL0_SLICE7_ISR_0

Offset: 0x1d8

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL0_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 ISR

INTR_CTLR_CHANNEL0_SLICE7_IDR_0

Offset: 0x1dc

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL0_SCRD_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

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Bit Reset Description

31:0 0x0 IDR

INTR_CTLR_CHANNEL0_SLICE7_IDR_SET_0

Offset: 0x1e0

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL0_SCRD_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X IDR_SET

INTR_CTLR_CHANNEL0_SLICE7_IDR_CLR_0

Offset: 0x1e4

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL0_SCRD_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X IDR_CLR

INTR_CTLR_CHANNEL0_SLICE8_VIRQ_0

Offset: 0x200

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL0_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X

VIRQ

INTR_CTLR_CHANNEL0_SLICE8_VFIQ_0

Offset: 0x204

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL0_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

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Bit Reset Description

31:0 X

VFIQ

INTR_CTLR_CHANNEL0_SLICE8_IER_0

Offset: 0x208

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL0_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 IER

INTR_CTLR_CHANNEL0_SLICE8_IER_SET_0

Offset: 0x20c

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL0_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X IER_SET

INTR_CTLR_CHANNEL0_SLICE8_IER_CLR_0

Offset: 0x210

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL0_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X IER_CLR

INTR_CTLR_CHANNEL0_SLICE8_IEP_CLASS_0

Offset: 0x214

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL0_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

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Bit Reset Description

31:0 0x0 IEP_CLASS

INTR_CTLR_CHANNEL0_SLICE8_ISR_0

Offset: 0x218

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL0_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

ISR

INTR_CTLR_CHANNEL0_SLICE8_IDR_0

Offset: 0x21c

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL0_SCRD_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 IDR

INTR_CTLR_CHANNEL0_SLICE8_IDR_SET_0

Offset: 0x220

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL0_SCRD_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X IDR_SET

INTR_CTLR_CHANNEL0_SLICE8_IDR_CLR_0

Offset: 0x224

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL0_SCRD_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

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Bit Reset Description

31:0 X IDR_CLR

INTR_CTLR_CHANNEL0_SLICE9_VIRQ_0

Offset: 0x240

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL0_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X VIRQ

INTR_CTLR_CHANNEL0_SLICE9_VFIQ_0

Offset: 0x244

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL0_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X

VFIQ

INTR_CTLR_CHANNEL0_SLICE9_IER_0

Offset: 0x248

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL0_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 IER

INTR_CTLR_CHANNEL0_SLICE9_IER_SET_0

Offset: 0x24c

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL0_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

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Bit Reset Description

31:0 X IER_SET

INTR_CTLR_CHANNEL0_SLICE9_IER_CLR_0

Offset: 0x250

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL0_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X IER_CLR

INTR_CTLR_CHANNEL0_SLICE9_IEP_CLASS_0

Offset: 0x254

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL0_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 IEP_CLASS

INTR_CTLR_CHANNEL0_SLICE9_ISR_0

Offset: 0x258

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL0_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

ISR

INTR_CTLR_CHANNEL0_SLICE9_IDR_0

Offset: 0x25c

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL0_SCRD_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

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Bit Reset Description

31:0 0x0

IDR

INTR_CTLR_CHANNEL0_SLICE9_IDR_SET_0

Offset: 0x260

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL0_SCRD_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X IDR_SET

INTR_CTLR_CHANNEL0_SLICE9_IDR_CLR_0

Offset: 0x264

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL0_SCRD_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X IDR_CLR

INTR_CTLR_CHANNEL0_SLICE10_VIRQ_0

Offset: 0x280

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL0_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X VIRQ

INTR_CTLR_CHANNEL0_SLICE10_VFIQ_0

Offset: 0x284

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL0_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

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Bit Reset Description

31:0 X VFIQ

INTR_CTLR_CHANNEL0_SLICE10_IER_0

Offset: 0x288

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL0_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

IER

INTR_CTLR_CHANNEL0_SLICE10_IER_SET_0

Offset: 0x28c

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL0_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X IER_SET

INTR_CTLR_CHANNEL0_SLICE10_IER_CLR_0

Offset: 0x290

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL0_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X IER_CLR

INTR_CTLR_CHANNEL0_SLICE10_IEP_CLASS_0

Offset: 0x294

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL0_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

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Bit Reset Description

31:0 0x0 IEP_CLASS

INTR_CTLR_CHANNEL0_SLICE10_ISR_0

Offset: 0x298

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL0_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 ISR

INTR_CTLR_CHANNEL0_SLICE10_IDR_0

Offset: 0x29c

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL0_SCRD_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

IDR

INTR_CTLR_CHANNEL0_SLICE10_IDR_SET_0

Offset: 0x2a0

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL0_SCRD_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X IDR_SET

INTR_CTLR_CHANNEL0_SLICE10_IDR_CLR_0

Offset: 0x2a4

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL0_SCRD_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

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Bit Reset Description

31:0 X IDR_CLR

INTR_CTLR_CHANNEL1_SLICE0_VIRQ_0

Offset: 0x800

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL1_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X VIRQ

INTR_CTLR_CHANNEL1_SLICE0_VFIQ_0

Offset: 0x804

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL1_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X VFIQ

INTR_CTLR_CHANNEL1_SLICE0_IER_0

Offset: 0x808

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL1_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

IER

INTR_CTLR_CHANNEL1_SLICE0_IER_SET_0

Offset: 0x80c

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL1_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

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Bit Reset Description

31:0 X

IER_SET

INTR_CTLR_CHANNEL1_SLICE0_IER_CLR_0

Offset: 0x810

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL1_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X IER_CLR

INTR_CTLR_CHANNEL1_SLICE0_IEP_CLASS_0

Offset: 0x814

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL1_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 IEP_CLASS

INTR_CTLR_CHANNEL1_SLICE0_ISR_0

Offset: 0x818

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL1_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 ISR

INTR_CTLR_CHANNEL1_SLICE0_IDR_0

Offset: 0x81c

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL1_SCRD_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

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Bit Reset Description

31:0 0x0 IDR

INTR_CTLR_CHANNEL1_SLICE0_IDR_SET_0

Offset: 0x820

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL1_SCRD_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X

IDR_SET

INTR_CTLR_CHANNEL1_SLICE0_IDR_CLR_0

Offset: 0x824

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL1_SCRD_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X IDR_CLR

INTR_CTLR_CHANNEL1_SLICE1_VIRQ_0

Offset: 0x840

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL1_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X VIRQ

INTR_CTLR_CHANNEL1_SLICE1_VFIQ_0

Offset: 0x844

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL1_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

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Bit Reset Description

31:0 X VFIQ

INTR_CTLR_CHANNEL1_SLICE1_IER_0

Offset: 0x848

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL1_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 IER

INTR_CTLR_CHANNEL1_SLICE1_IER_SET_0

Offset: 0x84c

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL1_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X

IER_SET

INTR_CTLR_CHANNEL1_SLICE1_IER_CLR_0

Offset: 0x850

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL1_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X IER_CLR

INTR_CTLR_CHANNEL1_SLICE1_IEP_CLASS_0

Offset: 0x854

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL1_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

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Bit Reset Description

31:0 0x0 IEP_CLASS

INTR_CTLR_CHANNEL1_SLICE1_ISR_0

Offset: 0x858

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL1_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 ISR

INTR_CTLR_CHANNEL1_SLICE1_IDR_0

Offset: 0x85c

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL1_SCRD_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 IDR

INTR_CTLR_CHANNEL1_SLICE1_IDR_SET_0

Offset: 0x860

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL1_SCRD_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X

IDR_SET

INTR_CTLR_CHANNEL1_SLICE1_IDR_CLR_0

Offset: 0x864

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL1_SCRD_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

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Bit Reset Description

31:0 X

IDR_CLR

INTR_CTLR_CHANNEL1_SLICE2_VIRQ_0

Offset: 0x880

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL1_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X VIRQ

INTR_CTLR_CHANNEL1_SLICE2_VFIQ_0

Offset: 0x884

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL1_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X VFIQ

INTR_CTLR_CHANNEL1_SLICE2_IER_0

Offset: 0x888

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL1_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 IER

INTR_CTLR_CHANNEL1_SLICE2_IER_SET_0

Offset: 0x88c

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL1_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

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Bit Reset Description

31:0 X IER_SET

INTR_CTLR_CHANNEL1_SLICE2_IER_CLR_0

Offset: 0x890

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL1_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X

IER_CLR

INTR_CTLR_CHANNEL1_SLICE2_IEP_CLASS_0

Offset: 0x894

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL1_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 IEP_CLASS

INTR_CTLR_CHANNEL1_SLICE2_ISR_0

Offset: 0x898

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL1_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 ISR

INTR_CTLR_CHANNEL1_SLICE2_IDR_0

Offset: 0x89c

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL1_SCRD_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

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Bit Reset Description

31:0 0x0 IDR

INTR_CTLR_CHANNEL1_SLICE2_IDR_SET_0

Offset: 0x8a0

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL1_SCRD_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X IDR_SET

INTR_CTLR_CHANNEL1_SLICE2_IDR_CLR_0

Offset: 0x8a4

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL1_SCRD_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X

IDR_CLR

INTR_CTLR_CHANNEL1_SLICE3_VIRQ_0

Offset: 0x8c0

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL1_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X VIRQ

INTR_CTLR_CHANNEL1_SLICE3_VFIQ_0

Offset: 0x8c4

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL1_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

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Bit Reset Description

31:0 X VFIQ

INTR_CTLR_CHANNEL1_SLICE3_IER_0

Offset: 0x8c8

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL1_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 IER

INTR_CTLR_CHANNEL1_SLICE3_IER_SET_0

Offset: 0x8cc

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL1_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X IER_SET

INTR_CTLR_CHANNEL1_SLICE3_IER_CLR_0

Offset: 0x8d0

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL1_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X

IER_CLR

INTR_CTLR_CHANNEL1_SLICE3_IEP_CLASS_0

Offset: 0x8d4

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL1_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

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Bit Reset Description

31:0 0x0

IEP_CLASS

INTR_CTLR_CHANNEL1_SLICE3_ISR_0

Offset: 0x8d8

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL1_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 ISR

INTR_CTLR_CHANNEL1_SLICE3_IDR_0

Offset: 0x8dc

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL1_SCRD_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 IDR

INTR_CTLR_CHANNEL1_SLICE3_IDR_SET_0

Offset: 0x8e0

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL1_SCRD_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X IDR_SET

INTR_CTLR_CHANNEL1_SLICE3_IDR_CLR_0

Offset: 0x8e4

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL1_SCRD_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

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Bit Reset Description

31:0 X IDR_CLR

INTR_CTLR_CHANNEL1_SLICE4_VIRQ_0

Offset: 0x900

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL1_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X

VIRQ

INTR_CTLR_CHANNEL1_SLICE4_VFIQ_0

Offset: 0x904

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL1_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X VFIQ

INTR_CTLR_CHANNEL1_SLICE4_IER_0

Offset: 0x908

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL1_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 IER

INTR_CTLR_CHANNEL1_SLICE4_IER_SET_0

Offset: 0x90c

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL1_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

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Bit Reset Description

31:0 X IER_SET

INTR_CTLR_CHANNEL1_SLICE4_IER_CLR_0

Offset: 0x910

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL1_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X IER_CLR

INTR_CTLR_CHANNEL1_SLICE4_IEP_CLASS_0

Offset: 0x914

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL1_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

IEP_CLASS

INTR_CTLR_CHANNEL1_SLICE4_ISR_0

Offset: 0x918

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL1_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 ISR

INTR_CTLR_CHANNEL1_SLICE4_IDR_0

Offset: 0x91c

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL1_SCRD_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

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Bit Reset Description

31:0 0x0 IDR

INTR_CTLR_CHANNEL1_SLICE4_IDR_SET_0

Offset: 0x920

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL1_SCRD_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X IDR_SET

INTR_CTLR_CHANNEL1_SLICE4_IDR_CLR_0

Offset: 0x924

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL1_SCRD_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X IDR_CLR

INTR_CTLR_CHANNEL1_SLICE5_VIRQ_0

Offset: 0x940

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL1_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X

VIRQ

INTR_CTLR_CHANNEL1_SLICE5_VFIQ_0

Offset: 0x944

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL1_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

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Bit Reset Description

31:0 X

VFIQ

INTR_CTLR_CHANNEL1_SLICE5_IER_0

Offset: 0x948

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL1_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 IER

INTR_CTLR_CHANNEL1_SLICE5_IER_SET_0

Offset: 0x94c

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL1_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X IER_SET

INTR_CTLR_CHANNEL1_SLICE5_IER_CLR_0

Offset: 0x950

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL1_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X IER_CLR

INTR_CTLR_CHANNEL1_SLICE5_IEP_CLASS_0

Offset: 0x954

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL1_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

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Bit Reset Description

31:0 0x0 IEP_CLASS

INTR_CTLR_CHANNEL1_SLICE5_ISR_0

Offset: 0x958

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL1_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

ISR

INTR_CTLR_CHANNEL1_SLICE5_IDR_0

Offset: 0x95c

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL1_SCRD_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 IDR

INTR_CTLR_CHANNEL1_SLICE5_IDR_SET_0

Offset: 0x960

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL1_SCRD_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X IDR_SET

INTR_CTLR_CHANNEL1_SLICE5_IDR_CLR_0

Offset: 0x964

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL1_SCRD_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

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Bit Reset Description

31:0 X IDR_CLR

INTR_CTLR_CHANNEL1_SLICE6_VIRQ_0

Offset: 0x980

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL1_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X VIRQ

INTR_CTLR_CHANNEL1_SLICE6_VFIQ_0

Offset: 0x984

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL1_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X

VFIQ

INTR_CTLR_CHANNEL1_SLICE6_IER_0

Offset: 0x988

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL1_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 IER

INTR_CTLR_CHANNEL1_SLICE6_IER_SET_0

Offset: 0x98c

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL1_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

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Bit Reset Description

31:0 X IER_SET

INTR_CTLR_CHANNEL1_SLICE6_IER_CLR_0

Offset: 0x990

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL1_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X IER_CLR

INTR_CTLR_CHANNEL1_SLICE6_IEP_CLASS_0

Offset: 0x994

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL1_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 IEP_CLASS

INTR_CTLR_CHANNEL1_SLICE6_ISR_0

Offset: 0x998

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL1_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

ISR

INTR_CTLR_CHANNEL1_SLICE6_IDR_0

Offset: 0x99c

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL1_SCRD_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

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Bit Reset Description

31:0 0x0

IDR

INTR_CTLR_CHANNEL1_SLICE6_IDR_SET_0

Offset: 0x9a0

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL1_SCRD_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X IDR_SET

INTR_CTLR_CHANNEL1_SLICE6_IDR_CLR_0

Offset: 0x9a4

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL1_SCRD_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X IDR_CLR

INTR_CTLR_CHANNEL1_SLICE7_VIRQ_0

Offset: 0x9c0

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL1_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X VIRQ

INTR_CTLR_CHANNEL1_SLICE7_VFIQ_0

Offset: 0x9c4

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL1_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

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Bit Reset Description

31:0 X VFIQ

INTR_CTLR_CHANNEL1_SLICE7_IER_0

Offset: 0x9c8

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL1_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

IER

INTR_CTLR_CHANNEL1_SLICE7_IER_SET_0

Offset: 0x9cc

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL1_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X IER_SET

INTR_CTLR_CHANNEL1_SLICE7_IER_CLR_0

Offset: 0x9d0

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL1_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X IER_CLR

INTR_CTLR_CHANNEL1_SLICE7_IEP_CLASS_0

Offset: 0x9d4

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL1_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

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Bit Reset Description

31:0 0x0 IEP_CLASS

INTR_CTLR_CHANNEL1_SLICE7_ISR_0

Offset: 0x9d8

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL1_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 ISR

INTR_CTLR_CHANNEL1_SLICE7_IDR_0

Offset: 0x9dc

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL1_SCRD_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

IDR

INTR_CTLR_CHANNEL1_SLICE7_IDR_SET_0

Offset: 0x9e0

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL1_SCRD_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X IDR_SET

INTR_CTLR_CHANNEL1_SLICE7_IDR_CLR_0

Offset: 0x9e4

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL1_SCRD_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

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Bit Reset Description

31:0 X IDR_CLR

INTR_CTLR_CHANNEL1_SLICE8_VIRQ_0

Offset: 0xa00

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL1_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X VIRQ

INTR_CTLR_CHANNEL1_SLICE8_VFIQ_0

Offset: 0xa04

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL1_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X VFIQ

INTR_CTLR_CHANNEL1_SLICE8_IER_0

Offset: 0xa08

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL1_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

IER

INTR_CTLR_CHANNEL1_SLICE8_IER_SET_0

Offset: 0xa0c

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL1_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

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Bit Reset Description

31:0 X

IER_SET

INTR_CTLR_CHANNEL1_SLICE8_IER_CLR_0

Offset: 0xa10

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL1_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X IER_CLR

INTR_CTLR_CHANNEL1_SLICE8_IEP_CLASS_0

Offset: 0xa14

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL1_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 IEP_CLASS

INTR_CTLR_CHANNEL1_SLICE8_ISR_0

Offset: 0xa18

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL1_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 ISR

INTR_CTLR_CHANNEL1_SLICE8_IDR_0

Offset: 0xa1c

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL1_SCRD_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

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Bit Reset Description

31:0 0x0 IDR

INTR_CTLR_CHANNEL1_SLICE8_IDR_SET_0

Offset: 0xa20

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL1_SCRD_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X

IDR_SET

INTR_CTLR_CHANNEL1_SLICE8_IDR_CLR_0

Offset: 0xa24

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL1_SCRD_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X IDR_CLR

INTR_CTLR_CHANNEL1_SLICE9_VIRQ_0

Offset: 0xa40

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL1_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X VIRQ

INTR_CTLR_CHANNEL1_SLICE9_VFIQ_0

Offset: 0xa44

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL1_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

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Bit Reset Description

31:0 X VFIQ

INTR_CTLR_CHANNEL1_SLICE9_IER_0

Offset: 0xa48

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL1_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 IER

INTR_CTLR_CHANNEL1_SLICE9_IER_SET_0

Offset: 0xa4c

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL1_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X

IER_SET

INTR_CTLR_CHANNEL1_SLICE9_IER_CLR_0

Offset: 0xa50

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL1_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X IER_CLR

INTR_CTLR_CHANNEL1_SLICE9_IEP_CLASS_0

Offset: 0xa54

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL1_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

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Bit Reset Description

31:0 0x0 IEP_CLASS

INTR_CTLR_CHANNEL1_SLICE9_ISR_0

Offset: 0xa58

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL1_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 ISR

INTR_CTLR_CHANNEL1_SLICE9_IDR_0

Offset: 0xa5c

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL1_SCRD_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 IDR

INTR_CTLR_CHANNEL1_SLICE9_IDR_SET_0

Offset: 0xa60

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL1_SCRD_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X

IDR_SET

INTR_CTLR_CHANNEL1_SLICE9_IDR_CLR_0

Offset: 0xa64

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL1_SCRD_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

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Bit Reset Description

31:0 X

IDR_CLR

INTR_CTLR_CHANNEL1_SLICE10_VIRQ_0

Offset: 0xa80

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL1_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X VIRQ

INTR_CTLR_CHANNEL1_SLICE10_VFIQ_0

Offset: 0xa84

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL1_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X VFIQ

INTR_CTLR_CHANNEL1_SLICE10_IER_0

Offset: 0xa88

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL1_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 IER

INTR_CTLR_CHANNEL1_SLICE10_IER_SET_0

Offset: 0xa8c

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL1_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

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Bit Reset Description

31:0 X IER_SET

INTR_CTLR_CHANNEL1_SLICE10_IER_CLR_0

Offset: 0xa90

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL1_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X

IER_CLR

INTR_CTLR_CHANNEL1_SLICE10_IEP_CLASS_0

Offset: 0xa94

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL1_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 IEP_CLASS

INTR_CTLR_CHANNEL1_SLICE10_ISR_0

Offset: 0xa98

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL1_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 ISR

INTR_CTLR_CHANNEL1_SLICE10_IDR_0

Offset: 0xa9c

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL1_SCRD_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

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Bit Reset Description

31:0 0x0 IDR

INTR_CTLR_CHANNEL1_SLICE10_IDR_SET_0

Offset: 0xaa0

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL1_SCRD_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X IDR_SET

INTR_CTLR_CHANNEL1_SLICE10_IDR_CLR_0

Offset: 0xaa4

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL1_SCRD_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X

IDR_CLR

INTR_CTLR_CHANNEL2_SLICE0_VIRQ_0

Offset: 0x1000

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL2_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X VIRQ

INTR_CTLR_CHANNEL2_SLICE0_VFIQ_0

Offset: 0x1004

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL2_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

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Bit Reset Description

31:0 X VFIQ

INTR_CTLR_CHANNEL2_SLICE0_IER_0

Offset: 0x1008

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL2_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 IER

INTR_CTLR_CHANNEL2_SLICE0_IER_SET_0

Offset: 0x100c

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL2_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X IER_SET

INTR_CTLR_CHANNEL2_SLICE0_IER_CLR_0

Offset: 0x1010

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL2_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X

IER_CLR

INTR_CTLR_CHANNEL2_SLICE0_IEP_CLASS_0

Offset: 0x1014

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL2_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

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Bit Reset Description

31:0 0x0

IEP_CLASS

INTR_CTLR_CHANNEL2_SLICE0_ISR_0

Offset: 0x1018

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL2_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 ISR

INTR_CTLR_CHANNEL2_SLICE0_IDR_0

Offset: 0x101c

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL2_SCRD_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 IDR

INTR_CTLR_CHANNEL2_SLICE0_IDR_SET_0

Offset: 0x1020

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL2_SCRD_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X IDR_SET

INTR_CTLR_CHANNEL2_SLICE0_IDR_CLR_0

Offset: 0x1024

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL2_SCRD_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

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Bit Reset Description

31:0 X IDR_CLR

INTR_CTLR_CHANNEL2_SLICE1_VIRQ_0

Offset: 0x1040

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL2_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X

VIRQ

INTR_CTLR_CHANNEL2_SLICE1_VFIQ_0

Offset: 0x1044

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL2_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X VFIQ

INTR_CTLR_CHANNEL2_SLICE1_IER_0

Offset: 0x1048

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL2_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 IER

INTR_CTLR_CHANNEL2_SLICE1_IER_SET_0

Offset: 0x104c

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL2_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

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Bit Reset Description

31:0 X IER_SET

INTR_CTLR_CHANNEL2_SLICE1_IER_CLR_0

Offset: 0x1050

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL2_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X IER_CLR

INTR_CTLR_CHANNEL2_SLICE1_IEP_CLASS_0

Offset: 0x1054

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL2_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

IEP_CLASS

INTR_CTLR_CHANNEL2_SLICE1_ISR_0

Offset: 0x1058

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL2_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 ISR

INTR_CTLR_CHANNEL2_SLICE1_IDR_0

Offset: 0x105c

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL2_SCRD_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

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Bit Reset Description

31:0 0x0 IDR

INTR_CTLR_CHANNEL2_SLICE1_IDR_SET_0

Offset: 0x1060

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL2_SCRD_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X IDR_SET

INTR_CTLR_CHANNEL2_SLICE1_IDR_CLR_0

Offset: 0x1064

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL2_SCRD_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X IDR_CLR

INTR_CTLR_CHANNEL2_SLICE2_VIRQ_0

Offset: 0x1080

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL2_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X

VIRQ

INTR_CTLR_CHANNEL2_SLICE2_VFIQ_0

Offset: 0x1084

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL2_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

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Bit Reset Description

31:0 X

VFIQ

INTR_CTLR_CHANNEL2_SLICE2_IER_0

Offset: 0x1088

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL2_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 IER

INTR_CTLR_CHANNEL2_SLICE2_IER_SET_0

Offset: 0x108c

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL2_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X IER_SET

INTR_CTLR_CHANNEL2_SLICE2_IER_CLR_0

Offset: 0x1090

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL2_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X IER_CLR

INTR_CTLR_CHANNEL2_SLICE2_IEP_CLASS_0

Offset: 0x1094

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL2_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

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Bit Reset Description

31:0 0x0 IEP_CLASS

INTR_CTLR_CHANNEL2_SLICE2_ISR_0

Offset: 0x1098

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL2_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

ISR

INTR_CTLR_CHANNEL2_SLICE2_IDR_0

Offset: 0x109c

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL2_SCRD_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 IDR

INTR_CTLR_CHANNEL2_SLICE2_IDR_SET_0

Offset: 0x10a0

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL2_SCRD_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X IDR_SET

INTR_CTLR_CHANNEL2_SLICE2_IDR_CLR_0

Offset: 0x10a4

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL2_SCRD_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

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Bit Reset Description

31:0 X IDR_CLR

INTR_CTLR_CHANNEL2_SLICE3_VIRQ_0

Offset: 0x10c0

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL2_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X VIRQ

INTR_CTLR_CHANNEL2_SLICE3_VFIQ_0

Offset: 0x10c4

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL2_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X

VFIQ

INTR_CTLR_CHANNEL2_SLICE3_IER_0

Offset: 0x10c8

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL2_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 IER

INTR_CTLR_CHANNEL2_SLICE3_IER_SET_0

Offset: 0x10cc

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL2_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

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Bit Reset Description

31:0 X IER_SET

INTR_CTLR_CHANNEL2_SLICE3_IER_CLR_0

Offset: 0x10d0

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL2_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X IER_CLR

INTR_CTLR_CHANNEL2_SLICE3_IEP_CLASS_0

Offset: 0x10d4

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL2_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 IEP_CLASS

INTR_CTLR_CHANNEL2_SLICE3_ISR_0

Offset: 0x10d8

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL2_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

ISR

INTR_CTLR_CHANNEL2_SLICE3_IDR_0

Offset: 0x10dc

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL2_SCRD_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

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Bit Reset Description

31:0 0x0

IDR

INTR_CTLR_CHANNEL2_SLICE3_IDR_SET_0

Offset: 0x10e0

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL2_SCRD_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X IDR_SET

INTR_CTLR_CHANNEL2_SLICE3_IDR_CLR_0

Offset: 0x10e4

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL2_SCRD_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X IDR_CLR

INTR_CTLR_CHANNEL2_SLICE4_VIRQ_0

Offset: 0x1100

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL2_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X VIRQ

INTR_CTLR_CHANNEL2_SLICE4_VFIQ_0

Offset: 0x1104

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL2_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

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Bit Reset Description

31:0 X VFIQ

INTR_CTLR_CHANNEL2_SLICE4_IER_0

Offset: 0x1108

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL2_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

IER

INTR_CTLR_CHANNEL2_SLICE4_IER_SET_0

Offset: 0x110c

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL2_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X IER_SET

INTR_CTLR_CHANNEL2_SLICE4_IER_CLR_0

Offset: 0x1110

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL2_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X IER_CLR

INTR_CTLR_CHANNEL2_SLICE4_IEP_CLASS_0

Offset: 0x1114

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL2_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

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Bit Reset Description

31:0 0x0 IEP_CLASS

INTR_CTLR_CHANNEL2_SLICE4_ISR_0

Offset: 0x1118

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL2_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 ISR

INTR_CTLR_CHANNEL2_SLICE4_IDR_0

Offset: 0x111c

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL2_SCRD_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

IDR

INTR_CTLR_CHANNEL2_SLICE4_IDR_SET_0

Offset: 0x1120

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL2_SCRD_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X IDR_SET

INTR_CTLR_CHANNEL2_SLICE4_IDR_CLR_0

Offset: 0x1124

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL2_SCRD_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

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Bit Reset Description

31:0 X IDR_CLR

INTR_CTLR_CHANNEL2_SLICE5_VIRQ_0

Offset: 0x1140

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL2_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X VIRQ

INTR_CTLR_CHANNEL2_SLICE5_VFIQ_0

Offset: 0x1144

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL2_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X VFIQ

INTR_CTLR_CHANNEL2_SLICE5_IER_0

Offset: 0x1148

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL2_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

IER

INTR_CTLR_CHANNEL2_SLICE5_IER_SET_0

Offset: 0x114c

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL2_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

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Bit Reset Description

31:0 X

IER_SET

INTR_CTLR_CHANNEL2_SLICE5_IER_CLR_0

Offset: 0x1150

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL2_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X IER_CLR

INTR_CTLR_CHANNEL2_SLICE5_IEP_CLASS_0

Offset: 0x1154

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL2_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 IEP_CLASS

INTR_CTLR_CHANNEL2_SLICE5_ISR_0

Offset: 0x1158

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL2_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 ISR

INTR_CTLR_CHANNEL2_SLICE5_IDR_0

Offset: 0x115c

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL2_SCRD_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

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Bit Reset Description

31:0 0x0 IDR

INTR_CTLR_CHANNEL2_SLICE5_IDR_SET_0

Offset: 0x1160

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL2_SCRD_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X

IDR_SET

INTR_CTLR_CHANNEL2_SLICE5_IDR_CLR_0

Offset: 0x1164

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL2_SCRD_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X IDR_CLR

INTR_CTLR_CHANNEL2_SLICE6_VIRQ_0

Offset: 0x1180

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL2_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X VIRQ

INTR_CTLR_CHANNEL2_SLICE6_VFIQ_0

Offset: 0x1184

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL2_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

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Bit Reset Description

31:0 X VFIQ

INTR_CTLR_CHANNEL2_SLICE6_IER_0

Offset: 0x1188

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL2_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 IER

INTR_CTLR_CHANNEL2_SLICE6_IER_SET_0

Offset: 0x118c

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL2_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X

IER_SET

INTR_CTLR_CHANNEL2_SLICE6_IER_CLR_0

Offset: 0x1190

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL2_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X IER_CLR

INTR_CTLR_CHANNEL2_SLICE6_IEP_CLASS_0

Offset: 0x1194

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL2_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

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Bit Reset Description

31:0 0x0 IEP_CLASS

INTR_CTLR_CHANNEL2_SLICE6_ISR_0

Offset: 0x1198

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL2_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 ISR

INTR_CTLR_CHANNEL2_SLICE6_IDR_0

Offset: 0x119c

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL2_SCRD_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 IDR

INTR_CTLR_CHANNEL2_SLICE6_IDR_SET_0

Offset: 0x11a0

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL2_SCRD_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X

IDR_SET

INTR_CTLR_CHANNEL2_SLICE6_IDR_CLR_0

Offset: 0x11a4

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL2_SCRD_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

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Bit Reset Description

31:0 X

IDR_CLR

INTR_CTLR_CHANNEL2_SLICE7_VIRQ_0

Offset: 0x11c0

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL2_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X VIRQ

INTR_CTLR_CHANNEL2_SLICE7_VFIQ_0

Offset: 0x11c4

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL2_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X VFIQ

INTR_CTLR_CHANNEL2_SLICE7_IER_0

Offset: 0x11c8

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL2_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 IER

INTR_CTLR_CHANNEL2_SLICE7_IER_SET_0

Offset: 0x11cc

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL2_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

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Bit Reset Description

31:0 X IER_SET

INTR_CTLR_CHANNEL2_SLICE7_IER_CLR_0

Offset: 0x11d0

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL2_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X

IER_CLR

INTR_CTLR_CHANNEL2_SLICE7_IEP_CLASS_0

Offset: 0x11d4

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL2_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 IEP_CLASS

INTR_CTLR_CHANNEL2_SLICE7_ISR_0

Offset: 0x11d8

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL2_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 ISR

INTR_CTLR_CHANNEL2_SLICE7_IDR_0

Offset: 0x11dc

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL2_SCRD_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

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Bit Reset Description

31:0 0x0 IDR

INTR_CTLR_CHANNEL2_SLICE7_IDR_SET_0

Offset: 0x11e0

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL2_SCRD_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X IDR_SET

INTR_CTLR_CHANNEL2_SLICE7_IDR_CLR_0

Offset: 0x11e4

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL2_SCRD_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X

IDR_CLR

INTR_CTLR_CHANNEL2_SLICE8_VIRQ_0

Offset: 0x1200

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL2_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X VIRQ

INTR_CTLR_CHANNEL2_SLICE8_VFIQ_0

Offset: 0x1204

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL2_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

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Bit Reset Description

31:0 X VFIQ

INTR_CTLR_CHANNEL2_SLICE8_IER_0

Offset: 0x1208

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL2_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 IER

INTR_CTLR_CHANNEL2_SLICE8_IER_SET_0

Offset: 0x120c

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL2_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X IER_SET

INTR_CTLR_CHANNEL2_SLICE8_IER_CLR_0

Offset: 0x1210

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL2_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X

IER_CLR

INTR_CTLR_CHANNEL2_SLICE8_IEP_CLASS_0

Offset: 0x1214

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL2_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

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Bit Reset Description

31:0 0x0

IEP_CLASS

INTR_CTLR_CHANNEL2_SLICE8_ISR_0

Offset: 0x1218

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL2_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 ISR

INTR_CTLR_CHANNEL2_SLICE8_IDR_0

Offset: 0x121c

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL2_SCRD_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 IDR

INTR_CTLR_CHANNEL2_SLICE8_IDR_SET_0

Offset: 0x1220

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL2_SCRD_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X IDR_SET

INTR_CTLR_CHANNEL2_SLICE8_IDR_CLR_0

Offset: 0x1224

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL2_SCRD_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

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Bit Reset Description

31:0 X IDR_CLR

INTR_CTLR_CHANNEL2_SLICE9_VIRQ_0

Offset: 0x1240

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL2_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X

VIRQ

INTR_CTLR_CHANNEL2_SLICE9_VFIQ_0

Offset: 0x1244

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL2_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X VFIQ

INTR_CTLR_CHANNEL2_SLICE9_IER_0

Offset: 0x1248

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL2_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 IER

INTR_CTLR_CHANNEL2_SLICE9_IER_SET_0

Offset: 0x124c

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL2_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

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Bit Reset Description

31:0 X IER_SET

INTR_CTLR_CHANNEL2_SLICE9_IER_CLR_0

Offset: 0x1250

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL2_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X IER_CLR

INTR_CTLR_CHANNEL2_SLICE9_IEP_CLASS_0

Offset: 0x1254

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL2_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

IEP_CLASS

INTR_CTLR_CHANNEL2_SLICE9_ISR_0

Offset: 0x1258

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL2_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 ISR

INTR_CTLR_CHANNEL2_SLICE9_IDR_0

Offset: 0x125c

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL2_SCRD_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

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Bit Reset Description

31:0 0x0 IDR

INTR_CTLR_CHANNEL2_SLICE9_IDR_SET_0

Offset: 0x1260

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL2_SCRD_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X IDR_SET

INTR_CTLR_CHANNEL2_SLICE9_IDR_CLR_0

Offset: 0x1264

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL2_SCRD_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X IDR_CLR

INTR_CTLR_CHANNEL2_SLICE10_VIRQ_0

Offset: 0x1280

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL2_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X

VIRQ

INTR_CTLR_CHANNEL2_SLICE10_VFIQ_0

Offset: 0x1284

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL2_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

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Bit Reset Description

31:0 X

VFIQ

INTR_CTLR_CHANNEL2_SLICE10_IER_0

Offset: 0x1288

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL2_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 IER

INTR_CTLR_CHANNEL2_SLICE10_IER_SET_0

Offset: 0x128c

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL2_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X IER_SET

INTR_CTLR_CHANNEL2_SLICE10_IER_CLR_0

Offset: 0x1290

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL2_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X IER_CLR

INTR_CTLR_CHANNEL2_SLICE10_IEP_CLASS_0

Offset: 0x1294

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL2_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

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Bit Reset Description

31:0 0x0 IEP_CLASS

INTR_CTLR_CHANNEL2_SLICE10_ISR_0

Offset: 0x1298

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL2_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

ISR

INTR_CTLR_CHANNEL2_SLICE10_IDR_0

Offset: 0x129c

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL2_SCRD_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 IDR

INTR_CTLR_CHANNEL2_SLICE10_IDR_SET_0

Offset: 0x12a0

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL2_SCRD_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X IDR_SET

INTR_CTLR_CHANNEL2_SLICE10_IDR_CLR_0

Offset: 0x12a4

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL2_SCRD_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

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Bit Reset Description

31:0 X IDR_CLR

INTR_CTLR_CHANNEL3_SLICE0_VIRQ_0

Offset: 0x1800

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL3_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X VIRQ

INTR_CTLR_CHANNEL3_SLICE0_VFIQ_0

Offset: 0x1804

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL3_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X

VFIQ

INTR_CTLR_CHANNEL3_SLICE0_IER_0

Offset: 0x1808

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL3_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 IER

INTR_CTLR_CHANNEL3_SLICE0_IER_SET_0

Offset: 0x180c

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL3_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

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Bit Reset Description

31:0 X IER_SET

INTR_CTLR_CHANNEL3_SLICE0_IER_CLR_0

Offset: 0x1810

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL3_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X IER_CLR

INTR_CTLR_CHANNEL3_SLICE0_IEP_CLASS_0

Offset: 0x1814

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL3_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 IEP_CLASS

INTR_CTLR_CHANNEL3_SLICE0_ISR_0

Offset: 0x1818

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL3_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

ISR

INTR_CTLR_CHANNEL3_SLICE0_IDR_0

Offset: 0x181c

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL3_SCRD_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

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Bit Reset Description

31:0 0x0

IDR

INTR_CTLR_CHANNEL3_SLICE0_IDR_SET_0

Offset: 0x1820

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL3_SCRD_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X IDR_SET

INTR_CTLR_CHANNEL3_SLICE0_IDR_CLR_0

Offset: 0x1824

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL3_SCRD_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X IDR_CLR

INTR_CTLR_CHANNEL3_SLICE1_VIRQ_0

Offset: 0x1840

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL3_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X VIRQ

INTR_CTLR_CHANNEL3_SLICE1_VFIQ_0

Offset: 0x1844

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL3_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

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Bit Reset Description

31:0 X VFIQ

INTR_CTLR_CHANNEL3_SLICE1_IER_0

Offset: 0x1848

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL3_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

IER

INTR_CTLR_CHANNEL3_SLICE1_IER_SET_0

Offset: 0x184c

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL3_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X IER_SET

INTR_CTLR_CHANNEL3_SLICE1_IER_CLR_0

Offset: 0x1850

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL3_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X IER_CLR

INTR_CTLR_CHANNEL3_SLICE1_IEP_CLASS_0

Offset: 0x1854

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL3_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

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Bit Reset Description

31:0 0x0 IEP_CLASS

INTR_CTLR_CHANNEL3_SLICE1_ISR_0

Offset: 0x1858

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL3_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 ISR

INTR_CTLR_CHANNEL3_SLICE1_IDR_0

Offset: 0x185c

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL3_SCRD_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

IDR

INTR_CTLR_CHANNEL3_SLICE1_IDR_SET_0

Offset: 0x1860

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL3_SCRD_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X IDR_SET

INTR_CTLR_CHANNEL3_SLICE1_IDR_CLR_0

Offset: 0x1864

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL3_SCRD_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

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Bit Reset Description

31:0 X IDR_CLR

INTR_CTLR_CHANNEL3_SLICE2_VIRQ_0

Offset: 0x1880

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL3_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X VIRQ

INTR_CTLR_CHANNEL3_SLICE2_VFIQ_0

Offset: 0x1884

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL3_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X VFIQ

INTR_CTLR_CHANNEL3_SLICE2_IER_0

Offset: 0x1888

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL3_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

IER

INTR_CTLR_CHANNEL3_SLICE2_IER_SET_0

Offset: 0x188c

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL3_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

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Bit Reset Description

31:0 X

IER_SET

INTR_CTLR_CHANNEL3_SLICE2_IER_CLR_0

Offset: 0x1890

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL3_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X IER_CLR

INTR_CTLR_CHANNEL3_SLICE2_IEP_CLASS_0

Offset: 0x1894

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL3_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 IEP_CLASS

INTR_CTLR_CHANNEL3_SLICE2_ISR_0

Offset: 0x1898

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL3_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 ISR

INTR_CTLR_CHANNEL3_SLICE2_IDR_0

Offset: 0x189c

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL3_SCRD_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

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Bit Reset Description

31:0 0x0 IDR

INTR_CTLR_CHANNEL3_SLICE2_IDR_SET_0

Offset: 0x18a0

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL3_SCRD_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X

IDR_SET

INTR_CTLR_CHANNEL3_SLICE2_IDR_CLR_0

Offset: 0x18a4

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL3_SCRD_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X IDR_CLR

INTR_CTLR_CHANNEL3_SLICE3_VIRQ_0

Offset: 0x18c0

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL3_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X VIRQ

INTR_CTLR_CHANNEL3_SLICE3_VFIQ_0

Offset: 0x18c4

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL3_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

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Bit Reset Description

31:0 X VFIQ

INTR_CTLR_CHANNEL3_SLICE3_IER_0

Offset: 0x18c8

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL3_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 IER

INTR_CTLR_CHANNEL3_SLICE3_IER_SET_0

Offset: 0x18cc

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL3_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X

IER_SET

INTR_CTLR_CHANNEL3_SLICE3_IER_CLR_0

Offset: 0x18d0

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL3_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X IER_CLR

INTR_CTLR_CHANNEL3_SLICE3_IEP_CLASS_0

Offset: 0x18d4

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL3_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

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Bit Reset Description

31:0 0x0 IEP_CLASS

INTR_CTLR_CHANNEL3_SLICE3_ISR_0

Offset: 0x18d8

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL3_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 ISR

INTR_CTLR_CHANNEL3_SLICE3_IDR_0

Offset: 0x18dc

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL3_SCRD_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 IDR

INTR_CTLR_CHANNEL3_SLICE3_IDR_SET_0

Offset: 0x18e0

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL3_SCRD_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X

IDR_SET

INTR_CTLR_CHANNEL3_SLICE3_IDR_CLR_0

Offset: 0x18e4

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL3_SCRD_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

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Bit Reset Description

31:0 X

IDR_CLR

INTR_CTLR_CHANNEL3_SLICE4_VIRQ_0

Offset: 0x1900

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL3_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X VIRQ

INTR_CTLR_CHANNEL3_SLICE4_VFIQ_0

Offset: 0x1904

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL3_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X VFIQ

INTR_CTLR_CHANNEL3_SLICE4_IER_0

Offset: 0x1908

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL3_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 IER

INTR_CTLR_CHANNEL3_SLICE4_IER_SET_0

Offset: 0x190c

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL3_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

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Bit Reset Description

31:0 X IER_SET

INTR_CTLR_CHANNEL3_SLICE4_IER_CLR_0

Offset: 0x1910

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL3_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X

IER_CLR

INTR_CTLR_CHANNEL3_SLICE4_IEP_CLASS_0

Offset: 0x1914

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL3_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 IEP_CLASS

INTR_CTLR_CHANNEL3_SLICE4_ISR_0

Offset: 0x1918

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL3_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 ISR

INTR_CTLR_CHANNEL3_SLICE4_IDR_0

Offset: 0x191c

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL3_SCRD_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

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Bit Reset Description

31:0 0x0 IDR

INTR_CTLR_CHANNEL3_SLICE4_IDR_SET_0

Offset: 0x1920

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL3_SCRD_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X IDR_SET

INTR_CTLR_CHANNEL3_SLICE4_IDR_CLR_0

Offset: 0x1924

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL3_SCRD_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X

IDR_CLR

INTR_CTLR_CHANNEL3_SLICE5_VIRQ_0

Offset: 0x1940

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL3_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X VIRQ

INTR_CTLR_CHANNEL3_SLICE5_VFIQ_0

Offset: 0x1944

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL3_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

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Bit Reset Description

31:0 X VFIQ

INTR_CTLR_CHANNEL3_SLICE5_IER_0

Offset: 0x1948

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL3_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 IER

INTR_CTLR_CHANNEL3_SLICE5_IER_SET_0

Offset: 0x194c

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL3_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X IER_SET

INTR_CTLR_CHANNEL3_SLICE5_IER_CLR_0

Offset: 0x1950

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL3_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X

IER_CLR

INTR_CTLR_CHANNEL3_SLICE5_IEP_CLASS_0

Offset: 0x1954

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL3_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

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Bit Reset Description

31:0 0x0

IEP_CLASS

INTR_CTLR_CHANNEL3_SLICE5_ISR_0

Offset: 0x1958

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL3_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 ISR

INTR_CTLR_CHANNEL3_SLICE5_IDR_0

Offset: 0x195c

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL3_SCRD_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 IDR

INTR_CTLR_CHANNEL3_SLICE5_IDR_SET_0

Offset: 0x1960

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL3_SCRD_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X IDR_SET

INTR_CTLR_CHANNEL3_SLICE5_IDR_CLR_0

Offset: 0x1964

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL3_SCRD_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

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Bit Reset Description

31:0 X IDR_CLR

INTR_CTLR_CHANNEL3_SLICE6_VIRQ_0

Offset: 0x1980

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL3_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X

VIRQ

INTR_CTLR_CHANNEL3_SLICE6_VFIQ_0

Offset: 0x1984

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL3_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X VFIQ

INTR_CTLR_CHANNEL3_SLICE6_IER_0

Offset: 0x1988

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL3_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 IER

INTR_CTLR_CHANNEL3_SLICE6_IER_SET_0

Offset: 0x198c

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL3_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

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Bit Reset Description

31:0 X IER_SET

INTR_CTLR_CHANNEL3_SLICE6_IER_CLR_0

Offset: 0x1990

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL3_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X IER_CLR

INTR_CTLR_CHANNEL3_SLICE6_IEP_CLASS_0

Offset: 0x1994

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL3_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

IEP_CLASS

INTR_CTLR_CHANNEL3_SLICE6_ISR_0

Offset: 0x1998

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL3_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 ISR

INTR_CTLR_CHANNEL3_SLICE6_IDR_0

Offset: 0x199c

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL3_SCRD_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

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Bit Reset Description

31:0 0x0 IDR

INTR_CTLR_CHANNEL3_SLICE6_IDR_SET_0

Offset: 0x19a0

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL3_SCRD_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X IDR_SET

INTR_CTLR_CHANNEL3_SLICE6_IDR_CLR_0

Offset: 0x19a4

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL3_SCRD_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X IDR_CLR

INTR_CTLR_CHANNEL3_SLICE7_VIRQ_0

Offset: 0x19c0

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL3_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X

VIRQ

INTR_CTLR_CHANNEL3_SLICE7_VFIQ_0

Offset: 0x19c4

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL3_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

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Bit Reset Description

31:0 X

VFIQ

INTR_CTLR_CHANNEL3_SLICE7_IER_0

Offset: 0x19c8

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL3_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 IER

INTR_CTLR_CHANNEL3_SLICE7_IER_SET_0

Offset: 0x19cc

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL3_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X IER_SET

INTR_CTLR_CHANNEL3_SLICE7_IER_CLR_0

Offset: 0x19d0

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL3_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X IER_CLR

INTR_CTLR_CHANNEL3_SLICE7_IEP_CLASS_0

Offset: 0x19d4

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL3_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

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Bit Reset Description

31:0 0x0 IEP_CLASS

INTR_CTLR_CHANNEL3_SLICE7_ISR_0

Offset: 0x19d8

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL3_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

ISR

INTR_CTLR_CHANNEL3_SLICE7_IDR_0

Offset: 0x19dc

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL3_SCRD_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 IDR

INTR_CTLR_CHANNEL3_SLICE7_IDR_SET_0

Offset: 0x19e0

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL3_SCRD_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X IDR_SET

INTR_CTLR_CHANNEL3_SLICE7_IDR_CLR_0

Offset: 0x19e4

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL3_SCRD_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

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Bit Reset Description

31:0 X IDR_CLR

INTR_CTLR_CHANNEL3_SLICE8_VIRQ_0

Offset: 0x1a00

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL3_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X VIRQ

INTR_CTLR_CHANNEL3_SLICE8_VFIQ_0

Offset: 0x1a04

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL3_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X

VFIQ

INTR_CTLR_CHANNEL3_SLICE8_IER_0

Offset: 0x1a08

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL3_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 IER

INTR_CTLR_CHANNEL3_SLICE8_IER_SET_0

Offset: 0x1a0c

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL3_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

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Bit Reset Description

31:0 X IER_SET

INTR_CTLR_CHANNEL3_SLICE8_IER_CLR_0

Offset: 0x1a10

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL3_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X IER_CLR

INTR_CTLR_CHANNEL3_SLICE8_IEP_CLASS_0

Offset: 0x1a14

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL3_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 IEP_CLASS

INTR_CTLR_CHANNEL3_SLICE8_ISR_0

Offset: 0x1a18

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL3_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

ISR

INTR_CTLR_CHANNEL3_SLICE8_IDR_0

Offset: 0x1a1c

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL3_SCRD_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

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Bit Reset Description

31:0 0x0

IDR

INTR_CTLR_CHANNEL3_SLICE8_IDR_SET_0

Offset: 0x1a20

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL3_SCRD_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X IDR_SET

INTR_CTLR_CHANNEL3_SLICE8_IDR_CLR_0

Offset: 0x1a24

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL3_SCRD_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X IDR_CLR

INTR_CTLR_CHANNEL3_SLICE9_VIRQ_0

Offset: 0x1a40

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL3_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X VIRQ

INTR_CTLR_CHANNEL3_SLICE9_VFIQ_0

Offset: 0x1a44

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL3_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

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Bit Reset Description

31:0 X VFIQ

INTR_CTLR_CHANNEL3_SLICE9_IER_0

Offset: 0x1a48

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL3_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

IER

INTR_CTLR_CHANNEL3_SLICE9_IER_SET_0

Offset: 0x1a4c

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL3_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X IER_SET

INTR_CTLR_CHANNEL3_SLICE9_IER_CLR_0

Offset: 0x1a50

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL3_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X IER_CLR

INTR_CTLR_CHANNEL3_SLICE9_IEP_CLASS_0

Offset: 0x1a54

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL3_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

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Bit Reset Description

31:0 0x0 IEP_CLASS

INTR_CTLR_CHANNEL3_SLICE9_ISR_0

Offset: 0x1a58

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL3_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 ISR

INTR_CTLR_CHANNEL3_SLICE9_IDR_0

Offset: 0x1a5c

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL3_SCRD_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

IDR

INTR_CTLR_CHANNEL3_SLICE9_IDR_SET_0

Offset: 0x1a60

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL3_SCRD_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X IDR_SET

INTR_CTLR_CHANNEL3_SLICE9_IDR_CLR_0

Offset: 0x1a64

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL3_SCRD_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

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Bit Reset Description

31:0 X IDR_CLR

INTR_CTLR_CHANNEL3_SLICE10_VIRQ_0

Offset: 0x1a80

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL3_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X VIRQ

INTR_CTLR_CHANNEL3_SLICE10_VFIQ_0

Offset: 0x1a84

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL3_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X VFIQ

INTR_CTLR_CHANNEL3_SLICE10_IER_0

Offset: 0x1a88

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL3_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

IER

INTR_CTLR_CHANNEL3_SLICE10_IER_SET_0

Offset: 0x1a8c

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL3_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

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Bit Reset Description

31:0 X

IER_SET

INTR_CTLR_CHANNEL3_SLICE10_IER_CLR_0

Offset: 0x1a90

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL3_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X IER_CLR

INTR_CTLR_CHANNEL3_SLICE10_IEP_CLASS_0

Offset: 0x1a94

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL3_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 IEP_CLASS

INTR_CTLR_CHANNEL3_SLICE10_ISR_0

Offset: 0x1a98

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL3_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 ISR

INTR_CTLR_CHANNEL3_SLICE10_IDR_0

Offset: 0x1a9c

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL3_SCRD_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

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Bit Reset Description

31:0 0x0 IDR

INTR_CTLR_CHANNEL3_SLICE10_IDR_SET_0

Offset: 0x1aa0

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL3_SCRD_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X

IDR_SET

INTR_CTLR_CHANNEL3_SLICE10_IDR_CLR_0

Offset: 0x1aa4

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL3_SCRD_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X IDR_CLR

INTR_CTLR_CHANNEL4_SLICE0_VIRQ_0

Offset: 0x2000

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL4_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X VIRQ

INTR_CTLR_CHANNEL4_SLICE0_VFIQ_0

Offset: 0x2004

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL4_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

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Bit Reset Description

31:0 X VFIQ

INTR_CTLR_CHANNEL4_SLICE0_IER_0

Offset: 0x2008

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL4_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 IER

INTR_CTLR_CHANNEL4_SLICE0_IER_SET_0

Offset: 0x200c

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL4_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X

IER_SET

INTR_CTLR_CHANNEL4_SLICE0_IER_CLR_0

Offset: 0x2010

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL4_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X IER_CLR

INTR_CTLR_CHANNEL4_SLICE0_IEP_CLASS_0

Offset: 0x2014

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL4_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

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Bit Reset Description

31:0 0x0 IEP_CLASS

INTR_CTLR_CHANNEL4_SLICE0_ISR_0

Offset: 0x2018

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL4_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 ISR

INTR_CTLR_CHANNEL4_SLICE0_IDR_0

Offset: 0x201c

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL4_SCRD_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 IDR

INTR_CTLR_CHANNEL4_SLICE0_IDR_SET_0

Offset: 0x2020

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL4_SCRD_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X

IDR_SET

INTR_CTLR_CHANNEL4_SLICE0_IDR_CLR_0

Offset: 0x2024

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL4_SCRD_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

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Bit Reset Description

31:0 X

IDR_CLR

INTR_CTLR_CHANNEL4_SLICE1_VIRQ_0

Offset: 0x2040

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL4_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X VIRQ

INTR_CTLR_CHANNEL4_SLICE1_VFIQ_0

Offset: 0x2044

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL4_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X VFIQ

INTR_CTLR_CHANNEL4_SLICE1_IER_0

Offset: 0x2048

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL4_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 IER

INTR_CTLR_CHANNEL4_SLICE1_IER_SET_0

Offset: 0x204c

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL4_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

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Bit Reset Description

31:0 X IER_SET

INTR_CTLR_CHANNEL4_SLICE1_IER_CLR_0

Offset: 0x2050

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL4_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X

IER_CLR

INTR_CTLR_CHANNEL4_SLICE1_IEP_CLASS_0

Offset: 0x2054

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL4_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 IEP_CLASS

INTR_CTLR_CHANNEL4_SLICE1_ISR_0

Offset: 0x2058

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL4_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 ISR

INTR_CTLR_CHANNEL4_SLICE1_IDR_0

Offset: 0x205c

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL4_SCRD_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

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Bit Reset Description

31:0 0x0 IDR

INTR_CTLR_CHANNEL4_SLICE1_IDR_SET_0

Offset: 0x2060

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL4_SCRD_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X IDR_SET

INTR_CTLR_CHANNEL4_SLICE1_IDR_CLR_0

Offset: 0x2064

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL4_SCRD_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X

IDR_CLR

INTR_CTLR_CHANNEL4_SLICE2_VIRQ_0

Offset: 0x2080

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL4_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X VIRQ

INTR_CTLR_CHANNEL4_SLICE2_VFIQ_0

Offset: 0x2084

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL4_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

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Bit Reset Description

31:0 X VFIQ

INTR_CTLR_CHANNEL4_SLICE2_IER_0

Offset: 0x2088

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL4_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 IER

INTR_CTLR_CHANNEL4_SLICE2_IER_SET_0

Offset: 0x208c

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL4_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X IER_SET

INTR_CTLR_CHANNEL4_SLICE2_IER_CLR_0

Offset: 0x2090

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL4_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X

IER_CLR

INTR_CTLR_CHANNEL4_SLICE2_IEP_CLASS_0

Offset: 0x2094

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL4_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

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Bit Reset Description

31:0 0x0

IEP_CLASS

INTR_CTLR_CHANNEL4_SLICE2_ISR_0

Offset: 0x2098

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL4_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 ISR

INTR_CTLR_CHANNEL4_SLICE2_IDR_0

Offset: 0x209c

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL4_SCRD_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 IDR

INTR_CTLR_CHANNEL4_SLICE2_IDR_SET_0

Offset: 0x20a0

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL4_SCRD_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X IDR_SET

INTR_CTLR_CHANNEL4_SLICE2_IDR_CLR_0

Offset: 0x20a4

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL4_SCRD_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

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Bit Reset Description

31:0 X IDR_CLR

INTR_CTLR_CHANNEL4_SLICE3_VIRQ_0

Offset: 0x20c0

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL4_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X

VIRQ

INTR_CTLR_CHANNEL4_SLICE3_VFIQ_0

Offset: 0x20c4

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL4_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X VFIQ

INTR_CTLR_CHANNEL4_SLICE3_IER_0

Offset: 0x20c8

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL4_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 IER

INTR_CTLR_CHANNEL4_SLICE3_IER_SET_0

Offset: 0x20cc

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL4_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

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Bit Reset Description

31:0 X IER_SET

INTR_CTLR_CHANNEL4_SLICE3_IER_CLR_0

Offset: 0x20d0

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL4_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X IER_CLR

INTR_CTLR_CHANNEL4_SLICE3_IEP_CLASS_0

Offset: 0x20d4

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL4_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

IEP_CLASS

INTR_CTLR_CHANNEL4_SLICE3_ISR_0

Offset: 0x20d8

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL4_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 ISR

INTR_CTLR_CHANNEL4_SLICE3_IDR_0

Offset: 0x20dc

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL4_SCRD_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

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Bit Reset Description

31:0 0x0 IDR

INTR_CTLR_CHANNEL4_SLICE3_IDR_SET_0

Offset: 0x20e0

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL4_SCRD_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X IDR_SET

INTR_CTLR_CHANNEL4_SLICE3_IDR_CLR_0

Offset: 0x20e4

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL4_SCRD_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X IDR_CLR

INTR_CTLR_CHANNEL4_SLICE4_VIRQ_0

Offset: 0x2100

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL4_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X

VIRQ

INTR_CTLR_CHANNEL4_SLICE4_VFIQ_0

Offset: 0x2104

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL4_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

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Bit Reset Description

31:0 X

VFIQ

INTR_CTLR_CHANNEL4_SLICE4_IER_0

Offset: 0x2108

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL4_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 IER

INTR_CTLR_CHANNEL4_SLICE4_IER_SET_0

Offset: 0x210c

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL4_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X IER_SET

INTR_CTLR_CHANNEL4_SLICE4_IER_CLR_0

Offset: 0x2110

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL4_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X IER_CLR

INTR_CTLR_CHANNEL4_SLICE4_IEP_CLASS_0

Offset: 0x2114

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL4_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

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Bit Reset Description

31:0 0x0 IEP_CLASS

INTR_CTLR_CHANNEL4_SLICE4_ISR_0

Offset: 0x2118

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL4_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

ISR

INTR_CTLR_CHANNEL4_SLICE4_IDR_0

Offset: 0x211c

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL4_SCRD_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 IDR

INTR_CTLR_CHANNEL4_SLICE4_IDR_SET_0

Offset: 0x2120

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL4_SCRD_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X IDR_SET

INTR_CTLR_CHANNEL4_SLICE4_IDR_CLR_0

Offset: 0x2124

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL4_SCRD_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

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Bit Reset Description

31:0 X IDR_CLR

INTR_CTLR_CHANNEL4_SLICE5_VIRQ_0

Offset: 0x2140

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL4_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X VIRQ

INTR_CTLR_CHANNEL4_SLICE5_VFIQ_0

Offset: 0x2144

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL4_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X

VFIQ

INTR_CTLR_CHANNEL4_SLICE5_IER_0

Offset: 0x2148

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL4_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 IER

INTR_CTLR_CHANNEL4_SLICE5_IER_SET_0

Offset: 0x214c

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL4_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

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Bit Reset Description

31:0 X IER_SET

INTR_CTLR_CHANNEL4_SLICE5_IER_CLR_0

Offset: 0x2150

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL4_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X IER_CLR

INTR_CTLR_CHANNEL4_SLICE5_IEP_CLASS_0

Offset: 0x2154

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL4_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 IEP_CLASS

INTR_CTLR_CHANNEL4_SLICE5_ISR_0

Offset: 0x2158

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL4_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

ISR

INTR_CTLR_CHANNEL4_SLICE5_IDR_0

Offset: 0x215c

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL4_SCRD_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

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Bit Reset Description

31:0 0x0

IDR

INTR_CTLR_CHANNEL4_SLICE5_IDR_SET_0

Offset: 0x2160

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL4_SCRD_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X IDR_SET

INTR_CTLR_CHANNEL4_SLICE5_IDR_CLR_0

Offset: 0x2164

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL4_SCRD_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X IDR_CLR

INTR_CTLR_CHANNEL4_SLICE6_VIRQ_0

Offset: 0x2180

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL4_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X VIRQ

INTR_CTLR_CHANNEL4_SLICE6_VFIQ_0

Offset: 0x2184

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL4_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

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Bit Reset Description

31:0 X VFIQ

INTR_CTLR_CHANNEL4_SLICE6_IER_0

Offset: 0x2188

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL4_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

IER

INTR_CTLR_CHANNEL4_SLICE6_IER_SET_0

Offset: 0x218c

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL4_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X IER_SET

INTR_CTLR_CHANNEL4_SLICE6_IER_CLR_0

Offset: 0x2190

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL4_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X IER_CLR

INTR_CTLR_CHANNEL4_SLICE6_IEP_CLASS_0

Offset: 0x2194

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL4_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

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Bit Reset Description

31:0 0x0 IEP_CLASS

INTR_CTLR_CHANNEL4_SLICE6_ISR_0

Offset: 0x2198

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL4_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 ISR

INTR_CTLR_CHANNEL4_SLICE6_IDR_0

Offset: 0x219c

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL4_SCRD_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

IDR

INTR_CTLR_CHANNEL4_SLICE6_IDR_SET_0

Offset: 0x21a0

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL4_SCRD_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X IDR_SET

INTR_CTLR_CHANNEL4_SLICE6_IDR_CLR_0

Offset: 0x21a4

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL4_SCRD_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

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Bit Reset Description

31:0 X IDR_CLR

INTR_CTLR_CHANNEL4_SLICE7_VIRQ_0

Offset: 0x21c0

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL4_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X VIRQ

INTR_CTLR_CHANNEL4_SLICE7_VFIQ_0

Offset: 0x21c4

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL4_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X VFIQ

INTR_CTLR_CHANNEL4_SLICE7_IER_0

Offset: 0x21c8

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL4_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

IER

INTR_CTLR_CHANNEL4_SLICE7_IER_SET_0

Offset: 0x21cc

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL4_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

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Bit Reset Description

31:0 X

IER_SET

INTR_CTLR_CHANNEL4_SLICE7_IER_CLR_0

Offset: 0x21d0

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL4_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X IER_CLR

INTR_CTLR_CHANNEL4_SLICE7_IEP_CLASS_0

Offset: 0x21d4

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL4_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 IEP_CLASS

INTR_CTLR_CHANNEL4_SLICE7_ISR_0

Offset: 0x21d8

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL4_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 ISR

INTR_CTLR_CHANNEL4_SLICE7_IDR_0

Offset: 0x21dc

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL4_SCRD_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

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Bit Reset Description

31:0 0x0 IDR

INTR_CTLR_CHANNEL4_SLICE7_IDR_SET_0

Offset: 0x21e0

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL4_SCRD_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X

IDR_SET

INTR_CTLR_CHANNEL4_SLICE7_IDR_CLR_0

Offset: 0x21e4

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL4_SCRD_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X IDR_CLR

INTR_CTLR_CHANNEL4_SLICE8_VIRQ_0

Offset: 0x2200

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL4_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X VIRQ

INTR_CTLR_CHANNEL4_SLICE8_VFIQ_0

Offset: 0x2204

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL4_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

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Bit Reset Description

31:0 X VFIQ

INTR_CTLR_CHANNEL4_SLICE8_IER_0

Offset: 0x2208

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL4_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 IER

INTR_CTLR_CHANNEL4_SLICE8_IER_SET_0

Offset: 0x220c

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL4_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X

IER_SET

INTR_CTLR_CHANNEL4_SLICE8_IER_CLR_0

Offset: 0x2210

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL4_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X IER_CLR

INTR_CTLR_CHANNEL4_SLICE8_IEP_CLASS_0

Offset: 0x2214

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL4_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

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Bit Reset Description

31:0 0x0 IEP_CLASS

INTR_CTLR_CHANNEL4_SLICE8_ISR_0

Offset: 0x2218

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL4_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 ISR

INTR_CTLR_CHANNEL4_SLICE8_IDR_0

Offset: 0x221c

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL4_SCRD_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 IDR

INTR_CTLR_CHANNEL4_SLICE8_IDR_SET_0

Offset: 0x2220

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL4_SCRD_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X

IDR_SET

INTR_CTLR_CHANNEL4_SLICE8_IDR_CLR_0

Offset: 0x2224

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL4_SCRD_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

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Bit Reset Description

31:0 X

IDR_CLR

INTR_CTLR_CHANNEL4_SLICE9_VIRQ_0

Offset: 0x2240

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL4_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X VIRQ

INTR_CTLR_CHANNEL4_SLICE9_VFIQ_0

Offset: 0x2244

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL4_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X VFIQ

INTR_CTLR_CHANNEL4_SLICE9_IER_0

Offset: 0x2248

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL4_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 IER

INTR_CTLR_CHANNEL4_SLICE9_IER_SET_0

Offset: 0x224c

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL4_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

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Bit Reset Description

31:0 X IER_SET

INTR_CTLR_CHANNEL4_SLICE9_IER_CLR_0

Offset: 0x2250

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL4_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X

IER_CLR

INTR_CTLR_CHANNEL4_SLICE9_IEP_CLASS_0

Offset: 0x2254

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL4_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 IEP_CLASS

INTR_CTLR_CHANNEL4_SLICE9_ISR_0

Offset: 0x2258

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL4_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 ISR

INTR_CTLR_CHANNEL4_SLICE9_IDR_0

Offset: 0x225c

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL4_SCRD_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

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Bit Reset Description

31:0 0x0 IDR

INTR_CTLR_CHANNEL4_SLICE9_IDR_SET_0

Offset: 0x2260

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL4_SCRD_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X IDR_SET

INTR_CTLR_CHANNEL4_SLICE9_IDR_CLR_0

Offset: 0x2264

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL4_SCRD_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X

IDR_CLR

INTR_CTLR_CHANNEL4_SLICE10_VIRQ_0

Offset: 0x2280

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL4_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X VIRQ

INTR_CTLR_CHANNEL4_SLICE10_VFIQ_0

Offset: 0x2284

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL4_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

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Bit Reset Description

31:0 X VFIQ

INTR_CTLR_CHANNEL4_SLICE10_IER_0

Offset: 0x2288

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL4_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 IER

INTR_CTLR_CHANNEL4_SLICE10_IER_SET_0

Offset: 0x228c

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL4_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X IER_SET

INTR_CTLR_CHANNEL4_SLICE10_IER_CLR_0

Offset: 0x2290

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL4_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X

IER_CLR

INTR_CTLR_CHANNEL4_SLICE10_IEP_CLASS_0

Offset: 0x2294

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL4_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

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Bit Reset Description

31:0 0x0

IEP_CLASS

INTR_CTLR_CHANNEL4_SLICE10_ISR_0

Offset: 0x2298

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL4_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 ISR

INTR_CTLR_CHANNEL4_SLICE10_IDR_0

Offset: 0x229c

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL4_SCRD_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 IDR

INTR_CTLR_CHANNEL4_SLICE10_IDR_SET_0

Offset: 0x22a0

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL4_SCRD_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X IDR_SET

INTR_CTLR_CHANNEL4_SLICE10_IDR_CLR_0

Offset: 0x22a4

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL4_SCRD_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

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Bit Reset Description

31:0 X IDR_CLR

INTR_CTLR_CHANNEL5_SLICE0_VIRQ_0

Offset: 0x2800

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL5_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X

VIRQ

INTR_CTLR_CHANNEL5_SLICE0_VFIQ_0

Offset: 0x2804

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL5_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X VFIQ

INTR_CTLR_CHANNEL5_SLICE0_IER_0

Offset: 0x2808

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL5_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 IER

INTR_CTLR_CHANNEL5_SLICE0_IER_SET_0

Offset: 0x280c

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL5_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

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Bit Reset Description

31:0 X IER_SET

INTR_CTLR_CHANNEL5_SLICE0_IER_CLR_0

Offset: 0x2810

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL5_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X IER_CLR

INTR_CTLR_CHANNEL5_SLICE0_IEP_CLASS_0

Offset: 0x2814

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL5_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

IEP_CLASS

INTR_CTLR_CHANNEL5_SLICE0_ISR_0

Offset: 0x2818

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL5_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 ISR

INTR_CTLR_CHANNEL5_SLICE0_IDR_0

Offset: 0x281c

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL5_SCRD_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

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Bit Reset Description

31:0 0x0 IDR

INTR_CTLR_CHANNEL5_SLICE0_IDR_SET_0

Offset: 0x2820

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL5_SCRD_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X IDR_SET

INTR_CTLR_CHANNEL5_SLICE0_IDR_CLR_0

Offset: 0x2824

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL5_SCRD_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X IDR_CLR

INTR_CTLR_CHANNEL5_SLICE1_VIRQ_0

Offset: 0x2840

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL5_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X

VIRQ

INTR_CTLR_CHANNEL5_SLICE1_VFIQ_0

Offset: 0x2844

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL5_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

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Bit Reset Description

31:0 X

VFIQ

INTR_CTLR_CHANNEL5_SLICE1_IER_0

Offset: 0x2848

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL5_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 IER

INTR_CTLR_CHANNEL5_SLICE1_IER_SET_0

Offset: 0x284c

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL5_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X IER_SET

INTR_CTLR_CHANNEL5_SLICE1_IER_CLR_0

Offset: 0x2850

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL5_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X IER_CLR

INTR_CTLR_CHANNEL5_SLICE1_IEP_CLASS_0

Offset: 0x2854

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL5_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

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Bit Reset Description

31:0 0x0 IEP_CLASS

INTR_CTLR_CHANNEL5_SLICE1_ISR_0

Offset: 0x2858

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL5_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

ISR

INTR_CTLR_CHANNEL5_SLICE1_IDR_0

Offset: 0x285c

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL5_SCRD_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 IDR

INTR_CTLR_CHANNEL5_SLICE1_IDR_SET_0

Offset: 0x2860

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL5_SCRD_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X IDR_SET

INTR_CTLR_CHANNEL5_SLICE1_IDR_CLR_0

Offset: 0x2864

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL5_SCRD_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

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Bit Reset Description

31:0 X IDR_CLR

INTR_CTLR_CHANNEL5_SLICE2_VIRQ_0

Offset: 0x2880

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL5_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X VIRQ

INTR_CTLR_CHANNEL5_SLICE2_VFIQ_0

Offset: 0x2884

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL5_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X

VFIQ

INTR_CTLR_CHANNEL5_SLICE2_IER_0

Offset: 0x2888

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL5_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 IER

INTR_CTLR_CHANNEL5_SLICE2_IER_SET_0

Offset: 0x288c

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL5_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

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Bit Reset Description

31:0 X IER_SET

INTR_CTLR_CHANNEL5_SLICE2_IER_CLR_0

Offset: 0x2890

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL5_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X IER_CLR

INTR_CTLR_CHANNEL5_SLICE2_IEP_CLASS_0

Offset: 0x2894

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL5_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 IEP_CLASS

INTR_CTLR_CHANNEL5_SLICE2_ISR_0

Offset: 0x2898

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL5_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

ISR

INTR_CTLR_CHANNEL5_SLICE2_IDR_0

Offset: 0x289c

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL5_SCRD_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

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Bit Reset Description

31:0 0x0

IDR

INTR_CTLR_CHANNEL5_SLICE2_IDR_SET_0

Offset: 0x28a0

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL5_SCRD_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X IDR_SET

INTR_CTLR_CHANNEL5_SLICE2_IDR_CLR_0

Offset: 0x28a4

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL5_SCRD_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X IDR_CLR

INTR_CTLR_CHANNEL5_SLICE3_VIRQ_0

Offset: 0x28c0

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL5_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X VIRQ

INTR_CTLR_CHANNEL5_SLICE3_VFIQ_0

Offset: 0x28c4

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL5_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

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Bit Reset Description

31:0 X VFIQ

INTR_CTLR_CHANNEL5_SLICE3_IER_0

Offset: 0x28c8

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL5_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

IER

INTR_CTLR_CHANNEL5_SLICE3_IER_SET_0

Offset: 0x28cc

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL5_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X IER_SET

INTR_CTLR_CHANNEL5_SLICE3_IER_CLR_0

Offset: 0x28d0

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL5_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X IER_CLR

INTR_CTLR_CHANNEL5_SLICE3_IEP_CLASS_0

Offset: 0x28d4

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL5_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

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Bit Reset Description

31:0 0x0 IEP_CLASS

INTR_CTLR_CHANNEL5_SLICE3_ISR_0

Offset: 0x28d8

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL5_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 ISR

INTR_CTLR_CHANNEL5_SLICE3_IDR_0

Offset: 0x28dc

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL5_SCRD_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

IDR

INTR_CTLR_CHANNEL5_SLICE3_IDR_SET_0

Offset: 0x28e0

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL5_SCRD_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X IDR_SET

INTR_CTLR_CHANNEL5_SLICE3_IDR_CLR_0

Offset: 0x28e4

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL5_SCRD_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

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Bit Reset Description

31:0 X IDR_CLR

INTR_CTLR_CHANNEL5_SLICE4_VIRQ_0

Offset: 0x2900

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL5_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X VIRQ

INTR_CTLR_CHANNEL5_SLICE4_VFIQ_0

Offset: 0x2904

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL5_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X VFIQ

INTR_CTLR_CHANNEL5_SLICE4_IER_0

Offset: 0x2908

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL5_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

IER

INTR_CTLR_CHANNEL5_SLICE4_IER_SET_0

Offset: 0x290c

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL5_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

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Bit Reset Description

31:0 X

IER_SET

INTR_CTLR_CHANNEL5_SLICE4_IER_CLR_0

Offset: 0x2910

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL5_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X IER_CLR

INTR_CTLR_CHANNEL5_SLICE4_IEP_CLASS_0

Offset: 0x2914

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL5_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 IEP_CLASS

INTR_CTLR_CHANNEL5_SLICE4_ISR_0

Offset: 0x2918

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL5_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 ISR

INTR_CTLR_CHANNEL5_SLICE4_IDR_0

Offset: 0x291c

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL5_SCRD_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

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Bit Reset Description

31:0 0x0 IDR

INTR_CTLR_CHANNEL5_SLICE4_IDR_SET_0

Offset: 0x2920

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL5_SCRD_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X

IDR_SET

INTR_CTLR_CHANNEL5_SLICE4_IDR_CLR_0

Offset: 0x2924

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL5_SCRD_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X IDR_CLR

INTR_CTLR_CHANNEL5_SLICE5_VIRQ_0

Offset: 0x2940

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL5_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X VIRQ

INTR_CTLR_CHANNEL5_SLICE5_VFIQ_0

Offset: 0x2944

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL5_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

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Bit Reset Description

31:0 X VFIQ

INTR_CTLR_CHANNEL5_SLICE5_IER_0

Offset: 0x2948

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL5_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 IER

INTR_CTLR_CHANNEL5_SLICE5_IER_SET_0

Offset: 0x294c

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL5_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X

IER_SET

INTR_CTLR_CHANNEL5_SLICE5_IER_CLR_0

Offset: 0x2950

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL5_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X IER_CLR

INTR_CTLR_CHANNEL5_SLICE5_IEP_CLASS_0

Offset: 0x2954

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL5_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

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Bit Reset Description

31:0 0x0 IEP_CLASS

INTR_CTLR_CHANNEL5_SLICE5_ISR_0

Offset: 0x2958

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL5_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 ISR

INTR_CTLR_CHANNEL5_SLICE5_IDR_0

Offset: 0x295c

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL5_SCRD_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 IDR

INTR_CTLR_CHANNEL5_SLICE5_IDR_SET_0

Offset: 0x2960

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL5_SCRD_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X

IDR_SET

INTR_CTLR_CHANNEL5_SLICE5_IDR_CLR_0

Offset: 0x2964

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL5_SCRD_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

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Bit Reset Description

31:0 X

IDR_CLR

INTR_CTLR_CHANNEL5_SLICE6_VIRQ_0

Offset: 0x2980

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL5_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X VIRQ

INTR_CTLR_CHANNEL5_SLICE6_VFIQ_0

Offset: 0x2984

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL5_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X VFIQ

INTR_CTLR_CHANNEL5_SLICE6_IER_0

Offset: 0x2988

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL5_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 IER

INTR_CTLR_CHANNEL5_SLICE6_IER_SET_0

Offset: 0x298c

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL5_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

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Bit Reset Description

31:0 X IER_SET

INTR_CTLR_CHANNEL5_SLICE6_IER_CLR_0

Offset: 0x2990

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL5_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X

IER_CLR

INTR_CTLR_CHANNEL5_SLICE6_IEP_CLASS_0

Offset: 0x2994

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL5_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 IEP_CLASS

INTR_CTLR_CHANNEL5_SLICE6_ISR_0

Offset: 0x2998

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL5_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 ISR

INTR_CTLR_CHANNEL5_SLICE6_IDR_0

Offset: 0x299c

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL5_SCRD_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

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Bit Reset Description

31:0 0x0 IDR

INTR_CTLR_CHANNEL5_SLICE6_IDR_SET_0

Offset: 0x29a0

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL5_SCRD_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X IDR_SET

INTR_CTLR_CHANNEL5_SLICE6_IDR_CLR_0

Offset: 0x29a4

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL5_SCRD_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X

IDR_CLR

INTR_CTLR_CHANNEL5_SLICE7_VIRQ_0

Offset: 0x29c0

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL5_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X VIRQ

INTR_CTLR_CHANNEL5_SLICE7_VFIQ_0

Offset: 0x29c4

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL5_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

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Bit Reset Description

31:0 X VFIQ

INTR_CTLR_CHANNEL5_SLICE7_IER_0

Offset: 0x29c8

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL5_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 IER

INTR_CTLR_CHANNEL5_SLICE7_IER_SET_0

Offset: 0x29cc

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL5_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X IER_SET

INTR_CTLR_CHANNEL5_SLICE7_IER_CLR_0

Offset: 0x29d0

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL5_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X

IER_CLR

INTR_CTLR_CHANNEL5_SLICE7_IEP_CLASS_0

Offset: 0x29d4

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL5_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

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Bit Reset Description

31:0 0x0

IEP_CLASS

INTR_CTLR_CHANNEL5_SLICE7_ISR_0

Offset: 0x29d8

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL5_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 ISR

INTR_CTLR_CHANNEL5_SLICE7_IDR_0

Offset: 0x29dc

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL5_SCRD_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 IDR

INTR_CTLR_CHANNEL5_SLICE7_IDR_SET_0

Offset: 0x29e0

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL5_SCRD_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X IDR_SET

INTR_CTLR_CHANNEL5_SLICE7_IDR_CLR_0

Offset: 0x29e4

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL5_SCRD_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

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Bit Reset Description

31:0 X IDR_CLR

INTR_CTLR_CHANNEL5_SLICE8_VIRQ_0

Offset: 0x2a00

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL5_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X

VIRQ

INTR_CTLR_CHANNEL5_SLICE8_VFIQ_0

Offset: 0x2a04

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL5_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X VFIQ

INTR_CTLR_CHANNEL5_SLICE8_IER_0

Offset: 0x2a08

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL5_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 IER

INTR_CTLR_CHANNEL5_SLICE8_IER_SET_0

Offset: 0x2a0c

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL5_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

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Bit Reset Description

31:0 X IER_SET

INTR_CTLR_CHANNEL5_SLICE8_IER_CLR_0

Offset: 0x2a10

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL5_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X IER_CLR

INTR_CTLR_CHANNEL5_SLICE8_IEP_CLASS_0

Offset: 0x2a14

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL5_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

IEP_CLASS

INTR_CTLR_CHANNEL5_SLICE8_ISR_0

Offset: 0x2a18

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL5_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 ISR

INTR_CTLR_CHANNEL5_SLICE8_IDR_0

Offset: 0x2a1c

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL5_SCRD_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

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Bit Reset Description

31:0 0x0 IDR

INTR_CTLR_CHANNEL5_SLICE8_IDR_SET_0

Offset: 0x2a20

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL5_SCRD_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X IDR_SET

INTR_CTLR_CHANNEL5_SLICE8_IDR_CLR_0

Offset: 0x2a24

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL5_SCRD_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X IDR_CLR

INTR_CTLR_CHANNEL5_SLICE9_VIRQ_0

Offset: 0x2a40

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL5_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X

VIRQ

INTR_CTLR_CHANNEL5_SLICE9_VFIQ_0

Offset: 0x2a44

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL5_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

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Bit Reset Description

31:0 X

VFIQ

INTR_CTLR_CHANNEL5_SLICE9_IER_0

Offset: 0x2a48

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL5_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 IER

INTR_CTLR_CHANNEL5_SLICE9_IER_SET_0

Offset: 0x2a4c

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL5_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X IER_SET

INTR_CTLR_CHANNEL5_SLICE9_IER_CLR_0

Offset: 0x2a50

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL5_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X IER_CLR

INTR_CTLR_CHANNEL5_SLICE9_IEP_CLASS_0

Offset: 0x2a54

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL5_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

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Bit Reset Description

31:0 0x0 IEP_CLASS

INTR_CTLR_CHANNEL5_SLICE9_ISR_0

Offset: 0x2a58

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL5_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

ISR

INTR_CTLR_CHANNEL5_SLICE9_IDR_0

Offset: 0x2a5c

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL5_SCRD_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 IDR

INTR_CTLR_CHANNEL5_SLICE9_IDR_SET_0

Offset: 0x2a60

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL5_SCRD_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X IDR_SET

INTR_CTLR_CHANNEL5_SLICE9_IDR_CLR_0

Offset: 0x2a64

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL5_SCRD_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

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Bit Reset Description

31:0 X IDR_CLR

INTR_CTLR_CHANNEL5_SLICE10_VIRQ_0

Offset: 0x2a80

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL5_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X VIRQ

INTR_CTLR_CHANNEL5_SLICE10_VFIQ_0

Offset: 0x2a84

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL5_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X

VFIQ

INTR_CTLR_CHANNEL5_SLICE10_IER_0

Offset: 0x2a88

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL5_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 IER

INTR_CTLR_CHANNEL5_SLICE10_IER_SET_0

Offset: 0x2a8c

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL5_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

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Bit Reset Description

31:0 X IER_SET

INTR_CTLR_CHANNEL5_SLICE10_IER_CLR_0

Offset: 0x2a90

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL5_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X IER_CLR

INTR_CTLR_CHANNEL5_SLICE10_IEP_CLASS_0

Offset: 0x2a94

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL5_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 IEP_CLASS

INTR_CTLR_CHANNEL5_SLICE10_ISR_0

Offset: 0x2a98

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL5_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

ISR

INTR_CTLR_CHANNEL5_SLICE10_IDR_0

Offset: 0x2a9c

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL5_SCRD_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

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Bit Reset Description

31:0 0x0

IDR

INTR_CTLR_CHANNEL5_SLICE10_IDR_SET_0

Offset: 0x2aa0

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL5_SCRD_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X IDR_SET

INTR_CTLR_CHANNEL5_SLICE10_IDR_CLR_0

Offset: 0x2aa4

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL5_SCRD_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X IDR_CLR

INTR_CTLR_CHANNEL6_SLICE0_VIRQ_0

Offset: 0x3000

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL6_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X VIRQ

INTR_CTLR_CHANNEL6_SLICE0_VFIQ_0

Offset: 0x3004

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL6_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

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Bit Reset Description

31:0 X VFIQ

INTR_CTLR_CHANNEL6_SLICE0_IER_0

Offset: 0x3008

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL6_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

IER

INTR_CTLR_CHANNEL6_SLICE0_IER_SET_0

Offset: 0x300c

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL6_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X IER_SET

INTR_CTLR_CHANNEL6_SLICE0_IER_CLR_0

Offset: 0x3010

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL6_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X IER_CLR

INTR_CTLR_CHANNEL6_SLICE0_IEP_CLASS_0

Offset: 0x3014

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL6_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

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Bit Reset Description

31:0 0x0 IEP_CLASS

INTR_CTLR_CHANNEL6_SLICE0_ISR_0

Offset: 0x3018

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL6_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 ISR

INTR_CTLR_CHANNEL6_SLICE0_IDR_0

Offset: 0x301c

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL6_SCRD_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

IDR

INTR_CTLR_CHANNEL6_SLICE0_IDR_SET_0

Offset: 0x3020

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL6_SCRD_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X IDR_SET

INTR_CTLR_CHANNEL6_SLICE0_IDR_CLR_0

Offset: 0x3024

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL6_SCRD_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

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Bit Reset Description

31:0 X IDR_CLR

INTR_CTLR_CHANNEL6_SLICE1_VIRQ_0

Offset: 0x3040

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL6_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X VIRQ

INTR_CTLR_CHANNEL6_SLICE1_VFIQ_0

Offset: 0x3044

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL6_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X VFIQ

INTR_CTLR_CHANNEL6_SLICE1_IER_0

Offset: 0x3048

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL6_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

IER

INTR_CTLR_CHANNEL6_SLICE1_IER_SET_0

Offset: 0x304c

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL6_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

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Bit Reset Description

31:0 X

IER_SET

INTR_CTLR_CHANNEL6_SLICE1_IER_CLR_0

Offset: 0x3050

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL6_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X IER_CLR

INTR_CTLR_CHANNEL6_SLICE1_IEP_CLASS_0

Offset: 0x3054

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL6_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 IEP_CLASS

INTR_CTLR_CHANNEL6_SLICE1_ISR_0

Offset: 0x3058

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL6_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 ISR

INTR_CTLR_CHANNEL6_SLICE1_IDR_0

Offset: 0x305c

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL6_SCRD_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

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Bit Reset Description

31:0 0x0 IDR

INTR_CTLR_CHANNEL6_SLICE1_IDR_SET_0

Offset: 0x3060

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL6_SCRD_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X

IDR_SET

INTR_CTLR_CHANNEL6_SLICE1_IDR_CLR_0

Offset: 0x3064

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL6_SCRD_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X IDR_CLR

INTR_CTLR_CHANNEL6_SLICE2_VIRQ_0

Offset: 0x3080

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL6_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X VIRQ

INTR_CTLR_CHANNEL6_SLICE2_VFIQ_0

Offset: 0x3084

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL6_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

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Bit Reset Description

31:0 X VFIQ

INTR_CTLR_CHANNEL6_SLICE2_IER_0

Offset: 0x3088

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL6_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 IER

INTR_CTLR_CHANNEL6_SLICE2_IER_SET_0

Offset: 0x308c

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL6_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X

IER_SET

INTR_CTLR_CHANNEL6_SLICE2_IER_CLR_0

Offset: 0x3090

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL6_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X IER_CLR

INTR_CTLR_CHANNEL6_SLICE2_IEP_CLASS_0

Offset: 0x3094

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL6_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

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Bit Reset Description

31:0 0x0 IEP_CLASS

INTR_CTLR_CHANNEL6_SLICE2_ISR_0

Offset: 0x3098

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL6_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 ISR

INTR_CTLR_CHANNEL6_SLICE2_IDR_0

Offset: 0x309c

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL6_SCRD_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 IDR

INTR_CTLR_CHANNEL6_SLICE2_IDR_SET_0

Offset: 0x30a0

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL6_SCRD_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X

IDR_SET

INTR_CTLR_CHANNEL6_SLICE2_IDR_CLR_0

Offset: 0x30a4

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL6_SCRD_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

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Bit Reset Description

31:0 X

IDR_CLR

INTR_CTLR_CHANNEL6_SLICE3_VIRQ_0

Offset: 0x30c0

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL6_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X VIRQ

INTR_CTLR_CHANNEL6_SLICE3_VFIQ_0

Offset: 0x30c4

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL6_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X VFIQ

INTR_CTLR_CHANNEL6_SLICE3_IER_0

Offset: 0x30c8

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL6_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 IER

INTR_CTLR_CHANNEL6_SLICE3_IER_SET_0

Offset: 0x30cc

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL6_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

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Bit Reset Description

31:0 X IER_SET

INTR_CTLR_CHANNEL6_SLICE3_IER_CLR_0

Offset: 0x30d0

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL6_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X

IER_CLR

INTR_CTLR_CHANNEL6_SLICE3_IEP_CLASS_0

Offset: 0x30d4

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL6_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 IEP_CLASS

INTR_CTLR_CHANNEL6_SLICE3_ISR_0

Offset: 0x30d8

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL6_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 ISR

INTR_CTLR_CHANNEL6_SLICE3_IDR_0

Offset: 0x30dc

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL6_SCRD_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

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Bit Reset Description

31:0 0x0 IDR

INTR_CTLR_CHANNEL6_SLICE3_IDR_SET_0

Offset: 0x30e0

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL6_SCRD_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X IDR_SET

INTR_CTLR_CHANNEL6_SLICE3_IDR_CLR_0

Offset: 0x30e4

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL6_SCRD_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X

IDR_CLR

INTR_CTLR_CHANNEL6_SLICE4_VIRQ_0

Offset: 0x3100

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL6_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X VIRQ

INTR_CTLR_CHANNEL6_SLICE4_VFIQ_0

Offset: 0x3104

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL6_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

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Bit Reset Description

31:0 X VFIQ

INTR_CTLR_CHANNEL6_SLICE4_IER_0

Offset: 0x3108

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL6_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 IER

INTR_CTLR_CHANNEL6_SLICE4_IER_SET_0

Offset: 0x310c

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL6_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X IER_SET

INTR_CTLR_CHANNEL6_SLICE4_IER_CLR_0

Offset: 0x3110

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL6_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X

IER_CLR

INTR_CTLR_CHANNEL6_SLICE4_IEP_CLASS_0

Offset: 0x3114

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL6_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

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Bit Reset Description

31:0 0x0

IEP_CLASS

INTR_CTLR_CHANNEL6_SLICE4_ISR_0

Offset: 0x3118

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL6_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 ISR

INTR_CTLR_CHANNEL6_SLICE4_IDR_0

Offset: 0x311c

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL6_SCRD_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 IDR

INTR_CTLR_CHANNEL6_SLICE4_IDR_SET_0

Offset: 0x3120

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL6_SCRD_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X IDR_SET

INTR_CTLR_CHANNEL6_SLICE4_IDR_CLR_0

Offset: 0x3124

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL6_SCRD_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

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Bit Reset Description

31:0 X IDR_CLR

INTR_CTLR_CHANNEL6_SLICE5_VIRQ_0

Offset: 0x3140

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL6_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X

VIRQ

INTR_CTLR_CHANNEL6_SLICE5_VFIQ_0

Offset: 0x3144

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL6_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X VFIQ

INTR_CTLR_CHANNEL6_SLICE5_IER_0

Offset: 0x3148

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL6_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 IER

INTR_CTLR_CHANNEL6_SLICE5_IER_SET_0

Offset: 0x314c

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL6_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

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Bit Reset Description

31:0 X IER_SET

INTR_CTLR_CHANNEL6_SLICE5_IER_CLR_0

Offset: 0x3150

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL6_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X IER_CLR

INTR_CTLR_CHANNEL6_SLICE5_IEP_CLASS_0

Offset: 0x3154

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL6_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

IEP_CLASS

INTR_CTLR_CHANNEL6_SLICE5_ISR_0

Offset: 0x3158

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL6_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 ISR

INTR_CTLR_CHANNEL6_SLICE5_IDR_0

Offset: 0x315c

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL6_SCRD_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

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Bit Reset Description

31:0 0x0 IDR

INTR_CTLR_CHANNEL6_SLICE5_IDR_SET_0

Offset: 0x3160

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL6_SCRD_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X IDR_SET

INTR_CTLR_CHANNEL6_SLICE5_IDR_CLR_0

Offset: 0x3164

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL6_SCRD_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X IDR_CLR

INTR_CTLR_CHANNEL6_SLICE6_VIRQ_0

Offset: 0x3180

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL6_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X

VIRQ

INTR_CTLR_CHANNEL6_SLICE6_VFIQ_0

Offset: 0x3184

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL6_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

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Bit Reset Description

31:0 X

VFIQ

INTR_CTLR_CHANNEL6_SLICE6_IER_0

Offset: 0x3188

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL6_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 IER

INTR_CTLR_CHANNEL6_SLICE6_IER_SET_0

Offset: 0x318c

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL6_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X IER_SET

INTR_CTLR_CHANNEL6_SLICE6_IER_CLR_0

Offset: 0x3190

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL6_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X IER_CLR

INTR_CTLR_CHANNEL6_SLICE6_IEP_CLASS_0

Offset: 0x3194

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL6_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

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Bit Reset Description

31:0 0x0 IEP_CLASS

INTR_CTLR_CHANNEL6_SLICE6_ISR_0

Offset: 0x3198

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL6_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

ISR

INTR_CTLR_CHANNEL6_SLICE6_IDR_0

Offset: 0x319c

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL6_SCRD_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 IDR

INTR_CTLR_CHANNEL6_SLICE6_IDR_SET_0

Offset: 0x31a0

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL6_SCRD_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X IDR_SET

INTR_CTLR_CHANNEL6_SLICE6_IDR_CLR_0

Offset: 0x31a4

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL6_SCRD_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

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Bit Reset Description

31:0 X IDR_CLR

INTR_CTLR_CHANNEL6_SLICE7_VIRQ_0

Offset: 0x31c0

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL6_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X VIRQ

INTR_CTLR_CHANNEL6_SLICE7_VFIQ_0

Offset: 0x31c4

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL6_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X

VFIQ

INTR_CTLR_CHANNEL6_SLICE7_IER_0

Offset: 0x31c8

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL6_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 IER

INTR_CTLR_CHANNEL6_SLICE7_IER_SET_0

Offset: 0x31cc

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL6_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

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Bit Reset Description

31:0 X IER_SET

INTR_CTLR_CHANNEL6_SLICE7_IER_CLR_0

Offset: 0x31d0

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL6_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X IER_CLR

INTR_CTLR_CHANNEL6_SLICE7_IEP_CLASS_0

Offset: 0x31d4

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL6_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 IEP_CLASS

INTR_CTLR_CHANNEL6_SLICE7_ISR_0

Offset: 0x31d8

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL6_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

ISR

INTR_CTLR_CHANNEL6_SLICE7_IDR_0

Offset: 0x31dc

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL6_SCRD_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

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Bit Reset Description

31:0 0x0

IDR

INTR_CTLR_CHANNEL6_SLICE7_IDR_SET_0

Offset: 0x31e0

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL6_SCRD_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X IDR_SET

INTR_CTLR_CHANNEL6_SLICE7_IDR_CLR_0

Offset: 0x31e4

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL6_SCRD_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X IDR_CLR

INTR_CTLR_CHANNEL6_SLICE8_VIRQ_0

Offset: 0x3200

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL6_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X VIRQ

INTR_CTLR_CHANNEL6_SLICE8_VFIQ_0

Offset: 0x3204

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL6_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

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Bit Reset Description

31:0 X VFIQ

INTR_CTLR_CHANNEL6_SLICE8_IER_0

Offset: 0x3208

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL6_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

IER

INTR_CTLR_CHANNEL6_SLICE8_IER_SET_0

Offset: 0x320c

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL6_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X IER_SET

INTR_CTLR_CHANNEL6_SLICE8_IER_CLR_0

Offset: 0x3210

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL6_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X IER_CLR

INTR_CTLR_CHANNEL6_SLICE8_IEP_CLASS_0

Offset: 0x3214

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL6_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

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Bit Reset Description

31:0 0x0 IEP_CLASS

INTR_CTLR_CHANNEL6_SLICE8_ISR_0

Offset: 0x3218

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL6_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 ISR

INTR_CTLR_CHANNEL6_SLICE8_IDR_0

Offset: 0x321c

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL6_SCRD_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

IDR

INTR_CTLR_CHANNEL6_SLICE8_IDR_SET_0

Offset: 0x3220

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL6_SCRD_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X IDR_SET

INTR_CTLR_CHANNEL6_SLICE8_IDR_CLR_0

Offset: 0x3224

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL6_SCRD_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

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Bit Reset Description

31:0 X IDR_CLR

INTR_CTLR_CHANNEL6_SLICE9_VIRQ_0

Offset: 0x3240

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL6_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X VIRQ

INTR_CTLR_CHANNEL6_SLICE9_VFIQ_0

Offset: 0x3244

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL6_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X VFIQ

INTR_CTLR_CHANNEL6_SLICE9_IER_0

Offset: 0x3248

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL6_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

IER

INTR_CTLR_CHANNEL6_SLICE9_IER_SET_0

Offset: 0x324c

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL6_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

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Bit Reset Description

31:0 X

IER_SET

INTR_CTLR_CHANNEL6_SLICE9_IER_CLR_0

Offset: 0x3250

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL6_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X IER_CLR

INTR_CTLR_CHANNEL6_SLICE9_IEP_CLASS_0

Offset: 0x3254

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL6_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 IEP_CLASS

INTR_CTLR_CHANNEL6_SLICE9_ISR_0

Offset: 0x3258

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL6_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 ISR

INTR_CTLR_CHANNEL6_SLICE9_IDR_0

Offset: 0x325c

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL6_SCRD_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

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Bit Reset Description

31:0 0x0 IDR

INTR_CTLR_CHANNEL6_SLICE9_IDR_SET_0

Offset: 0x3260

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL6_SCRD_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X

IDR_SET

INTR_CTLR_CHANNEL6_SLICE9_IDR_CLR_0

Offset: 0x3264

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL6_SCRD_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X IDR_CLR

INTR_CTLR_CHANNEL6_SLICE10_VIRQ_0

Offset: 0x3280

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL6_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X VIRQ

INTR_CTLR_CHANNEL6_SLICE10_VFIQ_0

Offset: 0x3284

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL6_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

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Bit Reset Description

31:0 X VFIQ

INTR_CTLR_CHANNEL6_SLICE10_IER_0

Offset: 0x3288

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL6_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 IER

INTR_CTLR_CHANNEL6_SLICE10_IER_SET_0

Offset: 0x328c

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL6_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X

IER_SET

INTR_CTLR_CHANNEL6_SLICE10_IER_CLR_0

Offset: 0x3290

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL6_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X IER_CLR

INTR_CTLR_CHANNEL6_SLICE10_IEP_CLASS_0

Offset: 0x3294

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL6_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

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Bit Reset Description

31:0 0x0 IEP_CLASS

INTR_CTLR_CHANNEL6_SLICE10_ISR_0

Offset: 0x3298

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL6_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 ISR

INTR_CTLR_CHANNEL6_SLICE10_IDR_0

Offset: 0x329c

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL6_SCRD_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 IDR

INTR_CTLR_CHANNEL6_SLICE10_IDR_SET_0

Offset: 0x32a0

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL6_SCRD_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X

IDR_SET

INTR_CTLR_CHANNEL6_SLICE10_IDR_CLR_0

Offset: 0x32a4

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL6_SCRD_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

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Bit Reset Description

31:0 X

IDR_CLR

INTR_CTLR_CHANNEL7_SLICE0_VIRQ_0

Offset: 0x3800

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL7_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X VIRQ

INTR_CTLR_CHANNEL7_SLICE0_VFIQ_0

Offset: 0x3804

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL7_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X VFIQ

INTR_CTLR_CHANNEL7_SLICE0_IER_0

Offset: 0x3808

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL7_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 IER

INTR_CTLR_CHANNEL7_SLICE0_IER_SET_0

Offset: 0x380c

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL7_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

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Bit Reset Description

31:0 X IER_SET

INTR_CTLR_CHANNEL7_SLICE0_IER_CLR_0

Offset: 0x3810

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL7_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X

IER_CLR

INTR_CTLR_CHANNEL7_SLICE0_IEP_CLASS_0

Offset: 0x3814

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL7_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 IEP_CLASS

INTR_CTLR_CHANNEL7_SLICE0_ISR_0

Offset: 0x3818

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL7_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 ISR

INTR_CTLR_CHANNEL7_SLICE0_IDR_0

Offset: 0x381c

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL7_SCRD_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

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Bit Reset Description

31:0 0x0 IDR

INTR_CTLR_CHANNEL7_SLICE0_IDR_SET_0

Offset: 0x3820

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL7_SCRD_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X IDR_SET

INTR_CTLR_CHANNEL7_SLICE0_IDR_CLR_0

Offset: 0x3824

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL7_SCRD_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X

IDR_CLR

INTR_CTLR_CHANNEL7_SLICE1_VIRQ_0

Offset: 0x3840

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL7_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X VIRQ

INTR_CTLR_CHANNEL7_SLICE1_VFIQ_0

Offset: 0x3844

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL7_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

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Bit Reset Description

31:0 X VFIQ

INTR_CTLR_CHANNEL7_SLICE1_IER_0

Offset: 0x3848

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL7_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 IER

INTR_CTLR_CHANNEL7_SLICE1_IER_SET_0

Offset: 0x384c

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL7_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X IER_SET

INTR_CTLR_CHANNEL7_SLICE1_IER_CLR_0

Offset: 0x3850

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL7_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X

IER_CLR

INTR_CTLR_CHANNEL7_SLICE1_IEP_CLASS_0

Offset: 0x3854

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL7_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

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Bit Reset Description

31:0 0x0

IEP_CLASS

INTR_CTLR_CHANNEL7_SLICE1_ISR_0

Offset: 0x3858

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL7_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 ISR

INTR_CTLR_CHANNEL7_SLICE1_IDR_0

Offset: 0x385c

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL7_SCRD_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 IDR

INTR_CTLR_CHANNEL7_SLICE1_IDR_SET_0

Offset: 0x3860

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL7_SCRD_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X IDR_SET

INTR_CTLR_CHANNEL7_SLICE1_IDR_CLR_0

Offset: 0x3864

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL7_SCRD_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

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Bit Reset Description

31:0 X IDR_CLR

INTR_CTLR_CHANNEL7_SLICE2_VIRQ_0

Offset: 0x3880

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL7_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X

VIRQ

INTR_CTLR_CHANNEL7_SLICE2_VFIQ_0

Offset: 0x3884

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL7_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X VFIQ

INTR_CTLR_CHANNEL7_SLICE2_IER_0

Offset: 0x3888

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL7_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 IER

INTR_CTLR_CHANNEL7_SLICE2_IER_SET_0

Offset: 0x388c

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL7_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

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Bit Reset Description

31:0 X IER_SET

INTR_CTLR_CHANNEL7_SLICE2_IER_CLR_0

Offset: 0x3890

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL7_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X IER_CLR

INTR_CTLR_CHANNEL7_SLICE2_IEP_CLASS_0

Offset: 0x3894

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL7_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

IEP_CLASS

INTR_CTLR_CHANNEL7_SLICE2_ISR_0

Offset: 0x3898

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL7_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 ISR

INTR_CTLR_CHANNEL7_SLICE2_IDR_0

Offset: 0x389c

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL7_SCRD_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

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Bit Reset Description

31:0 0x0 IDR

INTR_CTLR_CHANNEL7_SLICE2_IDR_SET_0

Offset: 0x38a0

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL7_SCRD_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X IDR_SET

INTR_CTLR_CHANNEL7_SLICE2_IDR_CLR_0

Offset: 0x38a4

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL7_SCRD_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X IDR_CLR

INTR_CTLR_CHANNEL7_SLICE3_VIRQ_0

Offset: 0x38c0

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL7_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X

VIRQ

INTR_CTLR_CHANNEL7_SLICE3_VFIQ_0

Offset: 0x38c4

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL7_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

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Bit Reset Description

31:0 X

VFIQ

INTR_CTLR_CHANNEL7_SLICE3_IER_0

Offset: 0x38c8

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL7_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 IER

INTR_CTLR_CHANNEL7_SLICE3_IER_SET_0

Offset: 0x38cc

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL7_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X IER_SET

INTR_CTLR_CHANNEL7_SLICE3_IER_CLR_0

Offset: 0x38d0

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL7_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X IER_CLR

INTR_CTLR_CHANNEL7_SLICE3_IEP_CLASS_0

Offset: 0x38d4

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL7_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

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Bit Reset Description

31:0 0x0 IEP_CLASS

INTR_CTLR_CHANNEL7_SLICE3_ISR_0

Offset: 0x38d8

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL7_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

ISR

INTR_CTLR_CHANNEL7_SLICE3_IDR_0

Offset: 0x38dc

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL7_SCRD_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 IDR

INTR_CTLR_CHANNEL7_SLICE3_IDR_SET_0

Offset: 0x38e0

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL7_SCRD_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X IDR_SET

INTR_CTLR_CHANNEL7_SLICE3_IDR_CLR_0

Offset: 0x38e4

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL7_SCRD_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

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Bit Reset Description

31:0 X IDR_CLR

INTR_CTLR_CHANNEL7_SLICE4_VIRQ_0

Offset: 0x3900

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL7_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X VIRQ

INTR_CTLR_CHANNEL7_SLICE4_VFIQ_0

Offset: 0x3904

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL7_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X

VFIQ

INTR_CTLR_CHANNEL7_SLICE4_IER_0

Offset: 0x3908

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL7_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 IER

INTR_CTLR_CHANNEL7_SLICE4_IER_SET_0

Offset: 0x390c

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL7_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

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Bit Reset Description

31:0 X IER_SET

INTR_CTLR_CHANNEL7_SLICE4_IER_CLR_0

Offset: 0x3910

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL7_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X IER_CLR

INTR_CTLR_CHANNEL7_SLICE4_IEP_CLASS_0

Offset: 0x3914

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL7_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 IEP_CLASS

INTR_CTLR_CHANNEL7_SLICE4_ISR_0

Offset: 0x3918

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL7_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

ISR

INTR_CTLR_CHANNEL7_SLICE4_IDR_0

Offset: 0x391c

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL7_SCRD_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

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Bit Reset Description

31:0 0x0

IDR

INTR_CTLR_CHANNEL7_SLICE4_IDR_SET_0

Offset: 0x3920

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL7_SCRD_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X IDR_SET

INTR_CTLR_CHANNEL7_SLICE4_IDR_CLR_0

Offset: 0x3924

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL7_SCRD_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X IDR_CLR

INTR_CTLR_CHANNEL7_SLICE5_VIRQ_0

Offset: 0x3940

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL7_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X VIRQ

INTR_CTLR_CHANNEL7_SLICE5_VFIQ_0

Offset: 0x3944

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL7_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

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Bit Reset Description

31:0 X VFIQ

INTR_CTLR_CHANNEL7_SLICE5_IER_0

Offset: 0x3948

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL7_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

IER

INTR_CTLR_CHANNEL7_SLICE5_IER_SET_0

Offset: 0x394c

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL7_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X IER_SET

INTR_CTLR_CHANNEL7_SLICE5_IER_CLR_0

Offset: 0x3950

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL7_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X IER_CLR

INTR_CTLR_CHANNEL7_SLICE5_IEP_CLASS_0

Offset: 0x3954

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL7_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

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Bit Reset Description

31:0 0x0 IEP_CLASS

INTR_CTLR_CHANNEL7_SLICE5_ISR_0

Offset: 0x3958

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL7_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 ISR

INTR_CTLR_CHANNEL7_SLICE5_IDR_0

Offset: 0x395c

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL7_SCRD_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

IDR

INTR_CTLR_CHANNEL7_SLICE5_IDR_SET_0

Offset: 0x3960

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL7_SCRD_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X IDR_SET

INTR_CTLR_CHANNEL7_SLICE5_IDR_CLR_0

Offset: 0x3964

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL7_SCRD_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

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Bit Reset Description

31:0 X IDR_CLR

INTR_CTLR_CHANNEL7_SLICE6_VIRQ_0

Offset: 0x3980

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL7_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X VIRQ

INTR_CTLR_CHANNEL7_SLICE6_VFIQ_0

Offset: 0x3984

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL7_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X VFIQ

INTR_CTLR_CHANNEL7_SLICE6_IER_0

Offset: 0x3988

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL7_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

IER

INTR_CTLR_CHANNEL7_SLICE6_IER_SET_0

Offset: 0x398c

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL7_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

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Bit Reset Description

31:0 X

IER_SET

INTR_CTLR_CHANNEL7_SLICE6_IER_CLR_0

Offset: 0x3990

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL7_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X IER_CLR

INTR_CTLR_CHANNEL7_SLICE6_IEP_CLASS_0

Offset: 0x3994

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL7_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 IEP_CLASS

INTR_CTLR_CHANNEL7_SLICE6_ISR_0

Offset: 0x3998

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL7_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 ISR

INTR_CTLR_CHANNEL7_SLICE6_IDR_0

Offset: 0x399c

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL7_SCRD_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

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Bit Reset Description

31:0 0x0 IDR

INTR_CTLR_CHANNEL7_SLICE6_IDR_SET_0

Offset: 0x39a0

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL7_SCRD_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X

IDR_SET

INTR_CTLR_CHANNEL7_SLICE6_IDR_CLR_0

Offset: 0x39a4

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL7_SCRD_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X IDR_CLR

INTR_CTLR_CHANNEL7_SLICE7_VIRQ_0

Offset: 0x39c0

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL7_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X VIRQ

INTR_CTLR_CHANNEL7_SLICE7_VFIQ_0

Offset: 0x39c4

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL7_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

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Bit Reset Description

31:0 X VFIQ

INTR_CTLR_CHANNEL7_SLICE7_IER_0

Offset: 0x39c8

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL7_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 IER

INTR_CTLR_CHANNEL7_SLICE7_IER_SET_0

Offset: 0x39cc

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL7_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X

IER_SET

INTR_CTLR_CHANNEL7_SLICE7_IER_CLR_0

Offset: 0x39d0

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL7_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X IER_CLR

INTR_CTLR_CHANNEL7_SLICE7_IEP_CLASS_0

Offset: 0x39d4

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL7_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

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Bit Reset Description

31:0 0x0 IEP_CLASS

INTR_CTLR_CHANNEL7_SLICE7_ISR_0

Offset: 0x39d8

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL7_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 ISR

INTR_CTLR_CHANNEL7_SLICE7_IDR_0

Offset: 0x39dc

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL7_SCRD_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 IDR

INTR_CTLR_CHANNEL7_SLICE7_IDR_SET_0

Offset: 0x39e0

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL7_SCRD_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X

IDR_SET

INTR_CTLR_CHANNEL7_SLICE7_IDR_CLR_0

Offset: 0x39e4

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL7_SCRD_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

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Bit Reset Description

31:0 X

IDR_CLR

INTR_CTLR_CHANNEL7_SLICE8_VIRQ_0

Offset: 0x3a00

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL7_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X VIRQ

INTR_CTLR_CHANNEL7_SLICE8_VFIQ_0

Offset: 0x3a04

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL7_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X VFIQ

INTR_CTLR_CHANNEL7_SLICE8_IER_0

Offset: 0x3a08

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL7_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 IER

INTR_CTLR_CHANNEL7_SLICE8_IER_SET_0

Offset: 0x3a0c

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL7_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

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Bit Reset Description

31:0 X IER_SET

INTR_CTLR_CHANNEL7_SLICE8_IER_CLR_0

Offset: 0x3a10

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL7_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X

IER_CLR

INTR_CTLR_CHANNEL7_SLICE8_IEP_CLASS_0

Offset: 0x3a14

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL7_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 IEP_CLASS

INTR_CTLR_CHANNEL7_SLICE8_ISR_0

Offset: 0x3a18

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL7_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 ISR

INTR_CTLR_CHANNEL7_SLICE8_IDR_0

Offset: 0x3a1c

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL7_SCRD_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

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Bit Reset Description

31:0 0x0 IDR

INTR_CTLR_CHANNEL7_SLICE8_IDR_SET_0

Offset: 0x3a20

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL7_SCRD_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X IDR_SET

INTR_CTLR_CHANNEL7_SLICE8_IDR_CLR_0

Offset: 0x3a24

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL7_SCRD_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X

IDR_CLR

INTR_CTLR_CHANNEL7_SLICE9_VIRQ_0

Offset: 0x3a40

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL7_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X VIRQ

INTR_CTLR_CHANNEL7_SLICE9_VFIQ_0

Offset: 0x3a44

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL7_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

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Bit Reset Description

31:0 X VFIQ

INTR_CTLR_CHANNEL7_SLICE9_IER_0

Offset: 0x3a48

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL7_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 IER

INTR_CTLR_CHANNEL7_SLICE9_IER_SET_0

Offset: 0x3a4c

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL7_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X IER_SET

INTR_CTLR_CHANNEL7_SLICE9_IER_CLR_0

Offset: 0x3a50

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL7_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X

IER_CLR

INTR_CTLR_CHANNEL7_SLICE9_IEP_CLASS_0

Offset: 0x3a54

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL7_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

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Bit Reset Description

31:0 0x0

IEP_CLASS

INTR_CTLR_CHANNEL7_SLICE9_ISR_0

Offset: 0x3a58

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL7_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 ISR

INTR_CTLR_CHANNEL7_SLICE9_IDR_0

Offset: 0x3a5c

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL7_SCRD_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 IDR

INTR_CTLR_CHANNEL7_SLICE9_IDR_SET_0

Offset: 0x3a60

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL7_SCRD_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X IDR_SET

INTR_CTLR_CHANNEL7_SLICE9_IDR_CLR_0

Offset: 0x3a64

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL7_SCRD_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

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Bit Reset Description

31:0 X IDR_CLR

INTR_CTLR_CHANNEL7_SLICE10_VIRQ_0

Offset: 0x3a80

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL7_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X

VIRQ

INTR_CTLR_CHANNEL7_SLICE10_VFIQ_0

Offset: 0x3a84

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL7_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X VFIQ

INTR_CTLR_CHANNEL7_SLICE10_IER_0

Offset: 0x3a88

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL7_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 IER

INTR_CTLR_CHANNEL7_SLICE10_IER_SET_0

Offset: 0x3a8c

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL7_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

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Bit Reset Description

31:0 X IER_SET

INTR_CTLR_CHANNEL7_SLICE10_IER_CLR_0

Offset: 0x3a90

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL7_SCRE_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X IER_CLR

INTR_CTLR_CHANNEL7_SLICE10_IEP_CLASS_0

Offset: 0x3a94

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL7_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

IEP_CLASS

INTR_CTLR_CHANNEL7_SLICE10_ISR_0

Offset: 0x3a98

Read/Write: RO

Parity Protection: N

SCR Protection: CHANNEL7_SCRE_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 ISR

INTR_CTLR_CHANNEL7_SLICE10_IDR_0

Offset: 0x3a9c

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL7_SCRD_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

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Bit Reset Description

31:0 0x0 IDR

INTR_CTLR_CHANNEL7_SLICE10_IDR_SET_0

Offset: 0x3aa0

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL7_SCRD_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X IDR_SET

INTR_CTLR_CHANNEL7_SLICE10_IDR_CLR_0

Offset: 0x3aa4

Read/Write: RW

Parity Protection: N

SCR Protection: CHANNEL7_SCRD_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X IDR_CLR

INTR_CTLR_COMMON_SLICE0_GISR_0

Offset: 0xf800

Read/Write: RO

Parity Protection: N

SCR Protection: SCR_COMMON_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X

GISR

INTR_CTLR_COMMON_SLICE0_FIR_0

Offset: 0xf804

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_COMMON_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

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Bit Reset Description

31:0 0x0

FIR

INTR_CTLR_COMMON_SLICE0_FIR_SET_0

Offset: 0xf808

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_COMMON_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X FIR_SET

INTR_CTLR_COMMON_SLICE0_FIR_CLR_0

Offset: 0xf80c

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_COMMON_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X FIR_CLR

INTR_CTLR_COMMON_SLICE0_CIDR_0

Offset: 0xf810

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_COMMON_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 CIDR

INTR_CTLR_COMMON_SLICE0_CIDR_SET_0

Offset: 0xf814

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_COMMON_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

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Bit Reset Description

31:0 X CIDR_SET

INTR_CTLR_COMMON_SLICE0_CIDR_CLR_0

Offset: 0xf818

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_COMMON_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X

CIDR_CLR

INTR_CTLR_COMMON_SLICE1_GISR_0

Offset: 0xf840

Read/Write: RO

Parity Protection: N

SCR Protection: SCR_COMMON_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X GISR

INTR_CTLR_COMMON_SLICE1_FIR_0

Offset: 0xf844

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_COMMON_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 FIR

INTR_CTLR_COMMON_SLICE1_FIR_SET_0

Offset: 0xf848

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_COMMON_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

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Bit Reset Description

31:0 X FIR_SET

INTR_CTLR_COMMON_SLICE1_FIR_CLR_0

Offset: 0xf84c

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_COMMON_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X FIR_CLR

INTR_CTLR_COMMON_SLICE1_CIDR_0

Offset: 0xf850

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_COMMON_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

CIDR

INTR_CTLR_COMMON_SLICE1_CIDR_SET_0

Offset: 0xf854

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_COMMON_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X CIDR_SET

INTR_CTLR_COMMON_SLICE1_CIDR_CLR_0

Offset: 0xf858

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_COMMON_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

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Bit Reset Description

31:0 X CIDR_CLR

INTR_CTLR_COMMON_SLICE2_GISR_0

Offset: 0xf880

Read/Write: RO

Parity Protection: N

SCR Protection: SCR_COMMON_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X GISR

INTR_CTLR_COMMON_SLICE2_FIR_0

Offset: 0xf884

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_COMMON_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 FIR

INTR_CTLR_COMMON_SLICE2_FIR_SET_0

Offset: 0xf888

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_COMMON_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X

FIR_SET

INTR_CTLR_COMMON_SLICE2_FIR_CLR_0

Offset: 0xf88c

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_COMMON_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

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Bit Reset Description

31:0 X

FIR_CLR

INTR_CTLR_COMMON_SLICE2_CIDR_0

Offset: 0xf890

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_COMMON_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 CIDR

INTR_CTLR_COMMON_SLICE2_CIDR_SET_0

Offset: 0xf894

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_COMMON_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X CIDR_SET

INTR_CTLR_COMMON_SLICE2_CIDR_CLR_0

Offset: 0xf898

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_COMMON_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X CIDR_CLR

INTR_CTLR_COMMON_SLICE3_GISR_0

Offset: 0xf8c0

Read/Write: RO

Parity Protection: N

SCR Protection: SCR_COMMON_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

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Bit Reset Description

31:0 X GISR

INTR_CTLR_COMMON_SLICE3_FIR_0

Offset: 0xf8c4

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_COMMON_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

FIR

INTR_CTLR_COMMON_SLICE3_FIR_SET_0

Offset: 0xf8c8

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_COMMON_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X FIR_SET

INTR_CTLR_COMMON_SLICE3_FIR_CLR_0

Offset: 0xf8cc

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_COMMON_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X FIR_CLR

INTR_CTLR_COMMON_SLICE3_CIDR_0

Offset: 0xf8d0

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_COMMON_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

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Bit Reset Description

31:0 0x0 CIDR

INTR_CTLR_COMMON_SLICE3_CIDR_SET_0

Offset: 0xf8d4

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_COMMON_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X CIDR_SET

INTR_CTLR_COMMON_SLICE3_CIDR_CLR_0

Offset: 0xf8d8

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_COMMON_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X

CIDR_CLR

INTR_CTLR_COMMON_SLICE4_GISR_0

Offset: 0xf900

Read/Write: RO

Parity Protection: N

SCR Protection: SCR_COMMON_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X GISR

INTR_CTLR_COMMON_SLICE4_FIR_0

Offset: 0xf904

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_COMMON_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

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Bit Reset Description

31:0 0x0 FIR

INTR_CTLR_COMMON_SLICE4_FIR_SET_0

Offset: 0xf908

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_COMMON_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X FIR_SET

INTR_CTLR_COMMON_SLICE4_FIR_CLR_0

Offset: 0xf90c

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_COMMON_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X FIR_CLR

INTR_CTLR_COMMON_SLICE4_CIDR_0

Offset: 0xf910

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_COMMON_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

CIDR

INTR_CTLR_COMMON_SLICE4_CIDR_SET_0

Offset: 0xf914

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_COMMON_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

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Bit Reset Description

31:0 X

CIDR_SET

INTR_CTLR_COMMON_SLICE4_CIDR_CLR_0

Offset: 0xf918

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_COMMON_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X CIDR_CLR

INTR_CTLR_COMMON_SLICE5_GISR_0

Offset: 0xf940

Read/Write: RO

Parity Protection: N

SCR Protection: SCR_COMMON_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X GISR

INTR_CTLR_COMMON_SLICE5_FIR_0

Offset: 0xf944

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_COMMON_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 FIR

INTR_CTLR_COMMON_SLICE5_FIR_SET_0

Offset: 0xf948

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_COMMON_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

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Bit Reset Description

31:0 X FIR_SET

INTR_CTLR_COMMON_SLICE5_FIR_CLR_0

Offset: 0xf94c

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_COMMON_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X

FIR_CLR

INTR_CTLR_COMMON_SLICE5_CIDR_0

Offset: 0xf950

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_COMMON_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 CIDR

INTR_CTLR_COMMON_SLICE5_CIDR_SET_0

Offset: 0xf954

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_COMMON_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X CIDR_SET

INTR_CTLR_COMMON_SLICE5_CIDR_CLR_0

Offset: 0xf958

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_COMMON_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

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Bit Reset Description

31:0 X CIDR_CLR

INTR_CTLR_COMMON_SLICE6_GISR_0

Offset: 0xf980

Read/Write: RO

Parity Protection: N

SCR Protection: SCR_COMMON_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X GISR

INTR_CTLR_COMMON_SLICE6_FIR_0

Offset: 0xf984

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_COMMON_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

FIR

INTR_CTLR_COMMON_SLICE6_FIR_SET_0

Offset: 0xf988

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_COMMON_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X FIR_SET

INTR_CTLR_COMMON_SLICE6_FIR_CLR_0

Offset: 0xf98c

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_COMMON_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

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Bit Reset Description

31:0 X FIR_CLR

INTR_CTLR_COMMON_SLICE6_CIDR_0

Offset: 0xf990

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_COMMON_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 CIDR

INTR_CTLR_COMMON_SLICE6_CIDR_SET_0

Offset: 0xf994

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_COMMON_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X CIDR_SET

INTR_CTLR_COMMON_SLICE6_CIDR_CLR_0

Offset: 0xf998

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_COMMON_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X

CIDR_CLR

INTR_CTLR_COMMON_SLICE7_GISR_0

Offset: 0xf9c0

Read/Write: RO

Parity Protection: N

SCR Protection: SCR_COMMON_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

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Bit Reset Description

31:0 X

GISR

INTR_CTLR_COMMON_SLICE7_FIR_0

Offset: 0xf9c4

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_COMMON_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 FIR

INTR_CTLR_COMMON_SLICE7_FIR_SET_0

Offset: 0xf9c8

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_COMMON_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X FIR_SET

INTR_CTLR_COMMON_SLICE7_FIR_CLR_0

Offset: 0xf9cc

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_COMMON_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X FIR_CLR

INTR_CTLR_COMMON_SLICE7_CIDR_0

Offset: 0xf9d0

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_COMMON_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

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Bit Reset Description

31:0 0x0 CIDR

INTR_CTLR_COMMON_SLICE7_CIDR_SET_0

Offset: 0xf9d4

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_COMMON_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X

CIDR_SET

INTR_CTLR_COMMON_SLICE7_CIDR_CLR_0

Offset: 0xf9d8

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_COMMON_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X CIDR_CLR

INTR_CTLR_COMMON_SLICE8_GISR_0

Offset: 0xfa00

Read/Write: RO

Parity Protection: N

SCR Protection: SCR_COMMON_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X GISR

INTR_CTLR_COMMON_SLICE8_FIR_0

Offset: 0xfa04

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_COMMON_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

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Bit Reset Description

31:0 0x0 FIR

INTR_CTLR_COMMON_SLICE8_FIR_SET_0

Offset: 0xfa08

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_COMMON_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X FIR_SET

INTR_CTLR_COMMON_SLICE8_FIR_CLR_0

Offset: 0xfa0c

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_COMMON_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X

FIR_CLR

INTR_CTLR_COMMON_SLICE8_CIDR_0

Offset: 0xfa10

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_COMMON_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 CIDR

INTR_CTLR_COMMON_SLICE8_CIDR_SET_0

Offset: 0xfa14

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_COMMON_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

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Bit Reset Description

31:0 X CIDR_SET

INTR_CTLR_COMMON_SLICE8_CIDR_CLR_0

Offset: 0xfa18

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_COMMON_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X CIDR_CLR

INTR_CTLR_COMMON_SLICE9_GISR_0

Offset: 0xfa40

Read/Write: RO

Parity Protection: N

SCR Protection: SCR_COMMON_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X GISR

INTR_CTLR_COMMON_SLICE9_FIR_0

Offset: 0xfa44

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_COMMON_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

FIR

INTR_CTLR_COMMON_SLICE9_FIR_SET_0

Offset: 0xfa48

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_COMMON_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

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Bit Reset Description

31:0 X

FIR_SET

INTR_CTLR_COMMON_SLICE9_FIR_CLR_0

Offset: 0xfa4c

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_COMMON_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X FIR_CLR

INTR_CTLR_COMMON_SLICE9_CIDR_0

Offset: 0xfa50

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_COMMON_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 CIDR

INTR_CTLR_COMMON_SLICE9_CIDR_SET_0

Offset: 0xfa54

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_COMMON_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X CIDR_SET

INTR_CTLR_COMMON_SLICE9_CIDR_CLR_0

Offset: 0xfa58

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_COMMON_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

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Bit Reset Description

31:0 X CIDR_CLR

INTR_CTLR_COMMON_SLICE10_GISR_0

Offset: 0xfa80

Read/Write: RO

Parity Protection: N

SCR Protection: SCR_COMMON_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X

GISR

INTR_CTLR_COMMON_SLICE10_FIR_0

Offset: 0xfa84

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_COMMON_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 FIR

INTR_CTLR_COMMON_SLICE10_FIR_SET_0

Offset: 0xfa88

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_COMMON_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X FIR_SET

INTR_CTLR_COMMON_SLICE10_FIR_CLR_0

Offset: 0xfa8c

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_COMMON_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

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Bit Reset Description

31:0 X FIR_CLR

INTR_CTLR_COMMON_SLICE10_CIDR_0

Offset: 0xfa90

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_COMMON_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 CIDR

INTR_CTLR_COMMON_SLICE10_CIDR_SET_0

Offset: 0xfa94

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_COMMON_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X

CIDR_SET

INTR_CTLR_COMMON_SLICE10_CIDR_CLR_0

Offset: 0xfa98

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_COMMON_0

Reset: 0xXXXXXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:0 X CIDR_CLR

INTR_CTLR_COMMON_CTRL_0

Offset: 0xffc0

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_COMMON_0

Reset: 0x00000000 (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxx0)

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Bit Reset Description

0 0x0 ENABLE_TIMESTAMPING:

Global enable for timestamping, used to control the EnableTsc signal. When 0b, the TSC terminal node is

disabled to reduce power consumption.

8.3 Timers

8.3.1 Overview

This chapter documents the various timers available to software in a Xavier Series SoC system. The following

table summarizes the different types of timer elements.

Table 8.14 List of Time-Keeping Elements

Name Primary Use

Interrupt

(1)

Security Frequency

Range

Notes

RTC Wall Clock RTC Configurab

1 kHz Seconds counter lockable

AOWDT SC7 watchdog AOWDT Configurab

1 kHz Part of RTC, last resort internal watchdog

USEC Real-time source - Configurab

1 MHz Also generates time reference pulses

TMR NV Generic TMR0-9 Local Configurab

1 MHz Only the ones at top named here, local timers exist

in some blocks

WDT Top and local

watchdog timers

WDT2-0 Local Configurab

1 MHz Only the ones at top named here, local WDT exist

in some blocks

TSC Reference for GT - TrustZone/

Configurab

30 MHz Counter value can only be updated in secure mode.

GT ARM Generic

PPI

(2)

TrustZone TSC These timers use TSC as reference.

A9T

Cortex -A9 Timers

PPI TrustZone SCU Problematic for DVFS

(1) See the Interrupt Controller chapter for the authoritative mapping of RTC/TMR/WDT interrupts.

(2) PPIs are per CPU Private Peripheral Interrupts.

All timer modules support fine grain access rights. The security model is TrustZone for modules coming from

ARM or following the ARM architecture prescriptions: TSC, GT, and A9T are the configurable NV security

models based on Security Control Register (SCR) for all other modules, including the NV-specific TSC

implementation registers.

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All time-keeping modules can be configured to stop during debug. This is useful to suspend the operation of

WDT (to avoid resetting the chip) and the CCPLEX GT (suspending the OS tick). The only exception is the

safety reference counter in RTC.

Conventions of Units

This TRM chapter follows the IEEE and NIST conventions for multiplying prefixes.

Among other things, this convention uses an 'i' to indicate the binary convention, and its absence to indicate

decimal. So, 1 KiB is 2 or 1,024 bytes, and 1 KB is 10 or 1,000 bytes. Similarly it uses:

10 3

Mi for 2 and M for 10

20 6

Gi for 2 and G for 10

30 9

Ti for 2 and T for 10

40 12

Glossary and Acronyms

Note that different names may end up in the same acronym when the entire Xavier TRM is put in perspective.

The acronyms listed here are within the context of the Timers chapter.

Term Definition

AO Always On

ARM Processor Complex ARM processor core itself plus some closely associated peripherals, including

CCPLEX, the main CPU complex of eight Carmel cores

Multiple Cortex-R5 clusters

The Cortex-A9 ADSP inside APE

AVIC ARM Vectored Interrupt Controller

GT Generic Timer

GTE Generic Timestamping Engine

LFSR Linear Feedback Shift Register

LIC Legacy Interrupt Controller

LNCO Lockable NCO

MTSC Master TSC

NCO Numerically Controlled Oscillator

OSC Oscillator

PCR Present Count value Register

PTV Present Trigger Value, the value loaded at start into an NV timer

RTC Real-Time Clock

SMP Symmetrical Multi-Processing

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Term Definition

SPE Sensor Processing Engine

TKE Time-Keeping Element, the module instantiating NV timers and WDTs

TMR TMR refers to NV timers

TSC Timer’s System Counter, also known as TimeStamp Counter

WDT WatchDog Timer

Relevant Chapters in the TRM

Address Map

Clock Controller and Reset (CAR)

Hardware Safety Manager (HSM)

Address Map

The address spaces (in 64 KiB pages) assigned to the different timers modules are as follows:

Each TKE

One page for shared registers

One page per NV Timer, nT of them where nT is a configuration parameter

One page per WDT, nW of them where nW is a configuration parameter

Each GTE requires one page

The RTC requires two pages:

One page for the RTC proper

One page for the AOWDT

The TSC requires four pages total

One page for each of the two ARM specified frames

One page for the TSC implementation registers

One page for the microsecond (µs) counter

Clocks

The TSC RefClk (aka tsc_ref_clk) is specific to timers and generated inside CAR using dedicated circuitry. The

base logic is a fractional divider, but with an additional adjust signal to allow for fine control of the generated

frequency. The fractional divider is part of CAR with the adjust signal coming from TSC.

TKE uses the following clocks:

APB clock

TSC RefClk, used for the TSC input and for general operation

TKE also uses one of these two clocks

OSC for the TKE instance inside the Always On partition

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clk_m for all other TKE instances

RTC uses the following clocks:

APB clock

The 32,768 Hz reference clock

TSC uses the following clocks:

APB clock

The 32,768 Hz reference clock

TSC RefClk

OSC clock (for the microsecond and reference pulse generation)

GTE uses the following clocks:

APB clock

TSC RefClk

Resets

Most modules have an associated software reset control in CAR.

The following time-related modules do not have a software reset:

TSC and RTC

As they maintain the notion of secure time and may be used to generate corresponding secure interrupts, their

operations should not be impeded by non-secure software. This requirement applies to the microsecond

counter (USEC) inside TSC as well.

TOP TKE

TOP TKE can also be used to expose secure time, so has no software reset. Other TKEs, however, still have

software resets.

The TSC terminal nodes are always associated with a logic block that consumes the TSC value. The TSC

terminal node may share their reset with other logic block it is tightly coupled with. The following table

summarizes the TSC terminal nodes and their reset logic.

Table 8.15 Terminal Nodes Reset Logic

Terminal node Reset logic

In AON (used for AON TKE) By software reset, CLK_RST_CONTROLLER_RST_DEV_TSCTNAON;

must be enabled by software at boot time for cold boot.

Disabled and restarted by software when terminal node is power gated.

ADSP and ADMA TSC in APE On same reset as ADSP and ADMA, no special action needed.

BPMP, SCE and RCE By software reset, CLK_RST_CONTROLLER_RST_DEV_TSCTN<BPMP, SCE, RCE>;

must be enabled by software during respectively BPMP, SCE and RCE startup sequence.

GPU On same reset as GPU, no special action needed.

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Terminal node Reset logic

CCPLEX On ROC reset, no special action needed.

Backbone (top TKE and GTE) On system reset, no special action needed.

Coresight and iLA On same reset as Coresight and iLA, no special action needed.

VI By software reset, CLK_RST_CONTROLLER_RST_DEV_TSCTNVI;

must be enabled by software during VI startup sequence.

PVA{0,1} By software reset, CLK_RST_CONTROLLER_RST_DEV_PVA<0,1>_TSCTN;

must be enabled by software during PVA startup sequence.

Falcon On same reset as falcon, no special action needed.

8.3.2 Functional Description

In Xavier, the common reference for all timers is a frequency corrected version of the 32,768 Hz input clock.

When operated in locked mode, the timers operate as a hierarchy shown below. When locking is not enabled,

the different timers operate independently.

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Figure 8.8 Timer Hierarchy

All Time-Keeping Elements (TKEs) in Xavier can be traced to the OSC or 32,768 Hz clocks. All TKEs, except

TSC, can optionally take TSC as their timing reference to ensure a universal timebase. This, however, is not a

mandatory mode of operation (see figure above).

Locking the reference happens via a Numerically Controlled Oscillator (NCO), i.e., a phase accumulator. An

NCO can be coupled with a very simple loop filter to lock its frequency to a reference (i.e., as very simple DPLL,

denoted LNCO for lockable NCO in this document).

Hierarchical Grouping

For ease of use, some TKE's are provided in a packaged module called Time-Keeping Element ( ) TKE

centered around the NV timers.

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Figure 8.9 Timekeeping Element IP Module

A TKE contains the following elements:

A TSC value synchronized to the TKE clock. The TSC value is used both for the operation of the timers inside the

TKE and exposed in software readable registers (providing a low-latency path for TSC access by a local processor).

The TSC value comes in parallel format, normally from a TSC terminal node. The terminal node could be used by

other blocks and is not instantiated inside the TKE itself.

Local microsecond and OSC counters, also synchronized to the TKE clock. These counters are used for the

operation of the timers and exposed in software readable registers. Contrary to the TSC, the microsecond and OSC

counters in different TKE modules are not aligned to a common master via hardware mechanisms.

A programmable number of NV timers, nT, at maximum 16.

A programmable number of watchdog timers, nW, at maximum 4.

An optional interrupt routing block, with nSI shared interrupts

An APB interface

A TKE module exposes as outputs:

A set of interrupts

The complete set of raw interrupts are always present. But only a smaller number, nDI, may be connected to

an interrupt controller

A set of aggregated and routed interrupts when the interrupt routing block is present

A set of WDT reset request interface signals, connected only when required.

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The next table shows the characteristics of the different TKE instances.

Table 8.16 TKE Instances

Module nT nW nDI nSI Remark

Top 10 3 14 10 System-level use cases, direct interrupts are from the WDTs only

WDT0 directly connected to CCPLEX (IRQ/FIQ), system

WDT

WDT1 used as redundant to WDT0 or for software-

defined use, IRQ/FIQ not connected

WDT2 being the APE WDT for legacy reasons, IRQ/FIQ

not connected

SPE

4 1 7 0 Local timekeeping, direct interrupts connected to local interrupt

controller except remote WDT interrupt.

SCE

BPMP

APE

PVA

RCE

Care must be taken to make sure that the SPE instance can still operate correctly when VDD_CORE is off and

OSC is present, possibly only for a subset of internal configurations. All instances of TKE, including SPE, do not

operate correctly when the OSC is off and only the 32,768 Hz clock is active.

TSC

The TSC logic operates in the AO domain for expediency.

Figure 8.10 TSC Generation

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A subset of MTSC is sent to RTC, allowing RTC to be optionally locked in frequency with TSC.

For convenience, the microsecond counter with associated reference pulses generation (see TKE Module,

) is instantiated inside the TSC logic, to share the same APB Including NVIDIA Timers and Watchdog Timers

interface.

Master TSC Generation

The master TSC is a high accuracy NCO operating on the 32,768 Hz clock. It supports frequency error

correction by allowing the master TSC operation to track an accurate external reference if wanted. As the

external reference is not hardware visible at the master TSC boundary, the tracking loop needs to be done in

software.

To support a very fine granularity for the frequency error correction, the master TSC uses a programmable bit of

the MTSC as the count enable for the rational divider controlling the adjust signal, this is equivalent to scaling

the divider by powers of 2.

Figure 8.11 Master TSC Generation

The master TSC's nominal frequency is programmable. The recommended value is 31.25 MHz so that the

period (32 nS) is a power of 2.

The MTSC nominal frequency is given by the formula below

The selected bit of MTSC must be correctly sampled (no frequency aliasing), bit[b] of MTSC can be interpreted

as a square wave with frequency ( / 2 ) sampled by the 32,768 Hz clock. Correct detection of the edges

out

b+1

require the sampling frequency to be at least twice the frequency of the sampled square wave, so:

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This can be solved for the value of b:

Using the recommended target frequency of 31.25 MHz and the 32,768 Hz input clock frequency gives:

The supported range for b is [9,16].

The width of the parameters of the adjustable rational divider with some extra margin, giving 24 bits for N and

12 bits for D , but the exact structure of the NCO needs to take into account the fact that the ratio is larger than

1. The corresponding structure splits the ratio into an integer and fractional part, that is:

The hardware directly uses R , D and M , with software responsible to calculate their correct value.

0 0 0

The corresponding structure of the NCO is shown below, including the adjust capability, with a total of four

software controlled parameters. The implementation further restricts A to be +1 or -1, A is the direction of the

0 0

frequency correction while the magnitude of the correction is controlled by the parameters of the rational divider

controlling the adjust frequency: N , D and b.

1 1

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Figure 8.12 NCO Structure for MTSC Generation

Slave TSC

In Xavier, only OSC at 38.4 MHz with K = 1 is supported.

The slave TSC is essentially a rational divider with adjust capabilities followed by a counter. In the normal

operation, the counter simply increments by one for each rising edge of the divided clock, similar to previous

chips, but can count by K instead to support low power modes where PLLs are stopped and only OSC is

available and operates at a frequency below the nominal TSC update frequency.

The slave TSC always takes its initial value from the master TSC and can optionally be dynamically locked on

it, this is achieved by adjusting the rational divider based on the deviation between the master and slave TSC

values.

Note that this function is not supported and must be disabled.

TSC Distribution Logic

The TSC distribution logic operates by replicating the TSC value at terminal nodes. This is achieved by

broadcasting both RefClk and serialized synchronization messages to all terminal nodes, plus a Halt indication

used to stop TSC during debug. This is transparent to software except for the need to enable the distribution

function.

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Generic Timestamping Engine

The generic timestamping engine (GTE) is an IP block that can be instantiated where timestamping is

performed by hardware instead of software. GTEs across the chip snoop a subset of signals:

Interrupts, either close to LIC or close to AVIC inside a Cortex-R5 processor complex

GPIO signals, especially for the sensor signals used by the SPE

The generic timestamping engine snoops a configurable set of signals, timestamps any change on them and

presents the timestamped events to software via FIFOs and an APB interface. Specific care is taken to make

the timestamping engine secure, i.e., to avoid security attacks through the use of timestamping.

The generic timestamping engine is built from a configurable number (nTS) of timestamping slices, each slice

built from a configurable number (nC) of capture slices, each capture slice able to snoop up to 32 signals, and

an arbitration stage when there are more than one capture slice per timestamping slice. Each timestamping

slice is normally associated with a different master in the SoC in particular, to provide differentiated security. All

timestamping slices share a common APB interface.

The capture slice continuously monitors the set of enabled and not disabled inputs, if the current value is

different from the last captured value and there is place in the capture FIFO:

The captured value is updated to be the current value

The current and last captured value is placed in the FIFO together with the slice ID and enough LSB of the TSC to

allow a correct disambiguation of the timestamp later on.

If multiple capture slices are present, an arbitration stage merges the different capture slices into a common

output FIFO.

Each output slice then presents the timestamping records to software via a set of access registers. Each

timestamping slice has its own set of access registers to allow for differentiated security, but all timestamping

slices share a common APB interface. Each timestamping slice can also generate an interrupt based on the

FIFO occupancy; that interrupt may or not be connected to an interrupt controller.

The access registers can present the capture records either in raw form or as a set of individual bit changes.

Encoded Form for Captured Information

The raw information contains the current and previously captured value of the signals in the slice as a bitmap.

Encoding transforms that into a sequence of changes. This is done by:

XORing the previous and current values to calculate a change bitmap

Iterating a procedure that:

Finds the lowest index of a bit at 1 in the change bitmap, providing the index and the value of the bit in a

Clears the corresponding bit from the change bit map until the change bitmap is zero.

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The index provides the full information about the signal captured; the register fields are defined so that the

combination (slice number, bit index) gives the interrupt number.

General Structure of GTE

The general structure of the GTE is shown in the figure below.

Figure 8.13 Generic Timestamping Engine

There are multiple instances of the GTE. Each instance has a width defined by a number of 32-bit slices (nS).

Some instances are paired to support multiple levels of security.

Table 8.17 GTE Instances

Module Paired nS Remark

LIC Yes TBD A pair of GTE for interrupt timestamping between LIC and GIC. Note that local GIC interrupts

are not timestamped.

BPMP No

2 Timestamping the local interrupts, i.e., the inputs to the AVIC.

SCE No

PVA No

RCE No

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Module Paired nS Remark

SPE No 3 Timestamping the local interrupts, i.e., the inputs to the VIC, plus a small subset of GPIOs.

RefClk Source Change Logic

The recommended usage model is to always use OSC (at 38.4 MHz) and with K=1 always.

Power Management

The TSC logic is not power gated but implements clock gating. Note that as it provides an SoC-wide timing

reference, TSC is normally always enabled.

s The slave TSC and TSC distribution logic can not work when the OSC is disabled, as RefClk i not available

then. OSC is disabled in some of the deep sleep states, with only 32,768 Hz present. This is true for some

variants of SC7. The transitions to and from the deep sleep states that disable the OSC circuitry are controlled

by the PMC logic. The PMC logic handshakes with TSC, to allow for a clean shutdown and restart of the slave

TSC as well as TSC distribution in case OSC is stopped in the target power state.

Entering a deep sleep mode where OSC is to be stopped

PMC asserts a deep sleep request signal while OSC and RefClk are still running

TSC stops the slave TSC and the distribution logic, then assert a deep sleep status signal to PMC

Stopping is logically equivalent to disabling these blocks via the software control bits

PMC can now stop OSC and indirectly stops RefClk

Exiting a deep sleep mode where OSC already stopped

PMC restarts OSC and indirectly restarts RefClk, and waits until OSC is stable

PMC deasserts the deep sleep request signal

TSC restarts the slave TSC and the TSC distribution logic if their respective software enable bits is set

Restarting the slave TSC requires an initialization, the master TSC value is copied to the slave TSC counter at

the next edge of the 32,768 Hz clock

Restarting the TSC distribution preferably includes sending a synchronization message as soon as possible

TSC deasserts the deep sleep status signal to PMC

The whole sequence is similar to the sequence used for ARM processors. The handshake must also work even

when TSC itself is disabled, to avoid blocking the forward progress of the PMC state machine. This may require

providing a non-gateable clock to the handshake logic.

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Figure 8.14 Deep Sleep Handshake with PMC

Real Time Clock

The internal RTC (or simply RTC) is a real-time clock in the AO partition that measures elapsed time since the

last cold boot, and is not affected by SC7 entry/exit transitions. Note that the PMIC also generally provides an

external RTC with better robustness (not affected by the cold boot of Xavier).

The RTC accumulates real time in a mixed radix format of seconds (32 bits) and milliseconds (10 bits), it

operates on the 32,768 Hz clock and can take its reference from the 32,768 Hz clock itself or TSC.

The seconds counter can be updated by software to provide an initial offset different from zero at initialization,

and later updates sticky disabled for security.

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The RTC provides different alarms that can be used as interrupts or SC7 wake signals. The RTC also provides

a safety reference counter, with no configuration whatsoever that can be used to check the correct operating

frequency of other TKEs.

RTC logic operates in the 32,768 Hz clock domain, and software must take into account when accessing RTC

registers. In particular, the RTC module maintains a ‘busy’ status register bit which is set (1’b1) while a register

write is being transferred. Software must not send a write when this bit is set (this requires write accesses to the

RTC to be protected by a resource semaphore if more than two agents are allowed to access the RTC) .

The RTC maintains a count of seconds and milliseconds since the last cold reset. It can select between the

32,768 Hz clock and MTSC as time base. The only difference is the first NCO stage, the rest of the logic is

independent of the selected reference.

The logic itself always operates at the 32,768 Hz clock.

Figure 8.15 RTC Generation

The RTC block also contains alarms implemented by comparison between a target value and the current RTC

value. The RTC value is exported to SPE where it is used to generate local alarms on top of the alarms

supported in RTC itself.

For safety related purposes, the RTC also provides a reference counter, always enabled, that simply

increments at each rising edge of the 32,768 Hz clock. This can be used as a safety reference to assess the

health of other timing elements. This reference counter is never halted, especially it is not stopped during debug

and has no configuration.

Always On WatchDog Timer

Xavier provides a watchdog timer (WDT) in the Always On power domain, with the following rationale:(AO)

Its operation is not dependent on OSC; it only requires the 32,768 Hz clock to be active.

The timer can be used to detect and flag SC7 related issues, such as an inability to wake up.

The AO WDT requirements are only slightly different from a standard WDT:

Opernates on the 32,768 Hz clock, so that it can operate continuously, including during power states where OSC is

OFF when WDT operation is suspended.

The actions associated with some expiration levels are redefined as wake events:

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Expiration level 2 asserts a standard wake signal.

Expiration level 3 asserts a wake signal that also clears the PMC scratch register info indicating warm boot.

The debug reset associated with expiration level 4, while connected, must not be used.

The AO WDT reuses the implementation of the TKE WDT, including the register interface; the only changes are

in the inputs and outputs connected to it, especially the operating clock.

Microsecond Counter and Time Reference Pulses Generation

The USEC module broadcasts periodic pulses with 1 microsecond and 1 millisecond periods, allowing time to

be measured in a platform-independent way. USEC operates on OSC to allow operation when no PLL is active.

The time base can be OSC itself or TSC, and USEC also maintains a counter of elapsed microseconds.

While USEC operates in the AO partition, it relies on OSC for its operation and so may be suspended in some

power states where RTC keeps counting, and so USEC and RTC are complementary, not redundant.

Figure 8.16 Reference Pulse Generation and Microsecond Counter

8.3.3 TKE Module

NV Timers (TMRs) and Watchdog Timers (WDTs) are instantiated as part of a TKE module. There are nT

timers and nW watchdog timers per TKE. The register interface constraints the dimensioning to a maximum of

16 timers and four watchdog timers.

Each TKE also includes registers to make different measures of time available: OSC, microsecond counter, and

TSC. This access is low latency to the local processor.

Finally, each TKE can optionally contain an interrupt routing function, this is only present for the TKE

instantiated at the top level to limit the number of top-level interrupts.

For debug purposes, the TKE operation can optionally be halted during debug. This is especially important to

suspend the operation of enabled WDTs that could otherwise reset the system while debug is in progress.

NV Timer

Each NV timer is a general-purpose timer with the following characteristics:

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Downcounter of 29 bits generating an interrupt when reaching zero

The decrement rate is on a configurable reference:

At 1 MHz, as defined by the 1 MHz reference pulse

At OSC rate

On any edge of TSC[0], so normally at the recommended 31.25 MHz TSC update rate

On any edge of TSC[12], so normally at 31.25 MHz / 4096, about 7.63 kHz

Optionally operates in periodic mode, i.e. automatically reload the start value when reaching zero

Optional Interrupt Routing

The interrupt routing block takes the set of interrupts present in the TKE and aggregates them in a configurable

fashion into nSI shared interrupts. This is only present for the top-level TKE and the shared interrupts are

hooked to the LIC in that case.

The number of (internal) interrupts inside a TKE is dependent on the number of NV timers and WDT:

Each NV timer has one associated interrupt, set when the downcounter reaches 0

Each WDT has three associated interrupts, one for each of the three first expirations of the WDT

The interrupt logic uses nSI masks, each containing (nT + 3 * nW) bits. Each mask selects which local interrupt

are included in the corresponding shared interrupt. The interrupt logic also exposes interrupt status registers to

software.

Watchdog Timer

A general view of the WDT logic is shown below.

Figure 8.17 WDT Structure

The watchdog mechanism operates in the following way:

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Each ARM processor complex is associated with one WDT. For the CCPLEX, all cores are in the same coherency

domain and are considered as one SMP processor for software purposes; i.e., all cores inside CCPLEX are

associated with the same WDT (WDT0 in the top TKE).

Select as reference time base either:

Any of the timer zero pulses

A transition on any bit in a defined subset of the bits of the local TSC counter

Implements a periodic downcounter decrementing at the selected rate. The downcounter generates an expiration

event when it reaches zero.

At each expiration, the WDT increases the expiration level, saturating at level 5

The increase may be larger than 1, the exact increase is configurable per expiration level

The WDT logic can assert specific output signals based on the current expiration

For the first three expiration levels, the WDT can assert a corresponding interrupt, each with a specific use:

If the expiration level is 1 or more, a normal priority interrupt (IRQ) directly routed to the associated

processor complex. This may be used to restart the timer inside an interrupt handler in non-safety

critical applications.

If the expiration level is 2 or more, a high priority interrupt (FIQ) directly routed to the associated

processor complex. This interrupt can also be made visible to other processor by using a shared

interrupt line if supported by the specific TKE. In Android, the corresponding interrupt handler assumes

the system is in a bad state and captures some state information for a potential post mortem analysis.

The interrupt handler may not attempt to correct the problem.

If the expiration level is 3 or more, a normal interrupt (IRQ) routed to the LIC and from there routed to a

set of processors, this is meant to trigger system wide actions, in particular recovery actions of the

processor associated with the WDT. This is also known as a remote interrupt.

If the expiration level transitions from a value strictly below 4 to a value above or equal to 4, the WDT can assert a

system wide debug reset. When debug is allowed, this reset can be intercepted by debug logic, and specific actions

taken to preserve information about the state of the system before reset assertion clears them, allowing for post-

mortem debug analysis. In particular, DFD logic attempts to flush the processor caches and local memories to DRAM,

save processor state, and put the DRAM in self-refresh before allowing the reset to take effect. WDT and CAR logic

uses a four phase handshake to communicate the WDT debug reset request.

If the expiration level is 5, the WDT can assert a system wide reset, equivalent to a Power On Reset, this reset can

optionally include a PMIC power cycling depending on the configuration in PMC. This is the last safety net for

recovery purposes, attempting to bring the system to a working state without any specific attempt at preserving

information.

Each WDT signals an error to the Hardware Safety Manager (HSM) when its expiration level is greater or equal than

a programmable threshold.

The watchdog timer features are disabled by default for backwards compatibility.

The counter can only be optionally restarted in defined windows of time instead of at any time

The granularity of the window mechanism in Xavier has been improved from its predecessor.

The counter can only be optionally restarted or disabled using a Challenge/Response pair (also known as Question

/Answer, QA).

The windowing operation works like this:

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Optionally enabled, normal operation is windowless and the WDT can be restarted at any time.

When enabled, a restart of the timer is disabled:

for a programmable set of expiration levels. This is achieved by disabling writes to the COMMAND register

based on a bitmap of disallowed expiration levels.

when outside an allowed window as measured by the combination of expiration level and downcounter as

shown in the figure below

Figure 8.18 Fine-Grained WDT Windowing Mechanism

The Challenge/Response works like this:

Optionally enabled, normal operation does not use Challenge/Response, unlocking is done by writing using a known

fixed pattern to the unlock register address.

When enabled, a restart is achieved only after unlocking via a Challenge/Response. This replaces the simpler unlock

mechanism used at other times to protect against disabling the counter.

The Challenge is that an LFSR value, present in the Unlock register and reading the Unlock register, is mandatory as

the implementation is allowed to use the read to alter internal state.

The Response is the next value of the LFSR that needs to be written in the Unlock register.

The LFSR is (re)initialized with the value written to the Unlock register.

Note that this is equivalent to advancing the LFSR if the unlock was successful.

0 is an allowed value that can be used for testing, the successor of 0 is 0.

The LFSR uses the classic CRC-32 polynomial operating in shift right (reversed) direction, that is to say

the next value is calculated as LFSR = (LFSR >> 1) ^ ((LFSR & 0x1) ? 0xEDB88320 : 0).

When locked, the Command register cannot be written.

An incorrect restart attempt can optionally result in an immediate jump in the expiration level. This is normally

used to immediately trigger a reset condition when the WDT is used as a safety-critical WDT.

Xavier provides a sticky enable, making it impossible to disable the WDT.

There is a watchdog timer in the Always On partition, that AO WDT is only reset by an external hardware Power

On Reset. The AO WDT has the same structure as the TKE WDTs but with different wiring of some inputs and

outputs. WDT operation may also be suspended when one or more of the TKE clocks is suspended. This can

happen for a standard WDT during some low-power states where OSC is stopped; for example, AO WDT is

specifically present to continue working during these power states.

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There is also a mechanism to stop all WDTs, similar to the ability to stop all timers. The request comes on a

wire broadcast to all TKEs (and AOWDTs). Each WDT adds a configuration bit to allow/disallow stopping the

WDT. Allowed after reset but can be switched to disallow for safety use cases. Each WDT also includes a

status bit indicating if it is currently frozen.

Figure 8.19 Example Timeline for Watchdog Operation

Generic Timers

ARM Generic Timer (GT) architecture defines timers to be used by ARM CPUs. This architecture uses the

system wide timing reference called Timestamp System Counter (TSC) that increases at a constant rate. This

allows the Generic Timers inside a CPU cluster to operate correctly without reconfiguration when the CPU

frequency changes.

The ARM Generic Timer includes the following features:

Physical counter that contains the count value of the system-counter.

Virtual counter that indicates virtual time. The virtual counter contains the value of the physical counter minus a 64-bit

virtual offset.

Set of four timers per CPU:

Secure Physical Timer

Non-Secure Physical Timer

Hypervisor Timer

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Virtual Timer

Full details about the operation of the Generic Timers were introduced in different ARM documents and are now

part of the .

ARM Architecture Reference Manual

Cortex-A9 Timers

The Cortex-A9 complex inside the APE contains an instance of a Cortex-A9 timer block, including the following:

Global timer, a 64-bit incrementing counter

Per CPU core private timer, a 32-bit decrementing counter with optional prescaler

Per CPU core watchdog timer. It has the same structure as a private timer augmented with watchdog capabilities, and

can be used as a second private timer. The Cortex-A9 WDT reset request signal is not connected.

All these timers operate on the Cortex-A9 clock, making them difficult to use for real-time purposes when the

Cortex-A9 clock is subject to DVFS. The APE cluster includes a TKE (not affected by DVFS) and APE software

usually do not use at all the Cortex-A9 timers.

TSC Update Frequency

The recommended frequency is 31.25 MHz to match the GPU ptimer requirement for a power-of-2 period (in

nS).

TSC Update Frequency Starting from PLLP

The cardinality of the operands, Numerator (N) and Denominator (D), for the slave TSC rational divider in path 0

is dependent on the division performed in the CAR divider. The ratio is the product of the CAR divider ratio

times the rational divider ratio. At least a factor of two is mandatory, whereas the divide-by-2 case is preferred

but the by-4 case is also allowed.

Configurationd to Generate 31.25 MHz

CAR Divider CAR Frequency

(MHz)

CAR Frequency/31.25 MHz

CAR Period, also Induced Jitter (ns)

Ratio # of Bits (N,D)

2 204 (7,10) 4.902

4 102 (7,9) 9.804

The (N,D) of the table above are held in

CLK_RST_CONTROLLER_TSC_HS_SUPER_CLK_DIVIDER_0.SUPER_TSC_HS_DIV_DIVIDEND (N)

CLK_RST_CONTROLLER_TSC_HS_SUPER_CLK_DIVIDER_0.SUPER_TSC_HS_DIV_DIVISOR (D)

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See Clock Controller and Reset (CAR) chapter for details.

TSC Update Frequency Starting from OSC

The cardinality of the operands, for the slave TSC rational divider in path 1 Numerator (N) and Denominator (D),

is constrained by the required support for a set of possible OSC frequencies. The table below lists different

input frequencies OSC_DIV (OSC frequency, 38.4 MHz, divided by 1, 2, 3, and 4) and their corresponding

Rational Divider Parameters for the Update Frequency 31.25 MHz (F) that are calculated in the following steps:

Find K that is the minimum for F/K to be lower than the OSC_DIV frequency (38.4 MHz).

Calculate the ratio of (F/K) and OSC_DIV.

Table 8.18 TSC Rational Divider Parameters ((F/K) / OSC_Div) at 38.4 MHz OSC Frequency and 31.25

MHz (F) Update Frequency

OSC_Div (MHz) K F/K

(F/K) / OSC_Div

Ratio # of Bits (N,D)

9.6 (38.4 / 4) 4 7.8125 (10,10)

12.8 (38.4 / 3) 3 10.416 (10,10)

19.2 (38.4 / 2) 2 15.625 (10,10)

38.4 (38.4 / 1) 1 31.25 (10,10)

The (N,D) of the table above are held in

CLK_RST_CONTROLLER_TSC_ _SUPER_CLK_DIVIDER_0.SUPER_TSC_OSC_DIV_DIVIDEND (N)OSC

CLK_RST_CONTROLLER_TSC_OSC_SUPER_CLK_DIVIDER_0.SUPER_TSC_OSC_DIV_DIVISOR (D)

See Clock Controller and Reset (CAR) chapter for details.

Safety Mechanism

The following blocks support register parity and send the parity error signals to an error collator:

RTC

TSC

USEC

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The are all inside the Always-On cluster and share the the Always-On cluster error collator with similar modules.

The Always-On cluster error collator forwards an aggregated error signal to the Hardware Safety manager

(HSM).

All hardware watchdog timers also generate an error signal when their expiration level is above a programmed

threshold. This error signal is directly connected to the HSM without going through an error collator.

8.3.4 Programming Guidelines

The following subsection provides guidance on the exact usage of the registers, especially when the sequence

of accesses is important.

Context Save and Restore Across Power State Transitions

Power state transitions require the affected modules to be restarted after the power state transition, with SC7

entry/exit the most important power state transition. There are a few canonical ways to handle this:

Do nothing, the reset value of the register is correct.

Registers are restored to a statically defined value. The register does not need to be fully static, but the initial value

after the power state transition is not dependent on the previous history.

Registers are restored based on their (dynamic) state prior to the power state transition. This requires to save a

relevant context, normally in external memory, and later to use the saved context to restore registers. Note that

preserving the context can be done either:

During SC7 entry

When the register is modified, this may be required for registers that are not accessible to the SC7 exit

process, generally because the SC7 entry process does not have sufficient access rights.

This section provides guidance for the registers, in particular detailing all special cases where the software

sequence may be more complex than simply writing back the stored value, including:

Security aspects linked to the new security model.

Registers that are have special access rules like indirection or lockable.

Registers that require some adaptation between save and restore.

The SC7 restore proceeds in two steps to reduce the latency associated with power state transitions:

A small set of registers, including the SCR are restored first by a secure software process. This set should be small

for performance reason. Note that in many cases, the SCR have static values, so they do not require to be saved.

Most of the registers protected by the SCR, especially most of the TrustZone secure registers are ideally restored

later, while some unrelated non secure software processes may already be active before full restoration takes place.

This specific way of handling SC7 requires checking if the default value of registers presents a security

exposure. This section classifies the different registers in three categories:

R0: Registers that must be restored in the first step to avoid a security exposure.

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R1: Registers that may be restored in the first step for a fully clean solution. These registers must be so that

information leakage can be fully averted if context restoration proceeds in a specific sequence. However not following

the ideal sequence only allows non secure software to observe TrustZone events that otherwise would be hidden, but

without compromising security itself.

R2: Restored registers with no specific security requirements.

NR: Registers that don’t need to be restored

The tables below list the registers and the associated guidance and are extensions of the corresponding

summary tables.

Table 8.19 Guidance for SC7 Handling of ARM TSC Control Registers

CNTCR

NR In Always On partition, not affected by SC7.

CNTSR

CNTCV0

CNTCV1

CNTFID0

CNTFID1

CounterID4

CounterID{5:7}

CounterID{0:3}

CounterID{8:11}

Table 8.20 Guidance for SC7 Handling of ARM TSC Status Registers

CNTCV0

NR In Always On partition, not affected by SC7.

CNTCV1

CounterID4

CounterID{5:7}

CounterID{0:3}

CounterID{8:

11}

Table 8.21 Guidance for SC7 Handling of TSC Implementation Registers

MTSCACR

MTSCADR

MTSCANNR

MTSCANDR

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In Always On partition, not affected by SC7. Note however that a portion of the TSC logic

depends on OSC or PLLP being active, so there are specific requirements to handle SC7, but the

sequence depicted there does not impact the registers.

MTSCCNTCV0

MTSCCNTCV1

STSCCR

STSCRSR

STSCIR{0,1}

STSCSR

TSCDCR

TSCSCR

Table 8.22 Guidance for SC7 Handling of TSC CAR Registers

CSTSCR0 R0

These are marked R0 because it is assumed they provide the reference for (secure) time, and so

should probably restored quickly. There are no associated security requirements. The values

restored are static for a given platform, so not clear if this requires a saving step.

TSCDIVR0 R0

TSCDIVR1 R0

Table 8.23 Guidance for SC7 Handling of Common GTE Registers, when Outside of AO Partition

TECTRL{t} R2 Generic TimeStamp Engine Control

TETSCH{t} NR 24 MSBs of the TSC associated with a timestamped event

TETSCL{t} NR 32 LSBs of the TSC associated with a timestamped event

TECCV{t} NR Current captured value of bitmap for timestamped event

TEPVV{t} NR Previous captured value of bitmap for timestamped event

TESRC{t} NR Identifies the source of the timestamped event

TEENCV{t} NR Encoded version of TECV{t} and TEPV{t}, with explicit valid

TECMD{t} NR Command register, especially to pop the FIFO

TESTATUS{t} NR Status register

TESCR{t} R0 Access rights control register for timestamp engine {t}.

TEDSCR{t} R0 Specific security domain for disable bits for timestamp engine {t}.

Table 8.24 Guidance for SC7 Handling of per Slice GTE Registers, when Outside of AO Partition

TETEN{t}{s} R2

TETDN{t}{s} R1 If not restored in step 1, non-secure software can observe the timing and occurrence of secure

events. This can be avoided by restoring this register before enabling the event source. As only

observation is possible if the sequence above is not followed, security is not directly compromised,

allowing R1.

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Table 8.25 Guidance for SC7 Handling of RTC Registers

RTCCR

NR In Always On partition, not affected by SC7.

RTCBR

RTCSCR

RTCSSCR

RTCMCR

RTCSAR{0,1}

RTCMAR

RTCSCAR

RTCMCAR

RTCIER

RTCISR

RTCIVR

RTCFIR

RTCRSR

RTCDR

RTCSCR

AOWDTCR

AOWDTSR

AOWDTCMDR

AOWDTUR

AOWDTSCOR

AOWDTSCR

Table 8.26 Guidance for SC7 Handling of USEC Registers

USECCVR

NR In Always On partition, not affected by SC7.

USECCCR

USECCRSR

USECCFR

USECSCR

Table 8.27 Guidance for SC7 Handling of TKE Registers, when outside of AO partition

TKETSC{0,1} NR

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TKEUSEC NR

TKEOSC NR

TKECR R2

TKEIE{i} R2

TKEIV NR

TKEIR NR

TKESCR R0

TMRCR{t} R2

Restoring the state of a timer may require compensating for the amount of time the power state

consumed.

TMRSR{t} NR (but saved)

TMRCSSR{t} R2

TMRSCR{t} R0

WDTCR{w} R2 WDT cannot compensate for the amount of time the power of state consumed, they can only be

restarted from scratch.

WDTSR{w} NR

WDTCMDR{w} NR

WDTUR{w} NR

WDTSCOR{w} R2

WDTSCR{w} R0

Restoring a TKE timer needs to consider a few special cases when trying to compensate for the amount of time

consumed by the power state:

For a one off timer

The timer may have expired during the power state, the restore code can perform either of the following:

Insert an (fake) event into the handler.

Program the timer to its shortest possible duration, resulting in the raising of the corresponding interrupt

as usual.

If the timer has not expired, the compensation can be done by performing any of the following:

Restore without compensation, the timer is linked to the amount of time elapsed in the active state, not

real time.

Restore in absolute fashion, if the timer targets a known real time deadline, the timer delay can be

computed by target time minus current time. This has the advantage that errors don’t accumulate if the

timer is suspended multiple times. This requires to save the calculated expiration time, not the TMRSR

{T} itself.

Restore in relative fashion, calculate the timer delay as the timer value at SC7 entry minus the amount

of time consumed during SC7. This requires saving TMRSR{t}.PCV and to know the time spent in SC7.

Note that the TMRSR{t}.PCV value is restored on a calculated value not the saved value itself.

For a periodic timer:

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The timer may have expired a number of times during the power state. Then, it may need to insert

corresponding (fake) events into the handler.

A timer cannot be restarted at a value different than its period. Then the restore may need to proceed in two

phases if the phase of the timer is important.

Restart the timer as a one off for the remainder of the period, using the same time of calculation for one-

off timer.

At the first expiration after the power state transition, restarts the timer in periodic mode.

If the phase of the periodic timer is not important, but only its period, then simply restart it immediately.

A final requirement is to assert/deassert the reset to terminal nodes located in a power-gated partition if the

reset is software controlled.

8.3.5 Timer Registers

Refer to "Reading Register Tables" in the Introduction chapter for the register table protocol as well as

recommendations for accessing registers.

The register descriptions below give the offset of each register within the Timers' address range. The Base

Addresses of these registers are specified in the Address Map section of the Xavier TRM.

Timer Keeping Element Shared Registers

TKE_AON_SHARED_TKETSC0_0

Value of Local TSC counter, synchronized across SOC

Offset: 0x0

Read/Write: RO

Parity Protection: N

SCR Protection: TKESCR_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

CV:

Current value of TSC, TSC[31:0]

TKE_AON_SHARED_TKETSC1_0

Value of Master TSC counter, synchronized across SOC

Offset: 0x4

Read/Write: RO

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Parity Protection: N

SCR Protection: TKESCR_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 CV:

8h0 followed by Master TSC[55:32]

TKE_AON_SHARED_TKEUSEC_0

Value of Local USEC counter, not synchronized across SOC

Offset: 0x8

Read/Write: RO

Parity Protection: N

SCR Protection: TKESCR_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 CV:

Current value of microsecond counter

TKE_AON_SHARED_TKEOSC_0

Value of Local OSC counter, not synchronized across SOC

Offset: 0xc

Read/Write: RO

Parity Protection: N

SCR Protection: TKESCR_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

CV:

Current value of osccilator counter

TKE_AON_SHARED_TKECR_0

TKE Control register

Offset: 0x10

Read/Write: R/W

Parity Protection: N

SCR Protection: TKESCR_0

Reset: 0x00000000 (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,0000)

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Bit Reset Description

3 0x0

HDBG:

Halt-on-debug. Controls whether a Halt-on-debug signal halts TKE logic

0: TKE ignores Halt-on-debug.

1: Asserted Halt-on-debug signal halts TKE logic, by disabling the update of the reference counters and

reference timing signals for all timers and all WDTs

2 0x0 OSC_DIS:

Disable the local OSC counter - Can be used to decrease the power consumption if OSC is not required

either by HW as a reference clock or by SW

1 0x0

USEC_DIS:

Disable the local USEC counter - Can be used to decrease the power consumption if usec is not required

either by HW as a reference clock or by SW

0 0x0 TSC_DIS:

Disable the local TSC - Can be used to decrease the power consumption if TSC is not required either by HW

as a reference clock or by SW

TKE_AON_SHARED_CLK_OVR_ON_0

Offset: 0x14

Read/Write: R/W

Parity Protection: N

SCR Protection: TKESCR_0

Reset: 0x00000000 (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxx0)

Bit Reset Description

0 0x0

OSC:

SLCG override bit

= DISABLE0

= ENABLE1

====================================================

Time Keeping Element: NV_Timers Master Spec

====================================================

TKE_AON_TIMER_TMR0_TMRCR_0

TMRCR{t} BT + P*{t} + 0 Timer Configuration Register

TMRSR{t} BT + P*{t} + 4 Timer Status Register

TMRCSSR{t} BT + P*{t} + 8 Timer Clock Source Selection Register

TMRATR{t} BT + P*{t} + 12 Timer Absolute Target Register

Timer Configuration Register

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Offset: 0x10000

Read/Write: R/W

Parity Protection: N

SCR Protection: TMRSCR0_0

Reset: 0x40000000 (0b01x0,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31 0x0 EN:

Enable, when set, enables the countdown process.

30 0x1

PER:

Periodic, when set, the internal counter is automatically reloaded after reaching 0

28:0 0x0

PTV:

Timer Present Trigger Value. When TMRCR is written and EN is 1b, the internal counter

is loaded with PTV+1 and starts counting down at each timing reference pulse. An interrupt

is set when the internal counter reaches 0. Note that writing TMRCR with EN=1 while

EN was already 1 restarts the counter.

Once the timer is started, TARGET can be used to either

- observe the value of the reference counter when the next interrupt is generated (read)

- select the exact reference counter value at which the next interrupt is generated (write)

TKE_AON_TIMER_TMR0_TMRSR_0

Timer Status Register

Offset: 0x10004

Read/Write: See table below

Parity Protection: N

SCR Protection: TMRSCR0_0

Reset: 0x00000000 (0bx0x0,0000,0000,0000,0000,0000,0000,0000)

Bit R/W Reset Description

30 RW 0x0 INTR_CLR:

Clears the interrupt when written as 1b, read always returns 0

28:0 RO 0x0 PCV:

Current counter value, writing to this field has no effect

TKE_AON_TIMER_TMR0_TMRCSSR_0

Timer Clock Source Selection Register

Offset: 0x10008

Read/Write: R/W

Parity Protection: N

SCR Protection: TMRSCR0_0

Reset: 0x00000000 (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xx00)

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Bit Reset Description

1:0 0x0

SRC_ID:

Select Count reference

2'b11 - TSC [41:12]

2'b10 - TSC [29:0]

2'b01 - oscCnt [29:0]

2'b00 - usecCnt [29:0]

The implementation of each timer uses comparison against counters incrementing

at the selected rate.

= SRC_USECCNT0

= SRC_OSCCNT1

= SRC_TSCCNT_29_02

= SRC_TSCCNT_41_123

TKE_AON_TIMER_TMR0_TMRATR_0

Timer Absolute Target Register

Offset: 0x1000c

Read/Write: R/W

Parity Protection: N

SCR Protection: TMRSCR0_0

Reset: 0x00000000 (0bxx00,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

29:0 0x0 TARGET:

Target value of the selected reference counter, i.e. when value of the selected reference

equals target value, the interrupt is generated. The difference between TARGET and the

current value must be positive when interpreting TARGET and the 29 LSB of the selected

reference counter as signed integers, otherwise the interrupt triggers immediately.

TKE_AON_TIMER_TMR1_TMRCR_0

TMRCR{t} BT + P*{t} + 0 Timer Configuration Register

TMRSR{t} BT + P*{t} + 4 Timer Status Register

TMRCSSR{t} BT + P*{t} + 8 Timer Clock Source Selection Register

TMRATR{t} BT + P*{t} + 12 Timer Absolute Target Register

Timer Configuration Register

Offset: 0x20000

Read/Write: R/W

Parity Protection: N

SCR Protection: TMRSCR1_0

Reset: 0x40000000 (0b01x0,0000,0000,0000,0000,0000,0000,0000)

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Bit Reset Description

31 0x0 EN:

Enable, when set, enables the countdown process.

30 0x1 PER:

Periodic, when set, the internal counter is automatically reloaded after reaching 0

28:0 0x0 PTV:

Timer Present Trigger Value. When TMRCR is written and EN is 1b, the internal counter

is loaded with PTV+1 and starts counting down at each timing reference pulse. An interrupt

is set when the internal counter reaches 0. Note that writing TMRCR with EN=1 while

EN was already 1 restarts the counter.

Once the timer is started, TARGET can be used to either

- observe the value of the reference counter when the next interrupt is generated (read)

- select the exact reference counter value at which the next interrupt is generated (write)

TKE_AON_TIMER_TMR1_TMRSR_0

Timer Status Register

Offset: 0x20004

Read/Write: See table below

Parity Protection: N

SCR Protection: TMRSCR1_0

Reset: 0x00000000 (0bx0x0,0000,0000,0000,0000,0000,0000,0000)

Bit R/W Reset Description

30 RW 0x0 INTR_CLR:

Clears the interrupt when written as 1b, read always returns 0

28:0 RO 0x0 PCV:

Current counter value, writing to this field has no effect

TKE_AON_TIMER_TMR1_TMRCSSR_0

Timer Clock Source Selection Register

Offset: 0x20008

Read/Write: R/W

Parity Protection: N

SCR Protection: TMRSCR1_0

Reset: 0x00000000 (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xx00)

Bit Reset Description

1:0

0x0

SRC_ID:

Select Count reference

2'b11 - TSC [41:12]

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Bit Reset Description

2'b10 - TSC [29:0]

2'b01 - oscCnt [29:0]

2'b00 - usecCnt [29:0]

The implementation of each timer uses comparison against counters incrementing

at the selected rate.

= SRC_USECCNT0

= SRC_OSCCNT1

= SRC_TSCCNT_29_02

= SRC_TSCCNT_41_123

TKE_AON_TIMER_TMR1_TMRATR_0

Timer Absolute Target Register

Offset: 0x2000c

Read/Write: R/W

Parity Protection: N

SCR Protection: TMRSCR1_0

Reset: 0x00000000 (0bxx00,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

29:0 0x0 TARGET:

Target value of the selected reference counter, i.e. when value of the selected reference

equals target value, the interrupt is generated. The difference between TARGET and the

current value must be positive when interpreting TARGET and the 29 LSB of the selected

reference counter as signed integers, otherwise the interrupt triggers immediately.

TKE_AON_TIMER_TMR2_TMRCR_0

TMRCR{t} BT + P*{t} + 0 Timer Configuration Register

TMRSR{t} BT + P*{t} + 4 Timer Status Register

TMRCSSR{t} BT + P*{t} + 8 Timer Clock Source Selection Register

TMRATR{t} BT + P*{t} + 12 Timer Absolute Target Register

Timer Configuration Register

Offset: 0x30000

Read/Write: R/W

Parity Protection: N

SCR Protection: TMRSCR2_0

Reset: 0x40000000 (0b01x0,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

0x0

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Bit Reset Description

EN:

Enable, when set, enables the countdown process.

30 0x1

PER:

Periodic, when set, the internal counter is automatically reloaded after reaching 0

28:0 0x0

PTV:

Timer Present Trigger Value. When TMRCR is written and EN is 1b, the internal counter

is loaded with PTV+1 and starts counting down at each timing reference pulse. An interrupt

is set when the internal counter reaches 0. Note that writing TMRCR with EN=1 while

EN was already 1 restarts the counter.

Once the timer is started, TARGET can be used to either

- observe the value of the reference counter when the next interrupt is generated (read)

- select the exact reference counter value at which the next interrupt is generated (write)

TKE_AON_TIMER_TMR2_TMRSR_0

Timer Status Register

Offset: 0x30004

Read/Write: See table below

Parity Protection: N

SCR Protection: TMRSCR2_0

Reset: 0x00000000 (0bx0x0,0000,0000,0000,0000,0000,0000,0000)

Bit R/W Reset Description

30 RW 0x0 INTR_CLR:

Clears the interrupt when written as 1b, read always returns 0

28:0 RO 0x0 PCV:

Current counter value, writing to this field has no effect

TKE_AON_TIMER_TMR2_TMRCSSR_0

Timer Clock Source Selection Register

Offset: 0x30008

Read/Write: R/W

Parity Protection: N

SCR Protection: TMRSCR2_0

Reset: 0x00000000 (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xx00)

Bit Reset Description

1:0

0x0

SRC_ID:

Select Count reference

2'b11 - TSC [41:12]

2'b10 - TSC [29:0]

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Bit Reset Description

2'b01 - oscCnt [29:0]

2'b00 - usecCnt [29:0]

The implementation of each timer uses comparison against counters incrementing

at the selected rate.

= SRC_USECCNT0

= SRC_OSCCNT1

= SRC_TSCCNT_29_02

= SRC_TSCCNT_41_123

TKE_AON_TIMER_TMR2_TMRATR_0

Timer Absolute Target Register

Offset: 0x3000c

Read/Write: R/W

Parity Protection: N

SCR Protection: TMRSCR2_0

Reset: 0x00000000 (0bxx00,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

29:0 0x0

TARGET:

Target value of the selected reference counter, i.e. when value of the selected reference

equals target value, the interrupt is generated. The difference between TARGET and the

current value must be positive when interpreting TARGET and the 29 LSB of the selected

reference counter as signed integers, otherwise the interrupt triggers immediately.

TKE_AON_TIMER_TMR3_TMRCR_0

TMRCR{t} BT + P*{t} + 0 Timer Configuration Register

TMRSR{t} BT + P*{t} + 4 Timer Status Register

TMRCSSR{t} BT + P*{t} + 8 Timer Clock Source Selection Register

TMRATR{t} BT + P*{t} + 12 Timer Absolute Target Register

Timer Configuration Register

Offset: 0x40000

Read/Write: R/W

Parity Protection: N

SCR Protection: TMRSCR3_0

Reset: 0x40000000 (0b01x0,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31 0x0

EN:

Enable, when set, enables the countdown process.

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Bit Reset Description

30 0x1

PER:

Periodic, when set, the internal counter is automatically reloaded after reaching 0

28:0 0x0

PTV:

Timer Present Trigger Value. When TMRCR is written and EN is 1b, the internal counter

is loaded with PTV+1 and starts counting down at each timing reference pulse. An interrupt

is set when the internal counter reaches 0. Note that writing TMRCR with EN=1 while

EN was already 1 restarts the counter.

Once the timer is started, TARGET can be used to either

- observe the value of the reference counter when the next interrupt is generated (read)

- select the exact reference counter value at which the next interrupt is generated (write)

TKE_AON_TIMER_TMR3_TMRSR_0

Timer Status Register

Offset: 0x40004

Read/Write: See table below

Parity Protection: N

SCR Protection: TMRSCR3_0

Reset: 0x00000000 (0bx0x0,0000,0000,0000,0000,0000,0000,0000)

Bit R/W Reset Description

30 RW 0x0 INTR_CLR:

Clears the interrupt when written as 1b, read always returns 0

28:0 RO 0x0 PCV:

Current counter value, writing to this field has no effect

TKE_AON_TIMER_TMR3_TMRCSSR_0

Timer Clock Source Selection Register

Offset: 0x40008

Read/Write: R/W

Parity Protection: N

SCR Protection: TMRSCR3_0

Reset: 0x00000000 (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xx00)

Bit Reset Description

1:0

0x0

SRC_ID:

Select Count reference

2'b11 - TSC [41:12]

2'b10 - TSC [29:0]

2'b01 - oscCnt [29:0]

2'b00 - usecCnt [29:0]

The implementation of each timer uses comparison against counters incrementing

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Bit Reset Description

at the selected rate.

= SRC_USECCNT0

= SRC_OSCCNT1

= SRC_TSCCNT_29_02

= SRC_TSCCNT_41_123

TKE_AON_TIMER_TMR3_TMRATR_0

Timer Absolute Target Register

Offset: 0x4000c

Read/Write: R/W

Parity Protection: N

SCR Protection: TMRSCR3_0

Reset: 0x00000000 (0bxx00,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

29:0 0x0

TARGET:

Target value of the selected reference counter, i.e. when value of the selected reference

equals target value, the interrupt is generated. The difference between TARGET and the

current value must be positive when interpreting TARGET and the 29 LSB of the selected

reference counter as signed integers, otherwise the interrupt triggers immediately.

====================================================

Time Keeping Element: WatchDog Timers Master Spec

====================================================

TKE_AON_WDT0_WDTCR_0

WDTCR{w} BW + P*{w} + 0 RW Watchdog Timer Configuration Register

WDTSR{w} BW + P*{w} + 4 RO Watchdog Timer Status Register

WDTCMDR{w} BW + P*{w} + 8 WO Watchdog Timer Command Register

WDTUR{w} BW + P*{w} + 12 RW Watchdog Timer Unlock Register

Watchdog Timer Configuration Register

Offset: 0x50000

Read/Write: R/W

Parity Protection: N

SCR Protection: WDTSCR0_0

Reset: 0x00700000 (0b0000,xx00,0111,0000,0000,0000,0000,0000)

Bit Reset Description

31:28

0x0

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Bit Reset Description

WindowedRestartDisableMap:

When WindowedOperationEnable is 1b, restart commands attempted when expiration level has value b are

rejected

if bit b equals 1b in this field

25 0x0 DisallowWDTFreeze:

When 1b, the signal watchdog_freeze_request has no effect

When 0b, when the signal watchdog_freeze_request is asserted, the WDT stops decrementing CurrentCount

if the WDT is enabled

24:23 0x0

RestartErrorAction:

If a restart action is attempted but fails, indicate which of 4 actions should be taken

0x0: do nothing, silently ignore the restart

0x1: immediately jump to expiration level 4 and reload the downcounter

0x2: immediately jump to expiration level 5 and reload the downcounter

0x3: immediately request a system power on reset

When jumping levels, the normal actions configured per level must take place

= NOP0

= JUMP_TO_41

= JUMP_TO_52

= POR_RESET3

22:20 0x7 ErrorThreshold:

The WDT logic asserts an error signal to HSM when ExpirationLevel >= ErrorThreshold.

19 0x0 TscReferenceEnable:

Select as timing reference transitions on a configured TSC bit.

18 0x0 ChallengeResponseEnable:

Enable the Challenge Response mode of operation. When 1b, the Unlock register operates as a Challenge

Response register.

17 0x0

WindowedOperationEnable:

Enable the windowed mode of operation. When 1b a restart command is rejected when the current expiration

level

is identified as disallowed in the WindowedRestartDisableMap or the current time is below the window

threshold.

The rejection is either silent or perform a reset based on RestartErrorAction

16 0x0

SystemPOResetEnable:

Enable internal full system reset at fifth expiration of the counter.

This reset cannot be intercepted and acts as a Power On Reset

15 0x0 SystemDebugResetEnable:

Enable system wide reset assertion at fourth expiration of the counter.

This reset can be intercepted by debug logic, e.g. to preserve information

14 0x0

RemoteInterruptEnable:

Enable normal priority interrupt assertion at third expiration of the counter,

connected to LIC for system wide visibility

0x0

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Bit Reset Description

LocalFIQEnable:

Enable high priority interrupt (FIQ) assertion at second expiration of the counter,

connected to local interrupt controller

12 0x0 LocalInterruptEnable:

Enable normal priority interrupt assertion at first expiration of the counter,

connected to local interrupt controller

11:4 0x0

Period:

Measured in periods of the timer selected as source, this is the reload value, so 0 is treated as maximum

period

3:0 0x0 TimerSource:

The timer source interpretation is dependent on the value of TscReferenceEnable:

TscReferenceEnable = 0b: timer<TimerSource> is the timing reference

TscReferenceEnable = 1b: a transition of TSC[2*TimerSource] is the timing reference

TKE_AON_WDT0_WDTSR_0

Watchdog Timer Status Register

Offset: 0x50004

Read/Write: RO

Parity Protection: N

SCR Protection: WDTSCR0_0

Reset: 0x00000000 (0bxxxx,xxxx,xxxx,0000,x000,0000,0000,0000)

Bit Reset Description

19 0x0 Frozen:

1b indicates that the WDT is frozen because of the assertion of the global WDT freeze request

(when allowed) or because of the assertion of the global timer freeze request

18 0x0

ErrorForced:

1b indicates that the error reported to HSM is forced active for testing purpose

17 0x0

StickyEnabled:

1b when the counter is enabled and cannot be disabled, set by StickyStart command, cleared by reset only.

16 0x0 CurrentError:

Current error reported to HSM, this is the output after combining the functional and forced error paths

14:12 0x0 CurrentExpirationCount:

Current count of expiration since last start operation, cleared by Start command, saturating at 5.

11:4 0x0 CurrentCount:

Current value of the downcounter, reloaded with Period by Start command.

3 0x0 RemoteInterruptStatus:

Current status of remote interrupt, cleared by Start command

2 0x0 LocalFIQStatus:

Current status of FIQ, cleared by Start command.

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Bit Reset Description

1 0x0

LocalInterruptStatus:

Current status of local interrupt, cleared by Start command.

0 0x0

Enabled:

1b when the counter is active. When Enabled is 1b, the configuration of the WDT is frozen by silently

ignoring write attempts to the configuration registers: WDTCR, WDTSCR and WDTFWCR. Set by Start or

StickyStart commands,

cleared by Disable when StickyEnabled is 0b.

TKE_AON_WDT0_WDTCMDR_0

Watchdog Timer Command Register

Offset: 0x50008

Read/Write: R/W

Parity Protection: N

SCR Protection: WDTSCR0_0

Reset: 0x00000000 (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,0000)

Bit Reset Description

3 0x0 ForceError:

Only working if the Command register is unlocked. 1b sets an internal flop that is ORED with the

functional error signal (based on threshold), 0b clears the bit. The state of the flop is shown

in the status register.

2 0x0

StickyStart:

Qualifies the StartCounter bit, if both bits are 1b, the counter is enabled in permanent fashion, i.e.

it remains enabled until the next reset, and a disable counter operation has no effect. Ignored if StartCounter

is 0b

1 0x0 DisableCounter:

Only working if the unlock register (WDTUR{w}) has been programmed before with the correct pattern.

Writing to the command register always clears the unlock register. If written to 1b, while StartCounter

is 0b and the unlock register contains the unlock pattern, the watchdog transitions back to disabled.

0 0x0 StartCounter:

When written to 1b, enable the counter operation,load the counter with Period and starts downcounting,

resets the expiration count to 0 and clears all status flags. Enabled is always 1b after this.

This is also used as Restart. Writing to StartCounter requires unlocking when ChallengeResponseEnable

is 1b, and writing to StartCounter is also restricted to windows of time given by WindowedRestartDisableMap

when WindowedOperationEnable is 1b.

TKE_AON_WDT0_WDTUR_0

Watchdog Timer Unlock Register

Offset: 0x5000c

Read/Write: R/W

Parity Protection: N

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SCR Protection: WDTSCR0_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

UnlockPattern:

The behavior of the Unlock pattern is dependent on the ChallengeResponseEnable configuration bit

When ChallengeResponseEnable is 0b, Unlock must be written with value 0x0000_C45A to allow a write to

DisableCounter to take effect. The UnlockPattern is reset at each write to the Command register.

When ChallengeResponseEnable is 1b, a write to the Command register is only allowed after reading the

Unlock pattern to get the current value of a LFSR, followed by writing the next value of the LFSR to the

UnlockPattern.

If the two values match, the unlock is successful, in all cases the LFSR gets (re)initialized with the written

value.

TKE_AON_WDT0_WDTSCR_0

Watchdog Timer Skip Configuration Register

Offset: 0x50010

Read/Write: R/W

Parity Protection: N

SCR Protection: WDTSCR0_0

Reset: 0x00000000 (0bxxxx,xxxx,xxxx,xxxx,x000,x000,x000,x000)

Bit Reset Description

14:12 0x0 Skip3:

Skip Value at Expiration count 3

At a Downcounter expiration, the expiration level changes as ExpC <= ExpC + 1 + Skip(ExpC), saturating at

10:8 0x0

Skip2:

Skip Value at Expiration count 2

6:4 0x0 Skip1:

Skip Value at Expiration count 1

2:0 0x0 Skip0:

Skip Value at Expiration count 0

TKE_AON_WDT0_WDTFWCR_0

Watchdog Timer Fine Window Configuration Register

Offset: 0x50014

Read/Write: R/W

Parity Protection: N

SCR Protection: WDTSCR0_0

Reset: 0x00000000 (0bxxxx,xxxx,xxxx,x000,xxxx,xxxx,0000,0000)

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Bit Reset Description

18:16 0x0 StartLevel:

If restart (i.e. start while WDT is already enabled) is attempted and windowing operation is enabled,

restart is rejected if current expiration < StartLevel

7:0 0x0

StartCount:

If restart (i.e. start while WDT is already enabled) is attempted and windowing operation is enabled and

current expiration level == StartLevel, restart is rejected if current downcounter > (Period - StartCount).

StartCount is the number of cycles where rejection takes place at the start of that level.

Time Keeping Element: TOP Registers

TKE_TOP_SHARED_TKETSC0_0

Value of Local TSC counter, synchronized across SOC

Offset: 0x0

Read/Write: RO

Parity Protection: N

SCR Protection: TKESCR_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 CV:

Current value of TSC, TSC[31:0]

TKE_TOP_SHARED_TKETSC1_0

Value of Master TSC counter, synchronized across SOC

Offset: 0x4

Read/Write: RO

Parity Protection: N

SCR Protection: TKESCR_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

CV:

8h0 followed by Master TSC[55:32]

TKE_TOP_SHARED_TKEUSEC_0

Value of Local USEC counter, not synchronized across SOC

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Offset: 0x8

Read/Write: RO

Parity Protection: N

SCR Protection: TKESCR_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 CV:

Current value of microsecond counter

TKE_TOP_SHARED_TKEOSC_0

Value of Local OSC counter, not synchronized across SOC

Offset: 0xc

Read/Write: RO

Parity Protection: N

SCR Protection: TKESCR_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

CV:

Current value of osccilator counter

TKE_TOP_SHARED_TKECR_0

TKE Control register

Offset: 0x10

Read/Write: R/W

Parity Protection: N

SCR Protection: TKESCR_0

Reset: 0x00000000 (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,0000)

Bit Reset Description

3 0x0

HDBG:

Halt-on-debug. Controls whether a Halt-on-debug signal halts TKE logic

0: TKE ignores Halt-on-debug.

1: Asserted Halt-on-debug signal halts TKE logic, by disabling the update of the reference counters and

reference timing signals for all timers and all WDTs

2 0x0 OSC_DIS:

Disable the local OSC counter - Can be used to decrease the power consumption if OSC is not required

either by HW as a reference clock or by SW

0x0

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Bit Reset Description

USEC_DIS:

Disable the local USEC counter - Can be used to decrease the power consumption if usec is not required

either by HW as a reference clock or by SW

0 0x0 TSC_DIS:

Disable the local TSC - Can be used to decrease the power consumption if TSC is not required either by HW

as a reference clock or by SW

TKE_TOP_SHARED_CLK_OVR_ON_0

Offset: 0x14

Read/Write: R/W

Parity Protection: N

SCR Protection: TKESCR_0

Reset: 0x00000000 (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxx0)

Bit Reset Description

0 0x0 OSC:

SLCG override bit

= DISABLE0

= ENABLE1

TKE_TOP_SHARED_TKEIE0_0

================================================================================================

Optional, controls the routing of shared interrupt {i}: 0 to 9

BITMAPPING:

15:0 of register TKEIE{i} = Timer Single Interrupt, for Timers 15 - 0.

18:16 of register TKEIE{i} = Watch-Dog Timer 0 internal interrupt status

19:19 of register TKEIE{i} = Reserved

22:20 of register TKEIE{i} = Watch-Dog Timer 1 internal interrupt status

23:23 of register TKEIE{i} = Reserved

26:24 of register TKEIE{i} = Watch-Dog Timer 2 internal interrupt status

27:27 of register TKEIE{i} = Reserved

30:28 of register TKEIE{i} = Watch-Dog Timer 3 internal interrupt status

31:31 of register TKEIE{i} = Reserved

================================================================================================

Offset: 0x100

Read/Write: R/W

Parity Protection: N

SCR Protection: TKESCR_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

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Bit Reset Description

31:0 0x0 EnableMap:

TKE_TOP_SHARED_TKEIE1_0

Offset: 0x104

Read/Write: R/W

Parity Protection: N

SCR Protection: TKESCR_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

EnableMap:

TKE_TOP_SHARED_TKEIE2_0

Offset: 0x108

Read/Write: R/W

Parity Protection: N

SCR Protection: TKESCR_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

EnableMap:

TKE_TOP_SHARED_TKEIE3_0

Offset: 0x10c

Read/Write: R/W

Parity Protection: N

SCR Protection: TKESCR_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

EnableMap:

TKE_TOP_SHARED_TKEIE4_0

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Offset: 0x110

Read/Write: R/W

Parity Protection: N

SCR Protection: TKESCR_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 EnableMap:

TKE_TOP_SHARED_TKEIE5_0

Offset: 0x114

Read/Write: R/W

Parity Protection: N

SCR Protection: TKESCR_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

EnableMap:

TKE_TOP_SHARED_TKEIE6_0

Offset: 0x118

Read/Write: R/W

Parity Protection: N

SCR Protection: TKESCR_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

EnableMap:

TKE_TOP_SHARED_TKEIE7_0

Offset: 0x11c

Read/Write: R/W

Parity Protection: N

SCR Protection: TKESCR_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

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Bit Reset Description

31:0 0x0 EnableMap:

TKE_TOP_SHARED_TKEIE8_0

Offset: 0x120

Read/Write: R/W

Parity Protection: N

SCR Protection: TKESCR_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 EnableMap:

TKE_TOP_SHARED_TKEIE9_0

Offset: 0x124

Read/Write: R/W

Parity Protection: N

SCR Protection: TKESCR_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

EnableMap:

TKE_TOP_SHARED_TKEIV_0

==================================================================

Indicates which shared interrupts are currently asserted

BITMAPPING:

0:0 - Current Status of external interrupt 0

1:1 - Current Status of external interrupt 1

2:2 - Current Status of external interrupt 2

3:3 - Current Status of external interrupt 3

4:4 - Current Status of external interrupt 4

5:5 - Current Status of external interrupt 5

6:6 - Current Status of external interrupt 6

7:7 - Current Status of external interrupt 7

8:8 - Current Status of external interrupt 8

9:9 - Current Status of external interrupt 9

==================================================================

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Offset: 0x200

Read/Write: RO

Parity Protection: N

SCR Protection: TKESCR_0

Reset: 0x00000000 (0bxxxx,xxxx,xxxx,xxxx,xxxx,xx00,0000,0000)

Bit Reset Description

9:0 0x0

ValidMap:

Currently enabled interrupts

TKE_TOP_SHARED_TKEIR_0

Which internal interrupts are currently asserted, before applying the TKEIE masks?

Offset: 0x204

Read/Write: RO

Parity Protection: N

SCR Protection: TKESCR_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 RawMap:

Currently asserted internal interrupts

The mapping of the Internal Interrupts is defined as follows:

Bits[00 + [nT-1:0]] are the interrupts of the nT instantiated timers

Bits[16 + {w} * 4 + [2:0]] are the sets of three interrupts of the nW instantiated watchdog timers

====================================================

Time Keeping Element: NV_Timers Master Spec

====================================================

TKE_TOP_TIMER_TMR0_TMRCR_0

TMRCR{t} BT + P*{t} + 0 Timer Configuration Register

TMRSR{t} BT + P*{t} + 4 Timer Status Register

TMRCSSR{t} BT + P*{t} + 8 Timer Clock Source Selection Register

TMRATR{t} BT + P*{t} + 12 Timer Absolute Target Register

Timer Configuration Register

Offset: 0x10000

Read/Write: R/W

Parity Protection: N

SCR Protection: TMRSCR0_0

Reset: 0x40000000 (0b01x0,0000,0000,0000,0000,0000,0000,0000)

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Bit Reset Description

31 0x0 EN:

Enable, when set, enables the countdown process.

30 0x1 PER:

Periodic, when set, the internal counter is automatically reloaded after reaching 0

28:0 0x0 PTV:

Timer Present Trigger Value. When TMRCR is written and EN is 1b, the internal counter

is loaded with PTV+1 and starts counting down at each timing reference pulse. An interrupt

is set when the internal counter reaches 0. Note that writing TMRCR with EN=1 while

EN was already 1 restarts the counter.

Once the timer is started, TARGET can be used to either

- observe the value of the reference counter when the next interrupt will be generated (read)

- select the exact reference counter value at which the next interrupt will be generated (write)

TKE_TOP_TIMER_TMR0_TMRSR_0

Timer Status Register

Offset: 0x10004

Read/Write: See table below

Parity Protection: N

SCR Protection: TMRSCR0_0

Reset: 0x00000000 (0bx0x0,0000,0000,0000,0000,0000,0000,0000)

Bit R/W Reset Description

30 RW 0x0

INTR_CLR:

Clears the interrupt when written as 1b, read always returns 0

28:0 RO 0x0 PCV:

Current counter value, writing to this field has no effect

TKE_TOP_TIMER_TMR0_TMRCSSR_0

Timer Clock Source Selection Register

Offset: 0x10008

Read/Write: R/W

Parity Protection: N

SCR Protection: TMRSCR0_0

Reset: 0x00000000 (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xx00)

Bit Reset Description

1:0

0x0

SRC_ID:

Select Count reference

2'b11 - TSC [41:12]

2'b10 - TSC [29:0]

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Bit Reset Description

2'b01 - oscCnt [29:0]

2'b00 - usecCnt [29:0]

The implementation of each timer uses comparison against counters incrementing

at the selected rate.

= SRC_USECCNT0

= SRC_OSCCNT1

= SRC_TSCCNT_29_02

= SRC_TSCCNT_41_123

TKE_TOP_TIMER_TMR0_TMRATR_0

Timer Absolute Target Register

Offset: 0x1000c

Read/Write: R/W

Parity Protection: N

SCR Protection: TMRSCR0_0

Reset: 0x00000000 (0bxx00,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

29:0 0x0 TARGET:

Target value of the selected reference counter, i.e. when value of the selected reference

equals target value, the interrupt is generated. The difference between TARGET and the

current value must be positive when interpreting TARGET and the 29 LSB of the selected

reference counter as signed integers, otherwise the interrupt triggers immediately.

TKE_TOP_TIMER_TMR1_TMRCR_0

TMRCR{t} BT + P*{t} + 0 Timer Configuration Register

TMRSR{t} BT + P*{t} + 4 Timer Status Register

TMRCSSR{t} BT + P*{t} + 8 Timer Clock Source Selection Register

TMRATR{t} BT + P*{t} + 12 Timer Absolute Target Register

Timer Configuration Register

Offset: 0x20000

Read/Write: R/W

Parity Protection: N

SCR Protection: TMRSCR1_0

Reset: 0x40000000 (0b01x0,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

0x0

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Bit Reset Description

EN:

Enable, when set, enables the countdown process.

30 0x1 PER:

Periodic, when set, the internal counter is automatically reloaded after reaching 0

28:0 0x0 PTV:

Timer Present Trigger Value. When TMRCR is written and EN is 1b, the internal counter

is loaded with PTV+1 and starts counting down at each timing reference pulse. An interrupt

is set when the internal counter reaches 0. Note that writing TMRCR with EN=1 while

EN was already 1 restarts the counter.

Once the timer is started, TARGET can be used to either

- observe the value of the reference counter when the next interrupt will be generated (read)

- select the exact reference counter value at which the next interrupt will be generated (write)

TKE_TOP_TIMER_TMR1_TMRSR_0

Timer Status Register

Offset: 0x20004

Read/Write: See table below

Parity Protection: N

SCR Protection: TMRSCR1_0

Reset: 0x00000000 (0bx0x0,0000,0000,0000,0000,0000,0000,0000)

Bit R/W Reset Description

30 RW 0x0

INTR_CLR:

Clears the interrupt when written as 1b, read always returns 0

28:0 RO 0x0

PCV:

Current counter value, writing to this field has no effect

TKE_TOP_TIMER_TMR1_TMRCSSR_0

Timer Clock Source Selection Register

Offset: 0x20008

Read/Write: R/W

Parity Protection: N

SCR Protection: TMRSCR1_0

Reset: 0x00000000 (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xx00)

Bit Reset Description

1:0

0x0

SRC_ID:

Select Count reference

2'b11 - TSC [41:12]

2'b10 - TSC [29:0]

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Bit Reset Description

2'b01 - oscCnt [29:0]

2'b00 - usecCnt [29:0]

The implementation of each timer uses comparison against counters incrementing

at the selected rate.

= SRC_USECCNT0

= SRC_OSCCNT1

= SRC_TSCCNT_29_02

= SRC_TSCCNT_41_123

TKE_TOP_TIMER_TMR1_TMRATR_0

Timer Absolute Target Register

Offset: 0x2000c

Read/Write: R/W

Parity Protection: N

SCR Protection: TMRSCR1_0

Reset: 0x00000000 (0bxx00,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

29:0 0x0 TARGET:

Target value of the selected reference counter, i.e. when value of the selected reference

equals target value, the interrupt is generated. The difference between TARGET and the

current value must be positive when interpreting TARGET and the 29 LSB of the selected

reference counter as signed integers, otherwise the interrupt triggers immediately.

TKE_TOP_TIMER_TMR2_TMRCR_0

TMRCR{t} BT + P*{t} + 0 Timer Configuration Register

TMRSR{t} BT + P*{t} + 4 Timer Status Register

TMRCSSR{t} BT + P*{t} + 8 Timer Clock Source Selection Register

TMRATR{t} BT + P*{t} + 12 Timer Absolute Target Register

Timer Configuration Register

Offset: 0x30000

Read/Write: R/W

Parity Protection: N

SCR Protection: TMRSCR2_0

Reset: 0x40000000 (0b01x0,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

0x0

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Bit Reset Description

EN:

Enable, when set, enables the countdown process.

30 0x1 PER:

Periodic, when set, the internal counter is automatically reloaded after reaching 0

28:0 0x0 PTV:

Timer Present Trigger Value. When TMRCR is written and EN is 1b, the internal counter

is loaded with PTV+1 and starts counting down at each timing reference pulse. An interrupt

is set when the internal counter reaches 0. Note that writing TMRCR with EN=1 while

EN was already 1 restarts the counter.

Once the timer is started, TARGET can be used to either

- observe the value of the reference counter when the next interrupt will be generated (read)

- select the exact reference counter value at which the next interrupt will be generated (write)

TKE_TOP_TIMER_TMR2_TMRSR_0

Timer Status Register

Offset: 0x30004

Read/Write: See table below

Parity Protection: N

SCR Protection: TMRSCR2_0

Reset: 0x00000000 (0bx0x0,0000,0000,0000,0000,0000,0000,0000)

Bit R/W Reset Description

30 RW 0x0 INTR_CLR:

Clears the interrupt when written as 1b, read always returns 0

28:0 RO 0x0

PCV:

Current counter value, writing to this field has no effect

TKE_TOP_TIMER_TMR2_TMRCSSR_0

Timer Clock Source Selection Register

Offset: 0x30008

Read/Write: R/W

Parity Protection: N

SCR Protection: TMRSCR2_0

Reset: 0x00000000 (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xx00)

Bit Reset Description

1:0

0x0

SRC_ID:

Select Count reference

2'b11 - TSC [41:12]

2'b10 - TSC [29:0]

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Bit Reset Description

2'b01 - oscCnt [29:0]

2'b00 - usecCnt [29:0]

The implementation of each timer uses comparison against counters incrementing

at the selected rate.

= SRC_USECCNT0

= SRC_OSCCNT1

= SRC_TSCCNT_29_02

= SRC_TSCCNT_41_123

TKE_TOP_TIMER_TMR2_TMRATR_0

Timer Absolute Target Register

Offset: 0x3000c

Read/Write: R/W

Parity Protection: N

SCR Protection: TMRSCR2_0

Reset: 0x00000000 (0bxx00,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

29:0 0x0 TARGET:

Target value of the selected reference counter, i.e. when value of the selected reference

equals target value, the interrupt is generated. The difference between TARGET and the

current value must be positive when interpreting TARGET and the 29 LSB of the selected

reference counter as signed integers, otherwise the interrupt triggers immediately.

TKE_TOP_TIMER_TMR3_TMRCR_0

TMRCR{t} BT + P*{t} + 0 Timer Configuration Register

TMRSR{t} BT + P*{t} + 4 Timer Status Register

TMRCSSR{t} BT + P*{t} + 8 Timer Clock Source Selection Register

TMRATR{t} BT + P*{t} + 12 Timer Absolute Target Register

Timer Configuration Register

Offset: 0x40000

Read/Write: R/W

Parity Protection: N

SCR Protection: TMRSCR3_0

Reset: 0x40000000 (0b01x0,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

0x0

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Bit Reset Description

EN:

Enable, when set, enables the countdown process.

30 0x1 PER:

Periodic, when set, the internal counter is automatically reloaded after reaching 0

28:0 0x0 PTV:

Timer Present Trigger Value. When TMRCR is written and EN is 1b, the internal counter

is loaded with PTV+1 and starts counting down at each timing reference pulse. An interrupt

is set when the internal counter reaches 0. Note that writing TMRCR with EN=1 while

EN was already 1 restarts the counter.

Once the timer is started, TARGET can be used to either

- observe the value of the reference counter when the next interrupt will be generated (read)

- select the exact reference counter value at which the next interrupt will be generated (write)

TKE_TOP_TIMER_TMR3_TMRSR_0

Timer Status Register

Offset: 0x40004

Read/Write: See table below

Parity Protection: N

SCR Protection: TMRSCR3_0

Reset: 0x00000000 (0bx0x0,0000,0000,0000,0000,0000,0000,0000)

Bit R/W Reset Description

30 RW 0x0

INTR_CLR:

Clears the interrupt when written as 1b, read always returns 0

28:0 RO 0x0

PCV:

Current counter value, writing to this field has no effect

TKE_TOP_TIMER_TMR3_TMRCSSR_0

Timer Clock Source Selection Register

Offset: 0x40008

Read/Write: R/W

Parity Protection: N

SCR Protection: TMRSCR3_0

Reset: 0x00000000 (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xx00)

Bit Reset Description

1:0

0x0

SRC_ID:

Select Count reference

2'b11 - TSC [41:12]

2'b10 - TSC [29:0]

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Bit Reset Description

2'b01 - oscCnt [29:0]

2'b00 - usecCnt [29:0]

The implementation of each timer uses comparison against counters incrementing

at the selected rate.

= SRC_USECCNT0

= SRC_OSCCNT1

= SRC_TSCCNT_29_02

= SRC_TSCCNT_41_123

TKE_TOP_TIMER_TMR3_TMRATR_0

Timer Absolute Target Register

Offset: 0x4000c

Read/Write: R/W

Parity Protection: N

SCR Protection: TMRSCR3_0

Reset: 0x00000000 (0bxx00,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

29:0 0x0 TARGET:

Target value of the selected reference counter, i.e. when value of the selected reference

equals target value, the interrupt is generated. The difference between TARGET and the

current value must be positive when interpreting TARGET and the 29 LSB of the selected

reference counter as signed integers, otherwise the interrupt triggers immediately.

TKE_TOP_TIMER_TMR4_TMRCR_0

TMRCR{t} BT + P*{t} + 0 Timer Configuration Register

TMRSR{t} BT + P*{t} + 4 Timer Status Register

TMRCSSR{t} BT + P*{t} + 8 Timer Clock Source Selection Register

TMRATR{t} BT + P*{t} + 12 Timer Absolute Target Register

Timer Configuration Register

Offset: 0x50000

Read/Write: R/W

Parity Protection: N

SCR Protection: TMRSCR4_0

Reset: 0x40000000 (0b01x0,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

0x0

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Bit Reset Description

EN:

Enable, when set, enables the countdown process.

30 0x1 PER:

Periodic, when set, the internal counter is automatically reloaded after reaching 0

28:0 0x0 PTV:

Timer Present Trigger Value. When TMRCR is written and EN is 1b, the internal counter

is loaded with PTV+1 and starts counting down at each timing reference pulse. An interrupt

is set when the internal counter reaches 0. Note that writing TMRCR with EN=1 while

EN was already 1 restarts the counter.

Once the timer is started, TARGET can be used to either

- observe the value of the reference counter when the next interrupt will be generated (read)

- select the exact reference counter value at which the next interrupt will be generated (write)

TKE_TOP_TIMER_TMR4_TMRSR_0

Timer Status Register

Offset: 0x50004

Read/Write: See table below

Parity Protection: N

SCR Protection: TMRSCR4_0

Reset: 0x00000000 (0bx0x0,0000,0000,0000,0000,0000,0000,0000)

Bit R/W Reset Description

30 RW 0x0 INTR_CLR:

Clears the interrupt when written as 1b, read always returns 0

28:0 RO 0x0

PCV:

Current counter value, writing to this field has no effect

TKE_TOP_TIMER_TMR4_TMRCSSR_0

Timer Clock Source Selection Register

Offset: 0x50008

Read/Write: R/W

Parity Protection: N

SCR Protection: TMRSCR4_0

Reset: 0x00000000 (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xx00)

Bit Reset Description

1:0

0x0

SRC_ID:

Select Count reference

2'b11 - TSC [41:12]

2'b10 - TSC [29:0]

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Bit Reset Description

2'b01 - oscCnt [29:0]

2'b00 - usecCnt [29:0]

The implementation of each timer uses comparison against counters incrementing

at the selected rate.

= SRC_USECCNT0

= SRC_OSCCNT1

= SRC_TSCCNT_29_02

= SRC_TSCCNT_41_123

TKE_TOP_TIMER_TMR4_TMRATR_0

Timer Absolute Target Register

Offset: 0x5000c

Read/Write: R/W

Parity Protection: N

SCR Protection: TMRSCR4_0

Reset: 0x00000000 (0bxx00,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

29:0 0x0 TARGET:

Target value of the selected reference counter, i.e. when value of the selected reference

equals target value, the interrupt is generated. The difference between TARGET and the

current value must be positive when interpreting TARGET and the 29 LSB of the selected

reference counter as signed integers, otherwise the interrupt triggers immediately.

TKE_TOP_TIMER_TMR5_TMRCR_0

TMRCR{t} BT + P*{t} + 0 Timer Configuration Register

TMRSR{t} BT + P*{t} + 4 Timer Status Register

TMRCSSR{t} BT + P*{t} + 8 Timer Clock Source Selection Register

TMRATR{t} BT + P*{t} + 12 Timer Absolute Target Register

Timer Configuration Register

Offset: 0x60000

Read/Write: R/W

Parity Protection: N

SCR Protection: TMRSCR5_0

Reset: 0x40000000 (0b01x0,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

0x0

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Bit Reset Description

EN:

Enable, when set, enables the countdown process.

30 0x1 PER:

Periodic, when set, the internal counter is automatically reloaded after reaching 0

28:0 0x0 PTV:

Timer Present Trigger Value. When TMRCR is written and EN is 1b, the internal counter

is loaded with PTV+1 and starts counting down at each timing reference pulse. An interrupt

is set when the internal counter reaches 0. Note that writing TMRCR with EN=1 while

EN was already 1 restarts the counter.

Once the timer is started, TARGET can be used to either

- observe the value of the reference counter when the next interrupt will be generated (read)

- select the exact reference counter value at which the next interrupt will be generated (write)

TKE_TOP_TIMER_TMR5_TMRSR_0

Timer Status Register

Offset: 0x60004

Read/Write: See table below

Parity Protection: N

SCR Protection: TMRSCR5_0

Reset: 0x00000000 (0bx0x0,0000,0000,0000,0000,0000,0000,0000)

Bit R/W Reset Description

30 RW 0x0

INTR_CLR:

Clears the interrupt when written as 1b, read always returns 0

28:0 RO 0x0

PCV:

Current counter value, writing to this field has no effect

TKE_TOP_TIMER_TMR5_TMRCSSR_0

Timer Clock Source Selection Register

Offset: 0x60008

Read/Write: R/W

Parity Protection: N

SCR Protection: TMRSCR5_0

Reset: 0x00000000 (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xx00)

Bit Reset Description

1:0

0x0

SRC_ID:

Select Count reference

2'b11 - TSC [41:12]

2'b10 - TSC [29:0]

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Bit Reset Description

2'b01 - oscCnt [29:0]

2'b00 - usecCnt [29:0]

The implementation of each timer uses comparison against counters incrementing

at the selected rate.

= SRC_USECCNT0

= SRC_OSCCNT1

= SRC_TSCCNT_29_02

= SRC_TSCCNT_41_123

TKE_TOP_TIMER_TMR5_TMRATR_0

Timer Absolute Target Register

Offset: 0x6000c

Read/Write: R/W

Parity Protection: N

SCR Protection: TMRSCR5_0

Reset: 0x00000000 (0bxx00,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

29:0 0x0 TARGET:

Target value of the selected reference counter, i.e. when value of the selected reference

equals target value, the interrupt is generated. The difference between TARGET and the

current value must be positive when interpreting TARGET and the 29 LSB of the selected

reference counter as signed integers, otherwise the interrupt triggers immediately.

TKE_TOP_TIMER_TMR6_TMRCR_0

TMRCR{t} BT + P*{t} + 0 Timer Configuration Register

TMRSR{t} BT + P*{t} + 4 Timer Status Register

TMRCSSR{t} BT + P*{t} + 8 Timer Clock Source Selection Register

TMRATR{t} BT + P*{t} + 12 Timer Absolute Target Register

Timer Configuration Register

Offset: 0x70000

Read/Write: R/W

Parity Protection: N

SCR Protection: TMRSCR6_0

Reset: 0x40000000 (0b01x0,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31 0x0 EN:

Enable, when set, enables the countdown process.

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Bit Reset Description

30 0x1 PER:

Periodic, when set, the internal counter is automatically reloaded after reaching 0

28:0 0x0 PTV:

Timer Present Trigger Value. When TMRCR is written and EN is 1b, the internal counter

is loaded with PTV+1 and starts counting down at each timing reference pulse. An interrupt

is set when the internal counter reaches 0. Note that writing TMRCR with EN=1 while

EN was already 1 restarts the counter.

Once the timer is started, TARGET can be used to either

- observe the value of the reference counter when the next interrupt will be generated (read)

- select the exact reference counter value at which the next interrupt will be generated (write)

TKE_TOP_TIMER_TMR6_TMRSR_0

Timer Status Register

Offset: 0x70004

Read/Write: See table below

Parity Protection: N

SCR Protection: TMRSCR6_0

Reset: 0x00000000 (0bx0x0,0000,0000,0000,0000,0000,0000,0000)

Bit R/W Reset Description

30 RW 0x0 INTR_CLR:

Clears the interrupt when written as 1b, read always returns 0

28:0 RO 0x0 PCV:

Current counter value, writing to this field has no effect

TKE_TOP_TIMER_TMR6_TMRCSSR_0

Timer Clock Source Selection Register

Offset: 0x70008

Read/Write: R/W

Parity Protection: N

SCR Protection: TMRSCR6_0

Reset: 0x00000000 (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xx00)

Bit Reset Description

1:0

0x0

SRC_ID:

Select Count reference

2'b11 - TSC [41:12]

2'b10 - TSC [29:0]

2'b01 - oscCnt [29:0]

2'b00 - usecCnt [29:0]

The implementation of each timer uses comparison against counters incrementing

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Bit Reset Description

at the selected rate.

= SRC_USECCNT0

= SRC_OSCCNT1

= SRC_TSCCNT_29_02

= SRC_TSCCNT_41_123

TKE_TOP_TIMER_TMR6_TMRATR_0

Timer Absolute Target Register

Offset: 0x7000c

Read/Write: R/W

Parity Protection: N

SCR Protection: TMRSCR6_0

Reset: 0x00000000 (0bxx00,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

29:0 0x0 TARGET:

Target value of the selected reference counter, i.e. when value of the selected reference

equals target value, the interrupt is generated. The difference between TARGET and the

current value must be positive when interpreting TARGET and the 29 LSB of the selected

reference counter as signed integers, otherwise the interrupt triggers immediately.

TKE_TOP_TIMER_TMR7_TMRCR_0

TMRCR{t} BT + P*{t} + 0 Timer Configuration Register

TMRSR{t} BT + P*{t} + 4 Timer Status Register

TMRCSSR{t} BT + P*{t} + 8 Timer Clock Source Selection Register

TMRATR{t} BT + P*{t} + 12 Timer Absolute Target Register

Timer Configuration Register

Offset: 0x80000

Read/Write: R/W

Parity Protection: N

SCR Protection: TMRSCR7_0

Reset: 0x40000000 (0b01x0,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31 0x0 EN:

Enable, when set, enables the countdown process.

30 0x1

PER:

Periodic, when set, the internal counter is automatically reloaded after reaching 0

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Bit Reset Description

28:0 0x0 PTV:

Timer Present Trigger Value. When TMRCR is written and EN is 1b, the internal counter

is loaded with PTV+1 and starts counting down at each timing reference pulse. An interrupt

is set when the internal counter reaches 0. Note that writing TMRCR with EN=1 while

EN was already 1 restarts the counter.

Once the timer is started, TARGET can be used to either

- observe the value of the reference counter when the next interrupt will be generated (read)

- select the exact reference counter value at which the next interrupt will be generated (write)

TKE_TOP_TIMER_TMR7_TMRSR_0

Timer Status Register

Offset: 0x80004

Read/Write: See table below

Parity Protection: N

SCR Protection: TMRSCR7_0

Reset: 0x00000000 (0bx0x0,0000,0000,0000,0000,0000,0000,0000)

Bit R/W Reset Description

30 RW 0x0 INTR_CLR:

Clears the interrupt when written as 1b, read always returns 0

28:0 RO 0x0 PCV:

Current counter value, writing to this field has no effect

TKE_TOP_TIMER_TMR7_TMRCSSR_0

Timer Clock Source Selection Register

Offset: 0x80008

Read/Write: R/W

Parity Protection: N

SCR Protection: TMRSCR7_0

Reset: 0x00000000 (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xx00)

Bit Reset Description

1:0

0x0

SRC_ID:

Select Count reference

2'b11 - TSC [41:12]

2'b10 - TSC [29:0]

2'b01 - oscCnt [29:0]

2'b00 - usecCnt [29:0]

The implementation of each timer uses comparison against counters incrementing

at the selected rate.

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Bit Reset Description

= SRC_USECCNT0

= SRC_OSCCNT1

= SRC_TSCCNT_29_02

= SRC_TSCCNT_41_123

TKE_TOP_TIMER_TMR7_TMRATR_0

Timer Absolute Target Register

Offset: 0x8000c

Read/Write: R/W

Parity Protection: N

SCR Protection: TMRSCR7_0

Reset: 0x00000000 (0bxx00,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

29:0 0x0

TARGET:

Target value of the selected reference counter, i.e. when value of the selected reference

equals target value, the interrupt is generated. The difference between TARGET and the

current value must be positive when interpreting TARGET and the 29 LSB of the selected

reference counter as signed integers, otherwise the interrupt triggers immediately.

TKE_TOP_TIMER_TMR8_TMRCR_0

TMRCR{t} BT + P*{t} + 0 Timer Configuration Register

TMRSR{t} BT + P*{t} + 4 Timer Status Register

TMRCSSR{t} BT + P*{t} + 8 Timer Clock Source Selection Register

TMRATR{t} BT + P*{t} + 12 Timer Absolute Target Register

Timer Configuration Register

Offset: 0x90000

Read/Write: R/W

Parity Protection: N

SCR Protection: TMRSCR8_0

Reset: 0x40000000 (0b01x0,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31 0x0 EN:

Enable, when set, enables the countdown process.

30 0x1 PER:

Periodic, when set, the internal counter is automatically reloaded after reaching 0

28:0

0x0

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Bit Reset Description

PTV:

Timer Present Trigger Value. When TMRCR is written and EN is 1b, the internal counter

is loaded with PTV+1 and starts counting down at each timing reference pulse. An interrupt

is set when the internal counter reaches 0. Note that writing TMRCR with EN=1 while

EN was already 1 restarts the counter.

Once the timer is started, TARGET can be used to either

- observe the value of the reference counter when the next interrupt will be generated (read)

- select the exact reference counter value at which the next interrupt will be generated (write)

TKE_TOP_TIMER_TMR8_TMRSR_0

Timer Status Register

Offset: 0x90004

Read/Write: See table below

Parity Protection: N

SCR Protection: TMRSCR8_0

Reset: 0x00000000 (0bx0x0,0000,0000,0000,0000,0000,0000,0000)

Bit R/W Reset Description

30 RW 0x0 INTR_CLR:

Clears the interrupt when written as 1b, read always returns 0

28:0 RO 0x0 PCV:

Current counter value, writing to this field has no effect

TKE_TOP_TIMER_TMR8_TMRCSSR_0

Timer Clock Source Selection Register

Offset: 0x90008

Read/Write: R/W

Parity Protection: N

SCR Protection: TMRSCR8_0

Reset: 0x00000000 (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xx00)

Bit Reset Description

1:0

0x0

SRC_ID:

Select Count reference

2'b11 - TSC [41:12]

2'b10 - TSC [29:0]

2'b01 - oscCnt [29:0]

2'b00 - usecCnt [29:0]

The implementation of each timer uses comparison against counters incrementing

at the selected rate.

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Bit Reset Description

= SRC_USECCNT0

= SRC_OSCCNT1

= SRC_TSCCNT_29_02

= SRC_TSCCNT_41_123

TKE_TOP_TIMER_TMR8_TMRATR_0

Timer Absolute Target Register

Offset: 0x9000c

Read/Write: R/W

Parity Protection: N

SCR Protection: TMRSCR8_0

Reset: 0x00000000 (0bxx00,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

29:0 0x0 TARGET:

Target value of the selected reference counter, i.e. when value of the selected reference

equals target value, the interrupt is generated. The difference between TARGET and the

current value must be positive when interpreting TARGET and the 29 LSB of the selected

reference counter as signed integers, otherwise the interrupt triggers immediately.

TKE_TOP_TIMER_TMR9_TMRCR_0

TMRCR{t} BT + P*{t} + 0 Timer Configuration Register

TMRSR{t} BT + P*{t} + 4 Timer Status Register

TMRCSSR{t} BT + P*{t} + 8 Timer Clock Source Selection Register

TMRATR{t} BT + P*{t} + 12 Timer Absolute Target Register

Timer Configuration Register

Offset: 0xa0000

Read/Write: R/W

Parity Protection: N

SCR Protection: TMRSCR9_0

Reset: 0x40000000 (0b01x0,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31 0x0 EN:

Enable, when set, enables the countdown process.

30 0x1 PER:

Periodic, when set, the internal counter is automatically reloaded after reaching 0

28:0

0x0

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Bit Reset Description

PTV:

Timer Present Trigger Value. When TMRCR is written and EN is 1b, the internal counter

is loaded with PTV+1 and starts counting down at each timing reference pulse. An interrupt

is set when the internal counter reaches 0. Note that writing TMRCR with EN=1 while

EN was already 1 restarts the counter.

Once the timer is started, TARGET can be used to either

- observe the value of the reference counter when the next interrupt will be generated (read)

- select the exact reference counter value at which the next interrupt will be generated (write)

TKE_TOP_TIMER_TMR9_TMRSR_0

Timer Status Register

Offset: 0xa0004

Read/Write: See table below

Parity Protection: N

SCR Protection: TMRSCR9_0

Reset: 0x00000000 (0bx0x0,0000,0000,0000,0000,0000,0000,0000)

Bit R/W Reset Description

30 RW 0x0 INTR_CLR:

Clears the interrupt when written as 1b, read always returns 0

28:0 RO 0x0 PCV:

Current counter value, writing to this field has no effect

TKE_TOP_TIMER_TMR9_TMRCSSR_0

Timer Clock Source Selection Register

Offset: 0xa0008

Read/Write: R/W

Parity Protection: N

SCR Protection: TMRSCR9_0

Reset: 0x00000000 (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xx00)

Bit Reset Description

1:0

0x0

SRC_ID:

Select Count reference

2'b11 - TSC [41:12]

2'b10 - TSC [29:0]

2'b01 - oscCnt [29:0]

2'b00 - usecCnt [29:0]

The implementation of each timer uses comparison against counters incrementing

at the selected rate.

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Bit Reset Description

= SRC_USECCNT0

= SRC_OSCCNT1

= SRC_TSCCNT_29_02

= SRC_TSCCNT_41_123

TKE_TOP_TIMER_TMR9_TMRATR_0

Timer Absolute Target Register

Offset: 0xa000c

Read/Write: R/W

Parity Protection: N

SCR Protection: TMRSCR9_0

Reset: 0x00000000 (0bxx00,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

29:0 0x0

TARGET:

Target value of the selected reference counter, i.e. when value of the selected reference

equals target value, the interrupt is generated. The difference between TARGET and the

current value must be positive when interpreting TARGET and the 29 LSB of the selected

reference counter as signed integers, otherwise the interrupt triggers immediately.

====================================================

Time Keeping Element: WatchDog Timers Master Spec

====================================================

TKE_TOP_WDT0_WDTCR_0

WDTCR{w} BW + P*{w} + 0 RW Watchdog Timer Configuration Register

WDTSR{w} BW + P*{w} + 4 RO Watchdog Timer Status Register

WDTCMDR{w} BW + P*{w} + 8 WO Watchdog Timer Command Register

WDTUR{w} BW + P*{w} + 12 RW Watchdog Timer Unlock Register

Watchdog Timer Configuration Register

Offset: 0xb0000

Read/Write: R/W

Parity Protection: N

SCR Protection: WDTSCR0_0

Reset: 0x00700000 (0b0000,xx00,0111,0000,0000,0000,0000,0000)

Bit Reset Description

31:28 0x0

WindowedRestartDisableMap:

When WindowedOperationEnable is 1b, restart commands attempted when expiration level has value b are

rejected

if bit b equals 1b in this field

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Bit Reset Description

25 0x0 DisallowWDTFreeze:

When 1b, the signal watchdog_freeze_request has no effect

When 0b, when the signal watchdog_freeze_request is asserted, the WDT stops decrementing CurrentCount

if the WDT is enabled

24:23 0x0

RestartErrorAction:

If a restart action is attempted but fails, indicate which of 4 actions should be taken

0x0: do nothing, silently ignore the restart

0x1: immediately jump to expiration level 4 and reload the downcounter

0x2: immediately jump to expiration level 5 and reload the downcounter

0x3: immediately request a system power on reset

When jumping levels, the normal actions configured per level must take place

= NOP0

= JUMP_TO_41

= JUMP_TO_52

= POR_RESET3

22:20 0x7 ErrorThreshold:

The WDT logic asserts an error signal to HSM when ExpirationLevel >= ErrorThreshold.

19 0x0 TscReferenceEnable:

Select as timing reference transitions on a configured TSC bit.

18 0x0 ChallengeResponseEnable:

Enable the Challenge Response mode of operation. When 1b, the Unlock register operates as a Challenge

Response register.

17 0x0

WindowedOperationEnable:

Enable the windowed mode of operation. When 1b a restart command is rejected when the current expiration

level

is identified as disallowed in the WindowedRestartDisableMap or the current time is below the window

threshold.

The rejection is either silent or perform a reset based on RestartErrorAction

16 0x0

SystemPOResetEnable:

Enable internal full system reset at fifth expiration of the counter.

This reset cannot be intercepted and acts as a Power On Reset

15 0x0 SystemDebugResetEnable:

Enable system wide reset assertion at fourth expiration of the counter.

This reset can be intercepted by debug logic, e.g. to preserve information

14 0x0 RemoteInterruptEnable:

Enable normal priority interrupt assertion at third expiration of the counter,

connected to LIC for system wide visibility

13 0x0

LocalFIQEnable:

Enable high priority interrupt (FIQ) assertion at second expiration of the counter,

connected to local interrupt controller

0x0

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Bit Reset Description

LocalInterruptEnable:

Enable normal priority interrupt assertion at first expiration of the counter,

connected to local interrupt controller

11:4 0x0

Period:

Measured in periods of the timer selected as source, this is the reload value, so 0 is treated as maximum

period

3:0 0x0 TimerSource:

The timer source interpretation is dependent on the value of TscReferenceEnable:

TscReferenceEnable = 0b: timer<TimerSource> is the timing reference

TscReferenceEnable = 1b: a transition of TSC[2*TimerSource] is the timing reference

TKE_TOP_WDT0_WDTSR_0

Watchdog Timer Status Register

Offset: 0xb0004

Read/Write: RO

Parity Protection: N

SCR Protection: WDTSCR0_0

Reset: 0x00000000 (0bxxxx,xxxx,xxxx,0000,x000,0000,0000,0000)

Bit Reset Description

19 0x0

Frozen:

1b indicates that the WDT is frozen because of the assertion of the global WDT freeze request

(when allowed) or because of the assertion of the global timer freeze request

18 0x0 ErrorForced:

1b indicates that the error reported to HSM is forced active for testing purpose

17 0x0 StickyEnabled:

1b when the counter is enabled and cannot be disabled, set by StickyStart command, cleared by reset only.

16 0x0 CurrentError:

Current error reported to HSM, this is the output after combining the functional and forced error paths

14:12 0x0 CurrentExpirationCount:

Current count of expiration since last start operation, cleared by Start command, saturating at 5.

11:4 0x0 CurrentCount:

Current value of the downcounter, reloaded with Period by Start command.

3 0x0

RemoteInterruptStatus:

Current status of remote interrupt, cleared by Start command

2 0x0

LocalFIQStatus:

Current status of FIQ, cleared by Start command.

1 0x0

LocalInterruptStatus:

Current status of local interrupt, cleared by Start command.

0x0

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Bit Reset Description

Enabled:

1b when the counter is active. When Enabled is 1b, the configuration of the WDT is frozen by silently

ignoring write attempts to the configuration registers: WDTCR, WDTSCR and WDTFWCR. Set by Start or

StickyStart commands,

cleared by Disable when StickyEnabled is 0b.

TKE_TOP_WDT0_WDTCMDR_0

Watchdog Timer Command Register

Offset: 0xb0008

Read/Write: R/W

Parity Protection: N

SCR Protection: WDTSCR0_0

Reset: 0x00000000 (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,0000)

Bit Reset Description

3 0x0

ForceError:

Only working if the Command register is unlocked. 1b sets an internal flop that is ORED with the

functional error signal (based on threshold), 0b clears the bit. The state of the flop is shown

in the status register.

2 0x0 StickyStart:

Qualifies the StartCounter bit, if both bits are 1b, the counter is enabled in permanent fashion, i.e.

it remains enabled until the next reset, and a disable counter operation has no effect. Ignored if StartCounter

is 0b

1 0x0

DisableCounter:

Only working if the unlock register (WDTUR{w}) has been programmed before with the correct pattern.

Writing to the command register always clears the unlock register. If written to 1b, while StartCounter

is 0b and the unlock register contains the unlock pattern, the watchdog transitions back to disabled.

0 0x0 StartCounter:

When written to 1b, enable the counter operation,load the counter with Period and starts downcounting,

resets the expiration count to 0 and clears all status flags. Enabled is always 1b after this.

This is also used as Restart. Writing to StartCounter requires unlocking when ChallengeResponseEnable

is 1b, and writing to StartCounter is also restricted to windows of time given by WindowedRestartDisableMap

when WindowedOperationEnable is 1b.

TKE_TOP_WDT0_WDTUR_0

Watchdog Timer Unlock Register

Offset: 0xb000c

Read/Write: R/W

Parity Protection: N

SCR Protection: WDTSCR0_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

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Bit Reset Description

31:0 0x0 UnlockPattern:

The behavior of the Unlock pattern is dependent on the ChallengeResponseEnable configuration bit

When ChallengeResponseEnable is 0b, Unlock must be written with value 0x0000_C45A to allow a write to

DisableCounter to take effect. The UnlockPattern is reset at each write to the Command register.

When ChallengeResponseEnable is 1b, a write to the Command register is only allowed after reading the

Unlock pattern to get the current value of a LFSR, followed by writing the next value of the LFSR to the

UnlockPattern.

If the two values match, the unlock is successful, in all cases the LFSR gets (re)initialized with the written

value.

TKE_TOP_WDT0_WDTSCR_0

Watchdog Timer Skip Configuration Register

Offset: 0xb0010

Read/Write: R/W

Parity Protection: N

SCR Protection: WDTSCR0_0

Reset: 0x00000000 (0bxxxx,xxxx,xxxx,xxxx,x000,x000,x000,x000)

Bit Reset Description

14:12 0x0

Skip3:

Skip Value at Expiration count 3

At a Downcounter expiration, the expiration level changes as ExpC <= ExpC + 1 + Skip(ExpC), saturating at

10:8 0x0 Skip2:

Skip Value at Expiration count 2

6:4 0x0 Skip1:

Skip Value at Expiration count 1

2:0 0x0

Skip0:

Skip Value at Expiration count 0

TKE_TOP_WDT0_WDTFWCR_0

Watchdog Timer Fine Window Configuration Register

Offset: 0xb0014

Read/Write: R/W

Parity Protection: N

SCR Protection: WDTSCR0_0

Reset: 0x00000000 (0bxxxx,xxxx,xxxx,x000,xxxx,xxxx,0000,0000)

Bit Reset Description

18:16

0x0

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Bit Reset Description

StartLevel:

If restart (i.e. start while WDT is already enabled) is attempted and windowing operation is enabled,

restart is rejected if current expiration < StartLevel

7:0 0x0 StartCount:

If restart (i.e. start while WDT is already enabled) is attempted and windowing operation is enabled and

current expiration level == StartLevel, restart is rejected if current downcounter > (Period - StartCount).

StartCount is the number of cycles where rejection takes place at the start of that level.

TKE_TOP_WDT1_WDTCR_0

WDTCR{w} BW + P*{w} + 0 RW Watchdog Timer Configuration Register

WDTSR{w} BW + P*{w} + 4 RO Watchdog Timer Status Register

WDTCMDR{w} BW + P*{w} + 8 WO Watchdog Timer Command Register

WDTUR{w} BW + P*{w} + 12 RW Watchdog Timer Unlock Register

Watchdog Timer Configuration Register

Offset: 0xc0000

Read/Write: R/W

Parity Protection: N

SCR Protection: WDTSCR1_0

Reset: 0x00700000 (0b0000,xx00,0111,0000,0000,0000,0000,0000)

Bit Reset Description

31:28 0x0 WindowedRestartDisableMap:

When WindowedOperationEnable is 1b, restart commands attempted when expiration level has value b are

rejected

if bit b equals 1b in this field

25 0x0 DisallowWDTFreeze:

When 1b, the signal watchdog_freeze_request has no effect

When 0b, when the signal watchdog_freeze_request is asserted, the WDT stops decrementing CurrentCount

if the WDT is enabled

24:23 0x0

RestartErrorAction:

If a restart action is attempted but fails, indicate which of 4 actions should be taken

0x0: do nothing, silently ignore the restart

0x1: immediately jump to expiration level 4 and reload the downcounter

0x2: immediately jump to expiration level 5 and reload the downcounter

0x3: immediately request a system Power On Reset

When jumping levels, the normal actions configured per level must take place

= NOP0

= JUMP_TO_41

= JUMP_TO_52

= POR_RESET3

22:20

0x7

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Bit Reset Description

ErrorThreshold:

The WDT logic asserts an error signal to HSM when ExpirationLevel >= ErrorThreshold.

19 0x0

TscReferenceEnable:

Select as timing reference transitions on a configured TSC bit.

18 0x0

ChallengeResponseEnable:

Enable the Challenge Response mode of operation. When 1b, the Unlock register operates as a Challenge

Response register.

17 0x0 WindowedOperationEnable:

Enable the windowed mode of operation. When 1b a restart command is rejected when the current expiration

level

is identified as disallowed in the WindowedRestartDisableMap or the current time is below the window

threshold.

The rejection is either silent or perform a reset based on RestartErrorAction

16 0x0 SystemPOResetEnable:

Enable internal full system reset at fifth expiration of the counter.

This reset cannot be intercepted and acts as a Power On Reset

15 0x0

SystemDebugResetEnable:

Enable system wide reset assertion at fourth expiration of the counter.

This reset can be intercepted by debug logic, e.g. to preserve information

14 0x0 RemoteInterruptEnable:

Enable normal priority interrupt assertion at third expiration of the counter,

connected to LIC for system wide visibility

13 0x0 LocalFIQEnable:

Enable high priority interrupt (FIQ) assertion at second expiration of the counter,

connected to local interrupt controller

12 0x0

LocalInterruptEnable:

Enable normal priority interrupt assertion at first expiration of the counter,

connected to local interrupt controller

11:4 0x0 Period:

Measured in periods of the timer selected as source, this is the reload value, so 0 is treated as maximum

period

3:0 0x0

TimerSource:

The timer source interpretation is dependent on the value of TscReferenceEnable:

TscReferenceEnable = 0b: timer<TimerSource> is the timing reference

TscReferenceEnable = 1b: a transition of TSC[2*TimerSource] is the timing reference

TKE_TOP_WDT1_WDTSR_0

Watchdog Timer Status Register

Offset: 0xc0004

Read/Write: RO

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Parity Protection: N

SCR Protection: WDTSCR1_0

Reset: 0x00000000 (0bxxxx,xxxx,xxxx,0000,x000,0000,0000,0000)

Bit Reset Description

19 0x0

Frozen:

1b indicates that the WDT is frozen because of the assertion of the global WDT freeze request

(when allowed) or because of the assertion of the global timer freeze request

18 0x0 ErrorForced:

1b indicates that the error reported to HSM is forced active for testing purpose

17 0x0 StickyEnabled:

1b when the counter is enabled and cannot be disabled, set by StickyStart command, cleared by reset only.

16 0x0 CurrentError:

Current error reported to HSM, this is the output after combining the functional and forced error paths

14:12 0x0

CurrentExpirationCount:

Current count of expiration since last start operation, cleared by Start command, saturating at 5.

11:4 0x0

CurrentCount:

Current value of the downcounter, reloaded with Period by Start command.

3 0x0

RemoteInterruptStatus:

Current status of remote interrupt, cleared by Start command

2 0x0

LocalFIQStatus:

Current status of FIQ, cleared by Start command.

1 0x0 LocalInterruptStatus:

Current status of local interrupt, cleared by Start command.

0 0x0 Enabled:

1b when the counter is active. When Enabled is 1b, the configuration of the WDT is frozen by silently

ignoring write attempts to the configuration registers: WDTCR, WDTSCR and WDTFWCR. Set by Start or

StickyStart commands,

cleared by Disable when StickyEnabled is 0b.

TKE_TOP_WDT1_WDTCMDR_0

Watchdog Timer Command Register

Offset: 0xc0008

Read/Write: R/W

Parity Protection: N

SCR Protection: WDTSCR1_0

Reset: 0x00000000 (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,0000)

Bit Reset Description

0x0

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Bit Reset Description

ForceError:

Only working if the Command register is unlocked. 1b sets an internal flop that is ORED with the

functional error signal (based on threshold), 0b clears the bit. The state of the flop is shown

in the status register.

2 0x0 StickyStart:

Qualifies the StartCounter bit, if both bits are 1b, the counter is enabled in permanent fashion, i.e.

it remains enabled until the next reset, and a disable counter operation has no effect. Ignored if StartCounter

is 0b

1 0x0

DisableCounter:

Only working if the unlock register (WDTUR{w}) has been programmed before with the correct pattern.

Writing to the command register always clears the unlock register. If written to 1b, while StartCounter

is 0b and the unlock register contains the unlock pattern, the watchdog transitions back to disabled.

0 0x0 StartCounter:

When written to 1b, enable the counter operation,load the counter with Period and starts downcounting,

resets the expiration count to 0 and clears all status flags. Enabled is always 1b after this.

This is also used as Restart. Writing to StartCounter requires unlocking when ChallengeResponseEnable

is 1b, and writing to StartCounter is also restricted to windows of time given by WindowedRestartDisableMap

when WindowedOperationEnable is 1b.

TKE_TOP_WDT1_WDTUR_0

Watchdog Timer Unlock Register

Offset: 0xc000c

Read/Write: R/W

Parity Protection: N

SCR Protection: WDTSCR1_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 UnlockPattern:

The behavior of the Unlock pattern is dependent on the ChallengeResponseEnable configuration bit

When ChallengeResponseEnable is 0b, Unlock must be written with value 0x0000_C45A to allow a write to

DisableCounter to take effect. The UnlockPattern is reset at each write to the Command register.

When ChallengeResponseEnable is 1b, a write to the Command register is only allowed after reading the

Unlock pattern to get the current value of a LFSR, followed by writing the next value of the LFSR to the

UnlockPattern.

If the two values match, the unlock is successful, in all cases the LFSR gets (re)initialized with the written

value.

TKE_TOP_WDT1_WDTSCR_0

Watchdog Timer Skip Configuration Register

Offset: 0xc0010

Read/Write: R/W

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Parity Protection: N

SCR Protection: WDTSCR1_0

Reset: 0x00000000 (0bxxxx,xxxx,xxxx,xxxx,x000,x000,x000,x000)

Bit Reset Description

14:12 0x0

Skip3:

Skip Value at Expiration count 3

At a Downcounter expiration, the expiration level changes as ExpC <= ExpC + 1 + Skip(ExpC), saturating at

10:8 0x0 Skip2:

Skip Value at Expiration count 2

6:4 0x0

Skip1:

Skip Value at Expiration count 1

2:0 0x0

Skip0:

Skip Value at Expiration count 0

TKE_TOP_WDT1_WDTFWCR_0

Watchdog Timer Fine Window Configuration Register

Offset: 0xc0014

Read/Write: R/W

Parity Protection: N

SCR Protection: WDTSCR1_0

Reset: 0x00000000 (0bxxxx,xxxx,xxxx,x000,xxxx,xxxx,0000,0000)

Bit Reset Description

18:16 0x0 StartLevel:

If restart (i.e. start while WDT is already enabled) is attempted and windowing operation is enabled,

restart is rejected if current expiration < StartLevel

7:0 0x0

StartCount:

If restart (i.e. start while WDT is already enabled) is attempted and windowing operation is enabled and

current expiration level == StartLevel, restart is rejected if current downcounter > (Period - StartCount).

StartCount is the number of cycles where rejection takes place at the start of that level.

TKE_TOP_WDT2_WDTCR_0

WDTCR{w} BW + P*{w} + 0 RW Watchdog Timer Configuration Register

WDTSR{w} BW + P*{w} + 4 RO Watchdog Timer Status Register

WDTCMDR{w} BW + P*{w} + 8 WO Watchdog Timer Command Register

WDTUR{w} BW + P*{w} + 12 RW Watchdog Timer Unlock Register

Watchdog Timer Configuration Register

Offset: 0xd0000

Read/Write: R/W

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Parity Protection: N

SCR Protection: WDTSCR2_0

Reset: 0x00700000 (0b0000,xx00,0111,0000,0000,0000,0000,0000)

Bit Reset Description

31:28 0x0 WindowedRestartDisableMap:

When WindowedOperationEnable is 1b, restart commands attempted when expiration level has value b are

rejected

if bit b equals 1b in this field

25 0x0 DisallowWDTFreeze:

When 1b, the signal watchdog_freeze_request has no effect

When 0b, when the signal watchdog_freeze_request is asserted, the WDT stops decrementing CurrentCount

if the WDT is enabled

24:23 0x0

RestartErrorAction:

If a restart action is attempted but fails, indicate which of 4 actions should be taken

0x0: do nothing, silently ignore the restart

0x1: immediately jump to expiration level 4 and reload the downcounter

0x2: immediately jump to expiration level 5 and reload the downcounter

0x3: immediately request a system Power On Reset

When jumping levels, the normal actions configured per level must take place

= NOP0

= JUMP_TO_41

= JUMP_TO_52

= POR_RESET3

22:20 0x7 ErrorThreshold:

The WDT logic asserts an error signal to HSM when ExpirationLevel >= ErrorThreshold.

19 0x0 TscReferenceEnable:

Select as timing reference transitions on a configured TSC bit.

18 0x0 ChallengeResponseEnable:

Enable the Challenge Response mode of operation. When 1b, the Unlock register operates as a Challenge

Response register.

17 0x0 WindowedOperationEnable:

Enable the windowed mode of operation. When 1b a restart command is rejected when the current expiration

level

is identified as disallowed in the WindowedRestartDisableMap or the current time is below the window

threshold.

The rejection is either silent or perform a reset based on RestartErrorAction

16 0x0

SystemPOResetEnable:

Enable internal full system reset at fifth expiration of the counter.

This reset cannot be intercepted and acts as a Power On Reset

15 0x0 SystemDebugResetEnable:

Enable system wide reset assertion at fourth expiration of the counter.

This reset can be intercepted by debug logic, e.g. to preserve information

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Bit Reset Description

14 0x0 RemoteInterruptEnable:

Enable normal priority interrupt assertion at third expiration of the counter,

connected to LIC for system wide visibility

13 0x0 LocalFIQEnable:

Enable high priority interrupt (FIQ) assertion at second expiration of the counter,

connected to local interrupt controller

12 0x0

LocalInterruptEnable:

Enable normal priority interrupt assertion at first expiration of the counter,

connected to local interrupt controller

11:4 0x0 Period:

Measured in periods of the timer selected as source, this is the reload value, so 0 is treated as maximum

period

3:0 0x0

TimerSource:

The timer source interpretation is dependent on the value of TscReferenceEnable:

TscReferenceEnable = 0b: timer<TimerSource> is the timing reference

TscReferenceEnable = 1b: a transition of TSC[2*TimerSource] is the timing reference

TKE_TOP_WDT2_WDTSR_0

Watchdog Timer Status Register

Offset: 0xd0004

Read/Write: RO

Parity Protection: N

SCR Protection: WDTSCR2_0

Reset: 0x00000000 (0bxxxx,xxxx,xxxx,0000,x000,0000,0000,0000)

Bit Reset Description

19 0x0

Frozen:

1b indicates that the WDT is frozen because of the assertion of the global WDT freeze request

(when allowed) or because of the assertion of the global timer freeze request

18 0x0 ErrorForced:

1b indicates that the error reported to HSM is forced active for testing purpose

17 0x0 StickyEnabled:

1b when the counter is enabled and cannot be disabled, set by StickyStart command, cleared by reset only.

16 0x0 CurrentError:

Current error reported to HSM, this is the output after combining the functional and forced error paths

14:12 0x0

CurrentExpirationCount:

Current count of expiration since last start operation, cleared by Start command, saturating at 5.

11:4 0x0

CurrentCount:

Current value of the downcounter, reloaded with Period by Start command.

3 0x0

RemoteInterruptStatus:

Current status of remote interrupt, cleared by Start command

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Bit Reset Description

2 0x0

LocalFIQStatus:

Current status of FIQ, cleared by Start command.

1 0x0

LocalInterruptStatus:

Current status of local interrupt, cleared by Start command.

0 0x0

Enabled:

1b when the counter is active. When Enabled is 1b, the configuration of the WDT is frozen by silently

ignoring write attempts to the configuration registers: WDTCR, WDTSCR and WDTFWCR. Set by Start or

StickyStart commands,

cleared by Disable when StickyEnabled is 0b.

TKE_TOP_WDT2_WDTCMDR_0

Watchdog Timer Command Register

Offset: 0xd0008

Read/Write: R/W

Parity Protection: N

SCR Protection: WDTSCR2_0

Reset: 0x00000000 (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,0000)

Bit Reset Description

3 0x0 ForceError:

Only working if the Command register is unlocked. 1b sets an internal flop that is ORED with the

functional error signal (based on threshold), 0b clears the bit. The state of the flop is shown

in the status register.

2 0x0

StickyStart:

Qualifies the StartCounter bit, if both bits are 1b, the counter is enabled in permanent fashion, i.e.

it remains enabled until the next reset, and a disable counter operation has no effect. Ignored if StartCounter

is 0b

1 0x0 DisableCounter:

Only working if the unlock register (WDTUR{w}) has been programmed before with the correct pattern.

Writing to the command register always clears the unlock register. If written to 1b, while StartCounter

is 0b and the unlock register contains the unlock pattern, the watchdog transitions back to disabled.

0 0x0 StartCounter:

When written to 1b, enable the counter operation,load the counter with Period and starts downcounting,

resets the expiration count to 0 and clears all status flags. Enabled is always 1b after this.

This is also used as Restart. Writing to StartCounter requires unlocking when ChallengeResponseEnable

is 1b, and writing to StartCounter is also restricted to windows of time given by WindowedRestartDisableMap

when WindowedOperationEnable is 1b.

TKE_TOP_WDT2_WDTUR_0

Watchdog Timer Unlock Register

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Offset: 0xd000c

Read/Write: R/W

Parity Protection: N

SCR Protection: WDTSCR2_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 UnlockPattern:

The behavior of the Unlock pattern is dependent on the ChallengeResponseEnable configuration bit

When ChallengeResponseEnable is 0b, Unlock must be written with value 0x0000_C45A to allow a write to

DisableCounter to take effect. The UnlockPattern is reset at each write to the Command register.

When ChallengeResponseEnable is 1b, a write to the Command register is only allowed after reading the

Unlock pattern to get the current value of a LFSR, followed by writing the next value of the LFSR to the

UnlockPattern.

If the two values match, the unlock is successful, in all cases the LFSR gets (re)initialized with the written

value.

TKE_TOP_WDT2_WDTSCR_0

Watchdog Timer Skip Configuration Register

Offset: 0xd0010

Read/Write: R/W

Parity Protection: N

SCR Protection: WDTSCR2_0

Reset: 0x00000000 (0bxxxx,xxxx,xxxx,xxxx,x000,x000,x000,x000)

Bit Reset Description

14:12 0x0

Skip3:

Skip Value at Expiration count 3

At a Downcounter expiration, the expiration level changes as ExpC <= ExpC + 1 + Skip(ExpC), saturating at

10:8 0x0 Skip2:

Skip Value at Expiration count 2

6:4 0x0 Skip1:

Skip Value at Expiration count 1

2:0 0x0 Skip0:

Skip Value at Expiration count 0

TKE_TOP_WDT2_WDTFWCR_0

Watchdog Timer Fine Window Configuration Register

Offset: 0xd0014

Read/Write: R/W

Parity Protection: N

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SCR Protection: WDTSCR2_0

Reset: 0x00000000 (0bxxxx,xxxx,xxxx,x000,xxxx,xxxx,0000,0000)

Bit Reset Description

18:16 0x0 StartLevel:

If restart (i.e. start while WDT is already enabled) is attempted and windowing operation is enabled,

restart is rejected if current expiration < StartLevel

7:0 0x0 StartCount:

If restart (i.e. start while WDT is already enabled) is attempted and windowing operation is enabled and

current expiration level == StartLevel, restart is rejected if current downcounter > (Period - StartCount).

StartCount is the number of cycles where rejection takes place at the start of that level.

Real-Time Clock Registers

RTC2_RTCCR_0

RTC Control Register

Offset: 0x0

Read/Write: R/W

Parity Protection: Y

SCR Protection: CNTSCR_0

Reset: 0x00000000 (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxx0)

Bit Reset Description

0 0x0 HDBG:

Halt-on-debug. Controls whether a Halt-on-debug signal halts the RTC

0 RTC ignores Halt-on-debug.

1 Asserted Halt-on-debug signal halts RTC.

= ON0

= OFF1

RTC2_RTCBR_0

RTC Busy Register

Offset: 0x4

Read/Write: RO

Parity Protection: N

SCR Protection: RTCSCR_0

Reset: 0x00000000 (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxx0)

Bit Reset Description

0x0

STATUS:

When 1, this bit indicates that a write is being transferred to the 32,768 Hz clock domain. It is set when a

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Bit Reset Description

write targeting

a register in the 32,768 Hz clock domain is received on the APB interface and is cleared when the

write is fully transferred to the 32,768 Hz clock domain.

= FREE0

= BUSY1

RTC2_RTCSCR_0

RTC Second Counter Register

Offset: 0x8

Read/Write: R/W

Parity Protection: N

SCR Protection: CNTSCR_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

CNT:

Part of the time elapsed measured in seconds, read data comes from a register updated in the APB clock

domain every 8 32,768 Hz clock cycles.

RTC2_RTCSSCR_0

RTC Shadow Second Counter Register

Offset: 0xc

Read/Write: RO

Parity Protection: N

SCR Protection: RTCSCR_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

CNT:

Shadow seconds register is updated over to APB side whenever there is a read to milliseconds counter.

This allows SW to get a consistent full accuracy value by reading the milliseconds counter then the shadow

seconds counter.

RTC2_RTCMCR_0

RTC Millisecond Counter Register

Offset: 0x10

Read/Write: RO

Parity Protection: N

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SCR Protection: RTCSCR_0

Reset: 0x00000000 (0bxxxx,xxxx,xxxx,xxxx,xxxx,xx00,0000,0000)

Bit Reset Description

9:0 0x0 CNT:

Part of the time elapsed measured in milliseconds, read data comes from a register updated in the APB clock

domain

every 8 32,768 Hz clock cycles.

RTC2_RTCSAR0_0

RTC Second Alarm Register 0.

Offset: 0x14

Read/Write: R/W

Parity Protection: Y

SCR Protection: RTCSCR_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 VALUE:

Interrupt is triggered when the seconds counter matches the value in this register.

RTC2_RTCSAR1_0

RTC Second Alarm Register 1.

Offset: 0x18

Read/Write: R/W

Parity Protection: Y

SCR Protection: RTCSCR_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

VALUE:

Interrupt is triggered when the seconds counter matches the value in this register.

RTC2_RTCMAR_0

All register fields are parity protected.

RTC Millisecond Alarm Register

Offset: 0x1c

Read/Write: R/W

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Parity Protection: Y

SCR Protection: RTCSCR_0

Reset: 0x00000000 (0bxxxx,xxxx,xxxx,xxxx,xxxx,xx00,0000,0000)

Bit Reset Description

9:0 0x0

VALUE:

Interrupt is triggered when the milliseconds counter matches the value in this register.

RTC2_RTCSCAR_0

RTC Second Countdown Alarm Register

Offset: 0x20

Read/Write: R/W

Parity Protection: Y

SCR Protection: RTCSCR_0

Reset: 0x40000000 (0b0100,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31 0x0 EN:

Enable, when set, enables the countdown process.

30 0x1 PER:

Periodic, when set, the internal counter is automatically reloaded after reaching 0

29:0 0x0

PTV:

Timer Present Trigger Value, when enabled, an internal counter is loaded with this field and counted down

every second until it reaches 0. If enabled, an interrupt is then triggered when the count reaches zero.

RTC2_RTCMCAR_0

RTC Millisecond Countdown Alarm Register

Offset: 0x24

Read/Write: R/W

Parity Protection: Y

SCR Protection: RTCSCR_0

Reset: 0x40000000 (0b0100,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31 0x0

EN:

Enable, when set, enables the countdown process.

30 0x1

PER:

Periodic, when set, the internal counter is automatically reloaded after reaching 0

29:0

0x0

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Bit Reset Description

PTV:

Timer Present Trigger Value, when enabled, an internal counter is loaded with this field and counted down

every millisecond until it reaches 0. If enabled, an interrupt is then triggered when the count reaches zero.

RTC2_RTCIER_0

RTC Interrupt Enable Register

Offset: 0x28

Read/Write: R/W

Parity Protection: Y

SCR Protection: RTCSCR_0

Reset: 0x00000000 (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxx0,0000)

Bit Reset Description

4 0x0 MSEC_CDN_ALARM:

Enable bit for interrupt associated with the millisecond countdown alarm

3 0x0

SEC_CDN_ALARM:

Enable bit for interrupt associated with the second countdown alarm

2 0x0

MSEC_ALARM:

Enable bit for interrupt associated with the milliseconds alarm

1:0 0x0

SEC_ALARM:

Enable bitmap for interrupt associated with each of the second alarms

RTC2_RTCISR_0

RTC Interrupt Status Register

Offset: 0x2c

Read/Write: R/W

Parity Protection: N

SCR Protection: RTCSCR_0

Reset: 0x00000000 (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxx0,0000)

Bit Reset Description

4 0x0 MSEC_CDN_ALARM

3 0x0 SEC_CDN_ALARM

2 0x0 MSEC_ALARM

1:0

0x0

SEC_ALARM:

Same structure as the RTC Interrupt Enable register, shows the current status of the interrupts before

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Bit Reset Description

processing.

The register is RWC, writing a 1 clear the corresponding status bit. The status is taken before applying the

enable mask.

RTC2_RTCIVR_0

RTC Interrupt Valid Register

Offset: 0x30

Read/Write: RO

Parity Protection: N

SCR Protection: RTCSCR_0

Reset: 0x00000000 (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxx0,0000)

Bit Reset Description

4 0x0

MSEC_CDN_ALARM

3 0x0 SEC_CDN_ALARM

2 0x0 MSEC_ALARM

1:0 0x0 SEC_ALARM:

Same structure as the RTC Interrupt Enable register, shows the current status of the interrupts after the

enable mask.

The register is R only and simply returns Status & Enable.

RTC2_RTCFIR_0

RTC Force Interrupt Register

Offset: 0x34

Read/Write: R/W

Parity Protection: N

SCR Protection: RTCSCR_0

Reset: 0x00000000 (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxx0,0000)

Bit Reset Description

4 0x0 MSEC_CDN_ALARM

3 0x0 SEC_CDN_ALARM

2 0x0 MSEC_ALARM

1:0

0x0

SEC_ALARM:

Note that the semantic of the FIR is slightly different than in LIC.

In LIC the FIR register is ORed with the incoming interrupt signals, in RTC the force toggles the source bit

itself.

Also the FIR in RTC acts like the FIR SET register in LIC.

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Bit Reset Description

Same structure as the RTC Interrupt Enable register. Write only register for test purposes, force the

corresponding interrupt status bit to 1b.

RTC2_RTCRSR_0

RTC Reference Selection Register

Offset: 0x38

Read/Write: R/W

Parity Protection: Y

SCR Protection: CNTSCR_0

Reset: 0x00000001 (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xx00,xxx1)

Bit Reset Description

5:4 0x0

MBS:

MTSC Bit Select, MTSC[9+MBS] edge used as reference when not free running.

0 0x1

FR:

Free Running , controls the RTC TSC lock behavior

When 0b RTC uses a selected bit of MTSC for reference, recommended mode

When 1b RTC counts on each 32,768 Hz clock edge

RTC2_RTCDR_0

The values are coded as real value - 1 (offset 1 encoding)

So the division ratio is (1+RTCDR.N) / (1+RTCDR.D) and must be selected

so that the reference frequency * Ratio = 1000 Hz

the reset value is correct for the (default) 32,768Hz clock

RTC Divider Register

Offset: 0x3c

Read/Write: R/W

Parity Protection: Y

SCR Protection: CNTSCR_0

Reset: 0x0fff007c (0b0000,1111,1111,1111,0000,0000,0111,1100)

Bit Reset Description

31:16 0xfff D:

Denominator

15:0 0x7c N:

Numerator

RTC2_RTCBRCR_0

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RTC Base Reference Counter Register

Offset: 0x40

Read/Write: RO

Parity Protection: N

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 CNT:

Counts rising edges of 32,768Hz clock, not sensitive to HDBG, i.e. never stops counting, and no

configuration

RTC2_AOWDTCR_0

====================== AO WDT Registers ======================

Always On Watchdog Timer Configuration Register

Offset: 0x100

Read/Write: R/W

Parity Protection: N

SCR Protection: AOWDTSCR_0

Reset: 0x00700000 (0b0000,xx00,0111,0000,0000,0000,0000,0000)

Bit Reset Description

31:28 0x0

WINDOWEDRESTARTDISABLEMAP:

When WindowedOperationEnable is 1b, restart commands attempted when expiration level has value l

become NOP

if bit b equals 1b.

25 0x0 DISALLOWWDTFREEZE:

When 1b, the signal watchdog_freeze_request has no effect

When 0b, when the signal watchdog_freeze_request is asserted, the WDT stops decrementing CurrentCount

if the WDT is enabled

24:23 0x0 RESTARTERRORACTION:

If a restart action is attempted but fails, indicate which of 4 actions should be taken

0x0: do nothing, silently ignore the restart

0x1: immediately jump to expiration level 4 and reload the downcounter

0x2: immediately jump to expiration level 5 and reload the downcounter

0x3: immediately request a system POR reset

When jumping levels, the normal actions configured per level must take place

22:20 0x7 ERRORTHRESHOLD:

The WDT logic asserts an error signal to HSM when ExpirationLevel > ErrorThreshold.

19 0x0

TSCREFERENCEENABLE:

Select as timing reference transitions on a configured TSC bit.

0x0

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Bit Reset Description

CHALLENGERESPONSEENABLE:

Enable the Challenge Response mode of operation.When 1b, the Unlock register operates as a Challenge

Response register.

17 0x0

WINDOWEDOPERATIONENABLE:

Enable the windowed mode of operation. When 1b a restart command is rejected when the current expiration

level is

identified as disallowed in the WindowedRestartDisableMap or the current time is below the window

threshold.

The rejection is either silent or perform a reset based on RestartErrorAction is identified

as disallowed in the WindowedRestartDisableMap.

16 0x0 SYSTEMPORRESETENABLE:

Enable full system reset at fifth expiration of the counter, mostly at the same level as the signal from

PMC asserted in case of a Power On Reset

15 0x0

SYSTEMDEBUGRESETENABLE:

Enable system wide reset assertion at fourth expiration of the counter.

This reset can be intercepted by debug logic, e.g. to preserve information.

Debug reset must not be enabled for AO WDT.

14 0x0 WAKECOLDENABLE:

Redefined, enable the generation of a SC7 wake event plus clearing of PMC scratch register 0 at third

expiration of

the counter.

This bit is RemoteInterruptEnable for a standard WDT

13 0x0 WAKEENABLE:

Redefined, enable the generation of a SC7 wake event at second expiration of the counter.

This bit is LocalFIQEnable for a standard WDT

12 0x0

LOCALINTERRUPTENABLE:

Enable normal priority interrupt assertion at first expiration of the counter, connected to local interrupt

controller

11:4 0x0 PERIOD:

Measured in periods of the timer selected as source, this is the reload value, so 0 is treated as maximum

period

3:0 0x0 TIMERSOURCE:

The timer source interpretation is dependent on the value of TscReferenceEnable-

TscReferenceEnable is 0b the timing reference is redefined as a transition on a RTC bit

If TimerSource is in 0 or 9, bit TimerSource in the Millisecond counter

If TimeSource is in 10 or 15, bit TimerSource-10 of the Second counter

TscReferenceEnable is 1b the timing reference is redefined as a transition on TSC[10+2*TimerSource]

RTC2_AOWDTSR_0

Always On Watchdog Timer Status Register

Offset: 0x104

Read/Write: RO

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Parity Protection: N

SCR Protection: AOWDTSCR_0

Reset: 0x00000000 (0bxxxx,xxxx,xxxx,0000,x000,0000,0000,0000)

Bit Reset Description

19 0x0

FROZEN:

1b indicates that the WDT is frozen because of the assertion of the global WDT freeze request

(when allowed) or because of the assertion of the global timer freeze request

18 0x0 ERRORFORCED:

1b indicates that the error reported to HSM is forced active for testing purpose

17 0x0 STICKYENABLED:

1b when the counter is enabled and cannot be disabled, set by StickyStart command, cleared by reset only.

16 0x0 CURRENTERROR:

Current error reported to HSM, this is the output after combining the functional and forced error paths

14:12 0x0

CURRENTEXPIRATIONCOUNT:

Current expiration level, cleared by Start command, saturating at 5.

11:4 0x0

CURRENTCOUNT:

Current value of the down counter, reloaded with Period by Start command.

3 0x0

WAKECOLDSTATUS:

Redefined as the status of the wake cold signal for the AO WDT, RemoteInterruptStatus for a standard WDT,

cleared by Start command

2 0x0 WAKESTATUS:

Redefined as the status of the wake signal for the AO WDT, LocalFIQStatus for a standard WDT,

cleared by Start command.

1 0x0 LOCALINTERRUPTSTATUS:

Current status of local interrupt, cleared by Start command.

0 0x0

ENABLED:

1b when the counter is active. When Enabled is 1b, the configuration of the WDT is frozen by silently

ignoring write attempts to the configuration registers: WDTCR, WDTSCR and WDTFWCR.

Set by Start or StickyStart commands, cleared by Disable when StickyEnabled is 0b.

Set by Start command, cleared by Disable.

RTC2_AOWDTCMDR_0

Always On Watchdog Timer Command Register

Offset: 0x108

Read/Write: R/W

Parity Protection: N

SCR Protection: AOWDTSCR_0

Reset: 0x00000000 (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,0000)

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Bit Reset Description

3 0x0

FORCEERROR:

Only working if the Command register is unlocked. 1b sets an internal flop that is ORED with the

functional error signal (based on threshold), 0b clears the bit. The state of the flop is shown

in the status register.

2 0x0 STICKYSTART:

Qualifies the StartCounter bit, if both bits are 1b, the counter is enabled in permanent fashion, i.e.

it remains enabled until the next reset, and a disable counter operation has no effect.

Ignored if StartCounter is 0b

1 0x0

DISABLECOUNTER:

Only working if the disable unlock register has been programmed before with the correct pattern.

Writing to the command register always clears the disable unlock register. If written to 1b,

while StartCounter is 0b and the unlock register contains the unlock

pattern, the watchdog transitions back to disabled.

0 0x0

STARTCOUNTER:

When written to 1b, enable the counter operation, load the counter with Period and starts downcounting,

resets the expiration count to 0 and clears all status flags. Enabled is always 1b after this.

This is also used as Restart.

RTC2_AOWDTUR_0

Always On Watchdog Timer Unlock Register

Offset: 0x10c

Read/Write: R/W

Parity Protection: N

SCR Protection: AOWDTSCR_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 UNLOCKPATTERN:

When ChallengeResponseEnable is 0b, Unlock must be written with value 0x0000_C45A to allow a write to

DisableCounter to take effect.

The UnlockPattern is reset at each write to the Command register.

When ChallengeResponseEnable is 1b, read of the Unlock pattern returns the current value of a LFSR,

and writing the next value of the LFSR allows a write to the Command register.

RTC2_AOWDTSCOR_0

Always On Watchdog Timer Skip Configuration Register

Offset: 0x110

Read/Write: R/W

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Parity Protection: N

SCR Protection: AOWDTSCR_0

Reset: 0x00000000 (0bxxxx,xxxx,xxxx,xxxx,x000,x000,x000,x000)

Bit Reset Description

14:12 0x0

SKIP3:

Skip Value at Expiration count 3

10:8 0x0 SKIP2:

Skip Value at Expiration count 2

6:4 0x0 SKIP1:

Skip Value at Expiration count 1

2:0 0x0 SKIP0:

Skip Value at Expiration count 0

RTC2_AOWDTFWCR_0

Watchdog Timer Fine Window Configuration Register

Offset: 0x114

Read/Write: R/W

Parity Protection: N

SCR Protection: AOWDTSCR_0

Reset: 0x00000000 (0bxxxx,xxxx,xxxx,x000,xxxx,xxxx,0000,0000)

Bit Reset Description

18:16 0x0

STARTLEVEL:

If restart (i.e. start while WDT is already enabled) is attempted and windowing operation is enabled, restart is

rejected if current expiration < StartLevel

7:0 0x0 STARTCOUNT:

If restart (i.e. start while WDT is already enabled) is attempted and windowing operation is enabled and

current expiration level == StartLevel, restart is rejected if current downcounter > (Period - StartCount).

StartCount is the number of cycles where rejection takes place at the start of that level.

RTC2_CLK_OVR_ON_0

Offset: 0x118

Read/Write: R/W

Parity Protection: N

SCR Protection: RTCSCR_0

Reset: 0x00000000 (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxx0)

Bit Reset Description

0x0

RTC:

SLCG override bit.

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Bit Reset Description

= DISABLE0

= ENABLE1

Time Stamp Counter System Control Registers

TSC_SYSCTR0_CNTCR_0

Counter Control Register

Offset: 0x0

Read/Write: See table below

Parity Protection: N

Secure: Trust Zone Protected

Reset: 0x00000000 (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxx0,xxxx,xx00)

Bit R/W Reset Description

8 RO 0x0

FCREQ:

Requested frequency modes table entry.

This bit is not used since we only support one frequency for TSC.

1 RW 0x0 HDBG:

Halt-on-debug. Controls whether a Halt-on-debug signal halts the system counter

0: System counter ignores Halt-on-debug.

1: Asserted Halt-on-debug signal halts system counter update.

= DISABLE0

= ENABLE1

0 RW 0x0 EN:

Enables the timestamp system counter

0: System counter disabled

1: System counter enabled

When this bit changes from '0' to '1', the master TSC is loaded with the CNTCVx registers value,

and starts incrementing from that value. Slave TSC may also start counting depending on

STSCCR.DIS, a field in a TSC implementatin register, see artsc.h

When this bit is '0', master and slave TSC do not count and maintain their value.

= DISABLE0

= ENABLE1

TSC_SYSCTR0_CNTSR_0

Counter Status Register

Offset: 0x4

Read/Write: RO

Parity Protection: N

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Secure: Trust Zone Protected

Reset: 0x00000000 (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxx0,xxxx,xx0x)

Bit Reset Description

8 0x0

FCACK:

Frequency change acknowledge

always 0 as only one frequency is exposed to the ARM architectural registers.

1 0x0 HDBG:

Indicates whether the counter is halted because the Halt-on-Debug signal is asserted:

0: Counter is not halted.

1: Counter is halted.

= DISABLE0

= ENABLE1

TSC_SYSCTR0_CNTCV0_0

Counter Count Value[31:0] Register

Offset: 0x8

Read/Write: R/W

Parity Protection: N

Secure: Trust Zone Protected

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

CV:

Counter value[31:0]

Read of this provides the slave TSC[31:0] value at the time of read.

When CNTCR[EN]=0, then write to this register is used to initialize the master TSC[31:0] value.

When CNTCR[EN]=1, then write to this register will have unpredictable behavior.

TSC_SYSCTR0_CNTCV1_0

Counter Count Value[63:32] Register

Offset: 0xc

Read/Write: R/W

Parity Protection: N

Secure: Trust Zone Protected

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0

0x0

CV:

Counter value[63:32]

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Bit Reset Description

Read of this provides the slave TSC[63:32] value at the time of read.

When CNTCR[EN]=0, then write to this register is used to initialize the master TSC[63:32] value.

When CNTCR[EN]=1, then write to this register will have unpredictable behavior.

TSC_SYSCTR0_CNTFID0_0

Frequency table entry register

Offset: 0x20

Read/Write: R/W

Parity Protection: N

Reset: 0x01dcd650 (0b0000,0001,1101,1100,1101,0110,0101,0000)

Bit Reset Description

31:0 0x1dcd650

FV:

Counter frequency value in Hz. Default is set to 31.25Mhz.

Note this register can be written only once

TSC_SYSCTR0_CNTFID1_0

Frequency table end marker

Offset: 0x24

Read/Write: RO

Parity Protection: N

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

FV:

Counter frequency value end marker (all-0 read-only)

TSC_SYSCTR0_COUNTERID4_0

COUNTERID11-0 registers are read-only, but to be able to initialize them at boot (by ARM7 or main CPU)

they are defined as write once. This allows if wanted to emulate the ID as defined by ARM.

Offset: 0xfd0

Read/Write: R/W

Parity Protection: N

Reset: 0x00000000 (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,0000,0000)

Bit Reset Description

7:0 0x0 VALUE:

Peripheral ID value

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TSC_SYSCTR0_COUNTERID5_0

Offset: 0xfd4

Read/Write: RO

Parity Protection: N

Secure: Trust Zone Protected

Reset: 0x00000000 (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,0000,0000)

Bit Reset Description

7:0 0x0

RESERVED:

reserved, a read will give all '0's

TSC_SYSCTR0_COUNTERID6_0

Offset: 0xfd8

Read/Write: RO

Parity Protection: N

Secure: Trust Zone Protected

Reset: 0x00000000 (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,0000,0000)

Bit Reset Description

7:0 0x0 RESERVED:

reserved, a read will give all '0's

TSC_SYSCTR0_COUNTERID7_0

Offset: 0xfdc

Read/Write: RO

Parity Protection: N

Secure: Trust Zone Protected

Reset: 0x00000000 (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,0000,0000)

Bit Reset Description

7:0 0x0 RESERVED:

reserved, a read will give all '0's

TSC_SYSCTR0_COUNTERID0_0

Offset: 0xfe0

Read/Write: R/W

Parity Protection: N

Reset: 0x00000000 (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,0000,0000)

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Bit Reset Description

7:0 0x0 VALUE:

Peripheral ID value

TSC_SYSCTR0_COUNTERID1_0

Offset: 0xfe4

Read/Write: R/W

Parity Protection: N

Reset: 0x00000000 (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,0000,0000)

Bit Reset Description

7:0 0x0

VALUE:

Peripheral ID value

TSC_SYSCTR0_COUNTERID2_0

Offset: 0xfe8

Read/Write: R/W

Parity Protection: N

Reset: 0x00000000 (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,0000,0000)

Bit Reset Description

7:0 0x0 VALUE:

Peripheral ID value

TSC_SYSCTR0_COUNTERID3_0

Offset: 0xfec

Read/Write: R/W

Parity Protection: N

Reset: 0x00000000 (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,0000,0000)

Bit Reset Description

7:0 0x0

VALUE:

Peripheral ID value

TSC_SYSCTR0_COUNTERID8_0

Offset: 0xff0

Read/Write: R/W

Parity Protection: N

Reset: 0x00000000 (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,0000,0000)

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Bit Reset Description

7:0 0x0 VALUE:

Component ID value

TSC_SYSCTR0_COUNTERID9_0

Offset: 0xff4

Read/Write: R/W

Parity Protection: N

Reset: 0x00000000 (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,0000,0000)

Bit Reset Description

7:0 0x0 VALUE:

Component ID value

TSC_SYSCTR0_COUNTERID10_0

Offset: 0xff8

Read/Write: R/W

Parity Protection: N

Reset: 0x00000000 (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,0000,0000)

Bit Reset Description

7:0 0x0

VALUE:

Component ID value

TSC_SYSCTR0_COUNTERID11_0

Offset: 0xffc

Read/Write: R/W

Parity Protection: N

Reset: 0x00000000 (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,0000,0000)

Bit Reset Description

7:0 0x0 VALUE:

Component ID value

Time Stamp Counter System Control Registers Continued

The status registers are simply some of control registers readable via CNTReadBase base address by secure

or non-secure accesses.

These are the same physical registers which are described in control register section (tsc_sysctr0).

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TSC_SYSCTR1_CNTCV0_0

Counter Count Value[31:0] Register

Offset: 0x8

Read/Write: RO

Parity Protection: N

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 CV:

Counter value[31:0]

TSC_SYSCTR1_CNTCV1_0

Counter Count Value[63:32] Register

Offset: 0xc

Read/Write: RO

Parity Protection: N

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

CV:

Counter value[63:32]

TSC_SYSCTR1_COUNTERID4_0

Offset: 0xfd0

Read/Write: RO

Parity Protection: N

Reset: 0x00000000 (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,0000,0000)

Bit Reset Description

7:0 0x0 VALUE:

Peripheral ID value

TSC_SYSCTR1_COUNTERID5_0

Offset: 0xfd4

Read/Write: RO

Parity Protection: N

Reset: 0x00000000 (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,0000,0000)

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Bit Reset Description

7:0 0x0 RESERVED:

reserved, a read will give all '0's

TSC_SYSCTR1_COUNTERID6_0

Offset: 0xfd8

Read/Write: RO

Parity Protection: N

Reset: 0x00000000 (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,0000,0000)

Bit Reset Description

7:0 0x0 RESERVED:

reserved, a read will give all '0's

TSC_SYSCTR1_COUNTERID7_0

Offset: 0xfdc

Read/Write: RO

Parity Protection: N

Reset: 0x00000000 (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,0000,0000)

Bit Reset Description

7:0 0x0 RESERVED:

reserved, a read will give all '0's

TSC_SYSCTR1_COUNTERID0_0

Offset: 0xfe0

Read/Write: RO

Parity Protection: N

Reset: 0x00000000 (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,0000,0000)

Bit Reset Description

7:0 0x0 VALUE:

Peripheral ID value

TSC_SYSCTR1_COUNTERID1_0

Offset: 0xfe4

Read/Write: RO

Parity Protection: N

Reset: 0x00000000 (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,0000,0000)

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Bit Reset Description

7:0 0x0

VALUE:

Peripheral ID value

TSC_SYSCTR1_COUNTERID2_0

Offset: 0xfe8

Read/Write: RO

Parity Protection: N

Reset: 0x00000000 (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,0000,0000)

Bit Reset Description

7:0 0x0 VALUE:

Peripheral ID value

TSC_SYSCTR1_COUNTERID3_0

Offset: 0xfec

Read/Write: RO

Parity Protection: N

Reset: 0x00000000 (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,0000,0000)

Bit Reset Description

7:0 0x0 VALUE:

Peripheral ID value

TSC_SYSCTR1_COUNTERID8_0

Offset: 0xff0

Read/Write: RO

Parity Protection: N

Reset: 0x00000000 (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,0000,0000)

Bit Reset Description

7:0 0x0 VALUE:

Component ID value

TSC_SYSCTR1_COUNTERID9_0

Offset: 0xff4

Read/Write: RO

Parity Protection: N

Reset: 0x00000000 (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,0000,0000)

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Bit Reset Description

7:0 0x0 VALUE:

Component ID value

TSC_SYSCTR1_COUNTERID10_0

Offset: 0xff8

Read/Write: RO

Parity Protection: N

Reset: 0x00000000 (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,0000,0000)

Bit Reset Description

7:0 0x0 VALUE:

Component ID value

TSC_SYSCTR1_COUNTERID11_0

Offset: 0xffc

Read/Write: RO

Parity Protection: N

Reset: 0x00000000 (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,0000,0000)

Bit Reset Description

7:0 0x0 VALUE:

Component ID value

Time Stamp Counter Registers

TSC_MTSCACR_0

Offset: 0x0

Read/Write: R/W

Parity Protection: Y

SCR Protection: TSCSCR_0

Reset: 0x00000002 (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,0000,xx10)

Bit Reset Description

7:4 0x0 ABS:

Adjust Bit Select, an edge on MTSC[9+ABS] triggers one adjust operation

1 0x1 DIR:

Direction of the adjustment, 0 indicates A0 = -1, 1 indicates A0 = +1

0x0

EN:

Enables frequency error correction

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Bit Reset Description

= DISABLE0

= ENABLE1

TSC_MTSCADR_0

Offset: 0x4

Read/Write: R/W

Parity Protection: Y

SCR Protection: TSCSCR_0

Reset: 0x00000000 (0bxxxx,0000,0000,0000,xxxx,0000,0000,0000)

Bit Reset Description

27:16 0x0 D1:

Parameters defining the adjust frequency for the master TSC NCO

11:0 0x0 N1:

Parameters defining the adjust frequency for the master TSC NCO

TSC_MTSCANNR_0

Offset: 0x8

Read/Write: R/W

Parity Protection: Y

SCR Protection: TSCSCR_0

Reset: 0x056503b9 (0bxxxx,0101,0110,0101,xxxx,0011,1011,1001)

Bit Reset Description

27:16 0x565 M0:

Parameters defining the numerator of the master TSC NCO

11:0 0x3b9

R0:

Parameters defining the numerator of the master TSC NCO

TSC_MTSCANDR_0

Offset: 0xc

Read/Write: R/W

Parity Protection: Y

SCR Protection: TSCSCR_0

Reset: 0x00000800 (0bxxxx,xxxx,xxxx,xxxx,xxxx,1000,0000,0000)

Bit Reset Description

11:0 0x800

D0:

The denominator of the master TSC NCO.

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TSC_MTSCCNTCV0_0

Master TSC Counter Count Value Register

Offset: 0x10

Read/Write: RO

Parity Protection: N

SCR Protection: TSCSCR_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 CV:

Read of this register provides Master TSC[31:0] value at the time of read (after synchronization to APB

clock).

TSC_MTSCCNTCV1_0

Master TSC Counter Count Value Register

Offset: 0x14

Read/Write: RO

Parity Protection: N

SCR Protection: TSCSCR_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

CV:

Read of this register provides {8h0,Master TSC[55:32]} value at the time of read (after synchronization to

APB clock).

TSC_STSCCR_0

Slave TSC Control Register

Offset: 0x100

Read/Write: R/W

Parity Protection: See table below

SCR Protection: TSCSCR_0

Reset: 0x00000000 (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxx0,xx0x,0000)

Bit Parity

Protection

Reset Description

0x0

FCREQ:

Frequency Change request, note that the bit with same name in the ARM registers is RO as the

notional TSC update frequency is constant.

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Bit Parity

Protection

Reset Description

When this bit changes value, it triggers the HW state machine that switches the clock paths,

normally resulting in a change of the frequency of RefClk.

The change is completed when STSCSR.FCACK returns the same value as STSCCR.FCREQ.

5 Y 0x0

FCREQ_DISABLE:

Do not trigger the HW state machine triggered at a change of STSCCR.FCREQ,

This allows for an alternate SW based clock change.

= DISABLE0

= ENABLE1

3 Y 0x0 SRC:

If FP is 1b, indicates which RefClk source path is selected.

2 Y 0x0 FP:

Force the source selection value for RefClk, overriding STSCCR.FCREQ, for debug purpose.

The selected path is controlled by the next field.

1 Y 0x0

DIS:

Disable, combined with the CNTCR.EN field, the slave TSC increments when CNTCR.EN is 1

and STSCCR.DIS is 0.

0 N 0x0 INIT:

Force the slave TSC to take its value from the master TSC. The transfer from master TSC to

slave TSC occurs once for each write of this bit to 1, the value returned is always 0.

SW must trigger INIT at least once before enabling the serial distribution of TSC (via TSCDCR.

EN),

at least 5 cycles of the 32,768Hz clock after enabling MTSC (i.e. enabling TSC itself) at cold

boot,

and at least 5 cycles of the reference clock after the reference is correctly configured.

TSC_STSCRSR_0

Slave TSC Reference Selection Register

Offset: 0x104

Read/Write: R/W

Parity Protection: Y

SCR Protection: TSCSCR_0

Reset: 0x00000000 (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xx00)

Bit Reset Description

0x0

RANGE:

Select between two lock ranges. used when FR == 0b. The lock range is proportional to the frequency of

adjust request:

When 0b, send adjust request at 32,768Hz, this does not work well with the recommended configuration, with

lock range about 1.4 ppm.

When 1b, send adjust request at TSC ref clk frequency divided by 8, lock range is about 160 ppm for

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Bit Reset Description

recommended configuration.

= SMALL0

= LARGE1

0 0x0

FR:

Free Running , controls the slave TSC dynamical lock behavior.

When 0b the Slave TSC locks itself on Master TSC, recommended mode.

When 1b the Slave TSC operates independently of Master TSC after initialization.

= LOCKEN0

= LOCKDIS1

TSC_STSCIR0_0

Slave TSC Increment Register0

Offset: 0x108

Read/Write: R/W

Parity Protection: Y

SCR Protection: TSCSCR_0

Reset: 0x00000001 (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,0001)

Bit Reset Description

3:0 0x1 K:

TSC is incremented by K at each update clock edge, programming 0 is allowed and freeze the slave TSC

without stopping RefClk.

One register per path for the RefClk source. This is for osc clock path.

K values different than 1 are not valid.

TSC_STSCIR1_0

Slave TSC Increment Register1

Offset: 0x10c

Read/Write: R/W

Parity Protection: Y

SCR Protection: TSCSCR_0

Reset: 0x00000001 (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,0001)

Bit Reset Description

3:0 0x1

TSC is incremented by K at each update clock edge, programming 0 is allowed and freeze the slave TSC

without stopping RefClk.

One register per path for the RefClk source. This is for osc clock path.

K values different than 1 are not valid.

TSC_STSCSR_0

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Slave TSC Status Register

Offset: 0x110

Read/Write: RO

Parity Protection: N

SCR Protection: TSCSCR_0

Reset: 0x00000000 (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxx0,0000,0000)

Bit Reset Description

8 0x0 RES:

Do not use.

7:0 0x0 OFS:

Offset, difference between master and slave TSC, measured at a change of master TSC.

This is calculated as MTSC[7:0] - STSC[7:0] with the result also on 8 bits to get circular arithmetic.

TSC_TSCDCR_0

TSC Distribution Control Register

Offset: 0x114

Read/Write: R/W

Parity Protection: See table below

SCR Protection: TSCSCR_0

Reset: 0x00000000 (0bxxxx,xxxx,xxxx,0000,xxxx,xx00,x000,0000)

Bit Parity

Protection

Reset Description

19:16 Y 0x0

SYNCEP:

Period between synchronization format in exponential notation, a periodic synchronization

message is sent when TSC[10+SYNCEP] toggles from 1 to 0. Note that all bits below the

selected bit also transition from 1 to 0 at the same time.

9:8 Y 0x0 RES:

Reserved bits inserted in all synchronization messages.

6 Y 0x0 DISABLE_PERIODIC:

Disable the sending of periodic messages, SW can still force the sending of synchronization

messages via the SYNC bit.

= DISABLE0

= ENABLE1

5 N 0x0 SYNC:

Force one synchronization message at each write of this bit to 1, the value returned is always 0.

4 Y 0x0 EN:

Enable the distribution network.

= DISABLE0

= ENABLE1

3:0

0x0

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Bit Parity

Protection

Reset Description

The K value inserted in SW triggered synchronization messages, in other cases the K value in

the synchronization message is the currently active K value, with special attention at RefClk

source change.

TSC_TSCDHCR_0

TSC Distribution Halt Configuration Register

The register bits are selected to allow future extensions into up to 16 groups

Offset: 0x118

Read/Write: R/W

Parity Protection: Y

SCR Protection: TSCSCR_0

Reset: 0x00000000 (0bxxxx,xxxx,xxxx,xxx0,xxxx,xxxx,xxxx,xxx0)

Bit Reset Description

16 0x0

STOP_CPU_TSC:

Unconditionally stop the CPU terminal nodes

0 0x0 HDBG_CPU:

Halt CPU terminal nodes in debug mode

TSC_CLK_OVR_ON_0

Offset: 0x11c

Read/Write: R/W

Parity Protection: Y

SCR Protection: TSCSCR_0

Reset: 0x00000000 (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxx0)

Bit Reset Description

0 0x0 CK32K:

SLCG override bit

= DISABLE0

= ENABLE1

Microsecond Counter Registers

USEC_CNTR_USECCVR_0

USECCVR, Microsecond Counter Value Register

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Offset: 0x0

Read/Write: RO

Parity Protection: N

SCR Protection: USECSCR_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 CNT:

Number of µs pulses since last system reset

USEC_CNTR_USECCCR_0

USECCCR, Microsecond Counter Configuration Register

Offset: 0x4

Read/Write: R/W

Parity Protection: Y

SCR Protection: USECSCR_0

Reset: 0x000004bf (0bxxxx,xxxx,xxxx,xxxx,0000,0100,1011,1111)

Bit Reset Description

15:8 0x4 Dividend:

Numerator is Dividend + 1, aka N

7:0 0xbf Divisor:

Denominator is Divisor + 1, default value corresponds to 38.4 MHz OSC.

USEC_CNTR_USECCRSR_0

USECCRSR, Microsecond Counter Reference Selection Register

Offset: 0x10

Read/Write: R/W

Parity Protection: Y

SCR Protection: USECSCR_0

Reset: 0x00000001 (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xx00,xxx1)

Bit Reset Description

5:4 0x0

MBS:

STSC Bit Select, STSC[1+MBS] edge used as reference when not free running.

0 0x1 FR:

Free Running, controls the microsecond counter TSC lock behavior

= the microsecond locks the µs reference pulse to a selected bit of STSC[4:1] using the adjust signal 0

(recommended mode).

= Usec Counter counts on each edge of OSC in free running fashion (legacy mode).1

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USEC_CNTR_USECCFR_0

USECCFR, Microsecond Counter Freeze Register

Offset: 0x3c

Read/Write: R/W

Parity Protection: Y

SCR Protection: USECSCR_0

Reset: 0x00000000 (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxx0)

Bit Reset Description

0 0x0 HDBG:

Halt-on-debug. Controls whether a Halt-on-debug signal halts the microsecond and associated divider logic

= Microsecond counter ignores Halt-on-debug.0

= Asserted Halt-on-debug signal halts the ration divider, automatically stopping the microsecond counter 1

and the timing reference signals.

Care must be taken to ensure that timing reference signals are in the inactive state during halt.

USEC_CNTR_CLK_OVR_ON_0

Offset: 0x40

Read/Write: R/W

Parity Protection: Y

SCR Protection: USECSCR_0

Reset: 0x00000000 (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxx0)

Bit Reset Description

0 0x0 OSC:

SLCG override bit.

= DISABLE0

= ENABLE1

Generic Timestamping Engine (GTE) APS Registers

GTE_APS_SLICE0_TETEN_0

Offset: 0x40

Read/Write: R/W

Parity Protection: N

SCR Protection: TESCR_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0

0x0

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Bit Reset Description

MAP:

Represents the set of enabled events.

Enable map is under control of masters allowed to read the timestamp

GTE_APS_SLICE0_TETDIS_0

Offset: 0x44

Read/Write: R/W

Parity Protection: N

SCR Protection: TEDSCR_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 MAP:

Represents the set of disabled events

Disable map is assumed to be frozen during system configuration to enforce visibility rules, i.e. taking the

security model into account to hide certain signals from certain masters

GTE_APS_SLICE1_TETEN_0

Offset: 0x60

Read/Write: R/W

Parity Protection: N

SCR Protection: TESCR_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

MAP:

Represents the set of enabled events.

Enable map is under control of masters allowed to read the timestamp

GTE_APS_SLICE1_TETDIS_0

Offset: 0x64

Read/Write: R/W

Parity Protection: N

SCR Protection: TEDSCR_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0

0x0

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Bit Reset Description

MAP:

Represents the set of disabled events

Disable map is assumed to be frozen during system configuration to enforce visibility rules, i.e., taking the

security model into account to hide certain signals from certain masters

Generic Timestamping Engine (GTE) GPIO Registers

GTE_GPIO_SLICE0_TETEN_0

Offset: 0x40

Read/Write: R/W

Parity Protection: N

SCR Protection: TESCR_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

MAP:

Represents the set of enabled events.

Enable map is under control of masters allowed to read the timestamp

GTE_GPIO_SLICE0_TETDIS_0

Offset: 0x44

Read/Write: R/W

Parity Protection: N

SCR Protection: TEDSCR_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 MAP:

Represents the set of disabled events

Disable map is assumed to be frozen during system configuration to enforce visibility rules, i.e., taking the

security model into account to hide certain signals from certain masters

GTE_GPIO_SLICE1_TETEN_0

Offset: 0x60

Read/Write: R/W

Parity Protection: N

SCR Protection: TESCR_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

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Bit Reset Description

31:0 0x0 MAP:

Represents the set of enabled events.

Enable map is under control of masters allowed to read the timestamp

GTE_GPIO_SLICE1_TETDIS_0

Offset: 0x64

Read/Write: R/W

Parity Protection: N

SCR Protection: TEDSCR_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 MAP:

Represents the set of disabled events

Disable map is assumed to be frozen during system configuration to enforce visibility rules, i.e., taking the

security model into account to hide certain signals from certain masters

GTE_GPIO_SLICE2_TETEN_0

Offset: 0x80

Read/Write: R/W

Parity Protection: N

SCR Protection: TESCR_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 MAP:

Represents the set of enabled events.

Enable map is under control of masters allowed to read the timestamp

GTE_GPIO_SLICE2_TETDIS_0

Offset: 0x84

Read/Write: R/W

Parity Protection: N

SCR Protection: TEDSCR_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0

0x0

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Bit Reset Description

MAP:

Represents the set of disabled events.

Disable map is assumed to be frozen during system configuration to enforce visibility rules, i.e., taking the

security model into account to hide certain signals from certain masters

Generic Timestamping Engine (GTE) Interrupt Controller Registers

GTE_INTR_CTLR_SLICE0_TETEN_0

Offset: 0x40

Read/Write: R/W

Parity Protection: N

SCR Protection: TESCR_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 MAP:

Represents the set of enabled events.

Enable map is under control of masters allowed to read the timestamp

GTE_INTR_CTLR_SLICE0_TETDIS_0

Offset: 0x44

Read/Write: R/W

Parity Protection: N

SCR Protection: TEDSCR_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

MAP:

Represents the set of disabled events

Disable map is assumed to be frozen during system configuration to enforce visibility rules, i.e. taking the

security model into account to hide certain signals from certain masters

GTE_INTR_CTLR_SLICE1_TETEN_0

Offset: 0x60

Read/Write: R/W

Parity Protection: N

SCR Protection: TESCR_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

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Bit Reset Description

31:0 0x0

MAP:

Represents the set of enabled events.

Enable map is under control of masters allowed to read the timestamp

GTE_INTR_CTLR_SLICE1_TETDIS_0

Offset: 0x64

Read/Write: R/W

Parity Protection: N

SCR Protection: TEDSCR_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 MAP:

Represents the set of disabled events

Disable map is assumed to be frozen during system configuration to enforce visibility rules, i.e., taking the

security model into account to hide certain signals from certain masters

GTE_INTR_CTLR_SLICE2_TETEN_0

Offset: 0x80

Read/Write: R/W

Parity Protection: N

SCR Protection: TESCR_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

MAP:

Represents the set of enabled events.

Enable map is under control of masters allowed to read the timestamp

GTE_INTR_CTLR_SLICE2_TETDIS_0

Offset: 0x84

Read/Write: R/W

Parity Protection: N

SCR Protection: TEDSCR_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0

0x0

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Bit Reset Description

MAP:

Represents the set of disabled events.

Disable map is assumed to be frozen during system configuration to enforce visibility rules, i.e., taking the

security model into account to hide certain signals from certain masters

GTE_INTR_CTLR_SLICE3_TETEN_0

Offset: 0xa0

Read/Write: R/W

Parity Protection: N

SCR Protection: TESCR_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

MAP:

Represents the set of enabled events.

Enable map is under control of masters allowed to read the timestamp

GTE_INTR_CTLR_SLICE3_TETDIS_0

Offset: 0xa4

Read/Write: R/W

Parity Protection: N

SCR Protection: TEDSCR_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 MAP:

Represents the set of disabled events.

Disable map is assumed to be frozen during system configuration to enforce visibility rules, i.e., taking the

security model into account to hide certain signals from certain masters.

GTE_INTR_CTLR_SLICE4_TETEN_0

Offset: 0xc0

Read/Write: R/W

Parity Protection: N

SCR Protection: TESCR_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0

0x0

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Bit Reset Description

MAP:

Represents the set of enabled events.

Enable map is under control of masters allowed to read the timestamp

GTE_INTR_CTLR_SLICE4_TETDIS_0

Offset: 0xc4

Read/Write: R/W

Parity Protection: N

SCR Protection: TEDSCR_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

MAP:

Represents the set of disabled events.

Disable map is assumed to be frozen during system configuration to enforce visibility rules, i.e., taking the

security model into account to hide certain signals from certain masters.

GTE_INTR_CTLR_SLICE5_TETEN_0

Offset: 0xe0

Read/Write: R/W

Parity Protection: N

SCR Protection: TESCR_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 MAP:

Represents the set of enabled events.

Enable map is under control of masters allowed to read the timestamp

GTE_INTR_CTLR_SLICE5_TETDIS_0

Offset: 0xe4

Read/Write: R/W

Parity Protection: N

SCR Protection: TEDSCR_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0

0x0

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Bit Reset Description

MAP:

Represents the set of disabled events.

Disable map is assumed to be frozen during system configuration to enforce visibility rules, i.e., taking the

security model into account to hide certain signals from certain masters

GTE_INTR_CTLR_SLICE6_TETEN_0

Offset: 0x100

Read/Write: R/W

Parity Protection: N

SCR Protection: TESCR_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

MAP:

Represents the set of enabled events.

Enable map is under control of masters allowed to read the timestamp

GTE_INTR_CTLR_SLICE6_TETDIS_0

Offset: 0x104

Read/Write: R/W

Parity Protection: N

SCR Protection: TEDSCR_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 MAP:

Represents the set of disabled events

Disable map is assumed to be frozen during system configuration to enforce visibility rules, i.e., taking the

security model into account to hide certain signals from certain masters

GTE_INTR_CTLR_SLICE7_TETEN_0

Offset: 0x120

Read/Write: R/W

Parity Protection: N

SCR Protection: TESCR_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0

0x0

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Bit Reset Description

MAP:

Represents the set of enabled events.

Enable map is under control of masters allowed to read the timestamp

GTE_INTR_CTLR_SLICE7_TETDIS_0

Offset: 0x124

Read/Write: R/W

Parity Protection: N

SCR Protection: TEDSCR_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 MAP:

Represents the set of disabled events

Disable map is assumed to be frozen during system configuration to enforce visibility rules, i.e., taking the

security model into account to hide certain signals from certain masters

GTE_INTR_CTLR_SLICE8_TETEN_0

Offset: 0x140

Read/Write: R/W

Parity Protection: N

SCR Protection: TESCR_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

MAP:

Represents the set of enabled events.

Enable map is under control of masters allowed to read the timestamp

GTE_INTR_CTLR_SLICE8_TETDIS_0

Offset: 0x144

Read/Write: R/W

Parity Protection: N

SCR Protection: TEDSCR_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0

0x0

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Bit Reset Description

MAP:

Represents the set of disabled events

Disable map is assumed to be frozen during system configuration to enforce visibility rules, i.e., taking the

security model into account to hide certain signals from certain masters

GTE_INTR_CTLR_SLICE9_TETEN_0

Offset: 0x160

Read/Write: R/W

Parity Protection: N

SCR Protection: TESCR_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

MAP:

Represents the set of enabled events.

Enable map is under control of masters allowed to read the timestamp

GTE_INTR_CTLR_SLICE9_TETDIS_0

Offset: 0x164

Read/Write: R/W

Parity Protection: N

SCR Protection: TEDSCR_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0 MAP:

Represents the set of disabled events

Disable map is assumed to be frozen during system configuration to enforce visibility rules, i.e., taking the

security model into account to hide certain signals from certain masters

GTE_INTR_CTLR_SLICE10_TETEN_0

Offset: 0x180

Read/Write: R/W

Parity Protection: N

SCR Protection: TESCR_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0

0x0

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Bit Reset Description

MAP:

Represents the set of enabled events.

Enable map is under control of masters allowed to read the timestamp

GTE_INTR_CTLR_SLICE10_TETDIS_0

Offset: 0x184

Read/Write: R/W

Parity Protection: N

SCR Protection: TEDSCR_0

Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0x0

MAP:

Represents the set of disabled events

Disable map is assumed to be frozen during system configuration to enforce visibility rules, i.e., taking the

security model into account to hide certain signals from certain masters

8.4 Multi-Purpose I/O Pins and Pin Multiplexing (PinMux)

8.4.1 Overview

The Xavier series SoC pad-ring is a compilation of pads, custom cells, and related test logic along the periphery

of the die. This chapter discusses the features and capabilities of the Multi-purpose I/O (MPIO) pads, and how

to configure their multiplexing so that the same group of MPIO's can serve multiple functions for different

applications, hence Pin Multiplexing (PinMux).

Scope of this chapter:

MPIO pad types

MPIO pad controls

Pad control units

MPIO pad features such low power, back drive

Low power features of MPIO pads

PinMux scheme

Generic programming considerations of pad controls

Default pin states and pull up/down selection

Misc system arch aspects applicable to MPIO pads

Registers for PinMux selection, I/O capabilities including electrical control settings.

PinMux allows a single MPIO pad or a group of MPIO pads to be used by multiple low-speed I/O controllers,

including the GPIO controller. Depending on the platform use case, the PinMux logic can be programmed

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/configured to allow any specific controller the exclusive use of the assigned MPIOs. The configuration is static

and determined by Xavier system platform requirements. With Pin Multiplexing, the total number of I/Os

required for Xavier can thus be optimized.

The PinMux scheme include multiple groups of MPIO pads, each of which is shared by a number of low-speed I

/O controllers, including the GPIO controller. A Pad control unit with configuration registers is associated with

each of these MPIO pads groups to achieve the following:

PinMux selection (selecting specific controller for its exclusive use of the group of MPIO pads)

I/O capabilities of the MPIO pads group

Electrical settings of the MPIO pads group

Notes:

Details of the MPIO pads are not discussed except for their usage and features.

Refer to the corresponding chapters of the various Low-speed Interfaces which are connected to the PinMux logic for

specific programming sequences.

High-Speed I/O (HSIO) interfaces such as PCIe, USB3.x, SATA, UFS, and SLVS do not use MPIO pads, do not

support pinmuxing, and are not discussed in this chapter. Refer to the HSIO Cluster chapter and related HSIO

Complex chapters for related features and programming guidelines.

The following diagram illustrates how PinMux multiplexes different Xavier I/O signals (UART, I S, SPI, and

PWM) to use one common MPIO pad (group).

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Figure 8.20 PinMux Illustration

Standard and Compatibility

Xavier's MPIO pads used in Pin Multiplexing support various low-speed interfaces as well as control sidebands

for high-speed interfaces. Each of the MPIO pad types is designed to comply with the interface standards

including their electrical specifications. The table below lists the MPIO pad types and the interfaces they

support.

Table 8.28 MPIO Pad Types and Their Supported Interfaces

MPIO Pad Type MPIO Pad Name Supported Interfaces/Devices

ST BDPGLP

UART, SPI, I S, Various peripheral sideband GPIOs

CZ BDSDMEM

SD, SDIO, EMMC, I S, CAN

DD BDPGLPHVIN

I C, PCIe sidebands, SPI, UART, DP-AUX sidebands, HDMI CEC, USB VBUS controls

LV_CZ BDSDMEMLV QSPI, RGMII, UFS sidebands

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MPIO Pad Type MPIO Pad Name Supported Interfaces/Devices

JT_RST BILPRST JTAG

For details of how these supported standards are implemented in Xavier, refer to the relevant LSIO and HSIO

chapters in this TRM.

Glossary

Note that different names may end up in the same acronym when the entire Xavier TRM is put in perspective.

The acronyms listed here are within the context of the Multi-Purpose I/O Pins and Pin Multiplexing chapter.

Term Definition

AON I/O Rails I/O rails VDDIO_SYS,VDDIO_AO and VDDIO_AO_HV serving as AON cluster logic are referred as AON I/O rails

CZ Controlled Impedance Pad

DD Dual Driver CMOS Pad

DPD Deep Power Down (Pad Low-Power Mode)

GPIO General Purpose I/O

HPD Hot Plug Detect

HSIO High-Speed I/O

LSIO Low-Speed I/O

LV Low Voltage Pad

MPIO Multi Purpose I/O

OD Open Drain/Over Drive

PAD Group Collection of pads sharing the same I/O supply/power ball

Padlet Logical group of pads sharing I/O voltage along with pad control registers, PinMux logic, test logic such as -

boundary scan, etc.

SFIO Special Functional I/O (indicating that the specific I/O pin meant for some functional interface connected with

Hardware IP controller)

ST Standard CMOS Pad

Relevant Chapters in the TRM

Address Map

Controller Area Network (CAN)

Clock Controller and Reset (CAR)

Hardware Safety Manager (HSM)

High-Speed I/O Cluster (HSIO)

I C Controller

MIPI M-PHY (MPHY)

Memory SubSystem (MSS)

NVLink Complex (NVLink)

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PCIe Complex (PCIe)

Pulse Width Modulation (PWM)

Quad Serial Peripheral Interface (QSPI)

SATA Complex (SATA)

Serial Peripheral Interface (SPI)

SD and MMC Controller (SDMMC)

Universal Asynchronous Receiver/Transmitter (UART)

Universal Flash Storage Complex (UFS)

USB Complex (USB)

MPIO Pad Features

PinMux MPIO pads

Output Driver

Tri-state capability

Drive strength controls

Push-pull mode, Open-drain mode, or both

Input Receiver

Schmitt mode, CMOS mode, or both

Weak pull-up and weak pull-down

Table 8.29 MPIO Pad Types

Pad/PHY

Type

I/O Rail

Voltage

Input

Buffer

Output Buffer I/O Voltage

Tolerance

Nominal Pull

Strength

Slew Rate

Control

Drive

Strength

Control

Pad Name

ST 1.8V Schmitt

and

CMOS

Push-pull and

open drain

(emulation

mode)

VDDIO 100 K ±15% No 5-bits, up

and down

BDPGLP_*

CZ 1.8/3.3V Schmitt

and

CMOS

Push-pull VDDIO 20 K ±35% 2-bits, up

and down

7-bits, up

and down

BDSDMEM_*

DD 1.8V Schmitt

and

CMOS

Push-pull and

Open Drain

3.3V for

Open Drain,

VDDIO

otherwise

100 K No 5-bits, up

and down

BDPGLPHVIN_

LV_CZ 1.8 V/1.2V Schmitt

and

CMOS

Push-pull VDDIO 18 K ±30% 2-bits, up

and down

5-bits, up

and down

BDSDMEMLV_

The Standard (ST) MPIO pads are the most common pads on the chip. They are used for typical General

Purpose I/O, and various slow speed interfaces.

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The Dual-driver (DD) MPIO pads are like the ST pads with the additional provision of tolerating I/O swing up to

3.3V as long as the pad’s output-driver is set to open-drain mode. There are special power-sequencing

considerations when using this functionality to ensure the pads operate without any damage/reliability issues.

They are used for open drain mode interfaces – I C, USB VBUS, PCIe side bands, HDMI CEC and Display

HPD signals.

The Controlled output impedance (CZ) MPIO pads are optimized for use in applications requiring tightly

controlled output impedance. They are like ST pads except for changes in the drive strength circuitry and in the

weak pull-ups/-downs. Circuitry within Xavier continually matches the output impedance of the CZ pads to the

on-board pull-up resistors attached to the CZ_COMP pad.

The Low Voltage Controlled Impedance (LV_CZ) pads are like CZ pads but optionally support for use with a 1.2

V supply voltage (and signaling level).

Special Purpose Pad Types

Beyond pad types covered so far, we have some special purpose pads used for targeted purpose. Note these

special purpose MPIO pads are different from PHYs used for high speed differential interfaces like USB,

Display etc.

Table 8.30 Special Purpose Pad Types

Pad I/O Rail

Voltage

Functional

Name

Brief Description Pad Name

MEM_COMP 1.8/3.3V SDMMC

Calibration

Pads

Used for generating PVT compensated impedance calibration code for

the SDMEM pads (typically used for interfacing SDMMC devices). It is

connected to GND external reference resistor of 50 Ohm with ± 1%

variation.

BDSDMEMCOMP_

MEMLV_COM

1.8V eMMC

Calibration

Pads

Same as MEM_COMP but can operated at lower I/O voltage. BSDMEMLVCOMP

JT_RST 1.8V JTAG and

Reset

Pads

(Input

Only)

Used for JTAG (except JTAG TDO) and Reset interface.

Has a special mode of operation called VDD only mode where in the

pad becomes operational without having the I/O rail up. This mode of

operation is needed for Reset pads which must propagate the reset

before I/O rails are up. This is achieved by Logic0 tie-off to

RCVR_SEL pin of this pad.

Beyond SYS_RESET_N pin, JTAG pin, JTAG mode selection pins

also follow similar usage with tie-off to RCVR_SEL pad input.

BILPRST_*

MPIO Pad Variations

Within each standard MPIO pad types there are variations that are mainly associated with the way how pads

behave during DPD mode and availability some specific features in DPD. There are three distinct types of

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variations in each type. Based on the functional and power choices appropriate Pad type shall be chosen for

each pin.

Table 8.31 MPIO Pad Variations

S.No Input

Receiver in

DPD

Output

Values

PU/PD

Availability

During DPD1

Pad Type

Extension

Usage

1 ENABLED DYNAMIC YES VDP1P1P1

Used for pins that need to be active when core supply

VDD_SOC = OFF

2 ENABLED STATIC YES VDVXP1P1

Used for pins that need to be active during chip DPD power

states.

Since the input receive is enabled, can be used for pins

used Wake events.

Lesser leakage power than *VDP1P1P1 type pads since

only input receive logic is active.

3 DISABLED STATIC YES VXVDP1P1

Since receiver is DISABLED can’t be used for signals acting

as Wake events

Consumes less leakage power of all pad variants as even

input receiver circuits are also in disabled state.

4 N/A N/A N/A R90 Pad physical orientation is North-South, default pad type

orientation is West-East.

Note 1: For DD pads PU is not available in DPD by nature of the pad.

Note 2: This variation is available only in BDPGLP_*, BDPGLPHVIN_*, BILPRST_* pads. These pads do have

DPD latching circuit like VDVXP1P1P1 pad type and support entering in to DPD mode with SEL_DPD/E_DPD

sequencing. We (earlier Xavier Arch) choose this way rather than removing the DPD latching and circuitry to be

able to have flexibility to park in a state during DPD. So structurally VDP1P1P1 and VDVXP1P1P1 pads are

same and the power domain of core side inputs is the only difference from usage POV.

Note 3: The pad type BDSDMEM_* and BDSDMEMLV_ deviates from the general MPIO pad type variation.

These types of pads have single VXVD pad type with wake capability selection through an additional pin.

When additional input pin “WAKE_PAD” tied to 1, it behaves like VDVX pad with input receiver enabled for

wake functionality.

When additional input pin “WAKE_PAD” tied to 1, it behaves like VXVD pad with receiver disabled.

MPIO Pad Low-power Modes and Features

Following is the summary of different power modes of the MPIO pads.

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Table 8.32 MPIO Pad Low-power Modes and Features

Mode Rail Status and DPD

Control Setting

Description Usage Remarks

OFF I/O Rail – OFF

VDD_RTC – OFF

VAUX_CORE – OFF

Control Inputs –Don’t

Care

Pad circuits are fully

OFF and non-

functional and

consuming zero

power.

System OFF

states

STANDBY-

NORETENTI

I/O Rail – OFF

VDD_RTC – ON

VAUX_CORE – OFF

E_DPD =1

SEL_DPD=1

Pads circuits are OFF

except for the

VDD_RTC portion of

the circuit.

Consumes minimal

leakage in the always-

on [AO] portion of the

circuit operating in

VDD_RTC.

SC7 State Specific Interface’s I/O rail can be turned OFF

and no I/O state is retained.

Since the core rail is OFF, E_DPD and

SEL_DPD should be at Logic1.

STANDBY I/O Rail – ON

VDD_RTC – ON

VAUX_CORE – OFF

E_DPD =1

SEL_DPD=1

Pads are holding the I

/O state but core rail is

OFF and hence

consuming minimal

power.

SC7 State I/O states are retained through holding latches

inside the pads

LOGICAL

DPD

I/O Rail – ON

VDD_RTC – ON

VAUX_CORE – ON

E_DPD =0

SEL_DPD=1

Pads are holding the I

/O state but core rail is

not OFF and hence

consuming normal

power.

Transitory state

and I/O values

are retained.

No power benefit in this mode since core rail is

ON. However, software can possibly go through

this state as and when the interface is becoming

IDLE to reach the STANDBY state

It happens with software sequences for power

saving to DPD state.

LOGICAL

DPD- I/O

OFF

I/O Rail – OFF

VDD_RTC – ON

VAUX_CORE – ON

E_DPD =0

SEL_DPD=1

Pads are not holding

the I/O state but core

rail is not OFF and

hence consuming

normal power.

Transitory state

and I/O Values

are not retained.

Used by the software to transit from STANDBY-

NO RETENTION to Functional Status Inactive

state.

INACTIVE

I/O Rail – OFF

VDD_RTC – ON

Pads are functional

from Core side but I/O

rails are kept OFF

This happens when I/O rails are powering up

time windows during system active-low power

states.

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Mode Rail Status and DPD

Control Setting

Description Usage Remarks

VAUX_CORE – ON

E_DPD =0

SEL_DPD=0

Transitory state

needed to for

transitioning to

low power states.

FUNCTIONA

ACTIVE

I/O Rail – ON

VDD_RTC – ON

VAUX_CORE – ON

E_DPD =0

SEL_DPD=0

Normal mode and

pads consume both

Static and Dynamic

power

Normal functional

usage

MPIO Pad Electrical Control Features

General purpose pads support features to cater electrical requirements of multiple slow speed interfaces and

GPIO pins. Following provides list of such features common to all MPIO pads. Further complete list of electrical

features by pad type are covered in Electrical Controls section.

Weak Pull-up: I/O driver pulls up the line irrespective of pull-up resistor on board.

Maps to PUPD bit field in pad control register.

Weak Pull-down: I/O driver pulls down the line irrespective of pull-up resister on board.

Maps to PUPD bit field in pad control register.

Programmable Output pull-up/pull-down drive strength: Enables to program different drive strengths required by

different external bridges, codecs, and such devices in the system.

Maps to CFG_CAL_DRVUP/DN fields in pad control register.

Schmitt receiver: Enables Schmitt receiver in input receiver circuit. Enabling Schmitt provides better noise margin

characteristics for the input and depending on driver’s logic threshold levels this can be enabled.

Maps to E_SCHMT bit field in pad control register.

Input receiver: Controls whether the input path (receiver portion of I/O driver) is enabled or not. Generally disabled for

most of the pads except those needed for boot.

Maps to E_INPUT bit field in pad control register.

pad output state: Top Level override to float Pad Output irrespective of the actual PinMux Control. Useful to get the

correct default values and while switching PinMux to GPIO mode of operation (though such switching is not

recommended in general).

Maps to TRISTATE bit field in pad control register.

TRISTATE = 0x0: i.e., Pad I/O driver is DRIVEN (Some of the critical pads typically PMIC interface pads, clock

pads etc., the Default status are driven to ensure correct values are driven to PMIC or external device)

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TRISTATE = 0x1: i.e., Pad I/O drive is FLOATED (actual value on the pad output depends on the Weak Pullup

/Pulldown control in the respective PUPD fields.

Boot Loader software enables this field to driven state before starts using the pad in output mode. Same applies

to peripheral interface drivers which shall configure pad control fields during the interface initialization. Other

than PMIC Interface related pads, Power On Reset default is FLOATED so that any unused pin comes with

OUTPUT FLOATED/Weak PU/PD state.

Electrical Controls

Below is summary of electrical controls of MPIO pads. All these electrical controls are configurable through pad

control registers. For more details of electrical controls or more pad types, refer to pad control registers.

Table 8.33 BDSDMEM Electrical Controls (BDSDMEM Variants)

Signal

Name

In/Out Power

Domain

Description

E_INPUT In VDD_SOC

/VDD_RT

Enables receiver path I/O ZI/TZI

E_SCHMT In VDD_SOC

/VDD_RT

Enables Schmitt trigger in the receiver

E_LPBK In VDD_SOC

/VDD_RT

Enables loopback mode A -> ZI/TZI

DRV_TYP

E_[0]

In VDD_SOC

/VDD_RT

1x/2x I/O driver selection

DRV_TYP

E_[1]

In VDD_SOC

/VDD_RT

Drive codes selection: COMP pad driven codes or pad default codes.

DRVUP_D

EF_[1:0]

In VDD_SOC

/VDD_RT

Back-up default driver output pull-up control code.

Applied Drive up/down codes - [0, 1, DRVUP_DEF [1], DRVUP_DEF[0], 0]

DRVDN_D

EF_[1:0]

In VDD_SOC

/VDD_RT

Back-up default driver output pull-down control code.

Applied Drive up/down codes - [0, 1, DRVDN_DEF [1], DRVDN_DEF[0], 0]

E_PULLU In VDD_SOC

/VDD_RT

Enables weak pull-up (20 K Ohm ±35%)

E_PULLD In VDD_SOC

/VDD_RT

Enables weak pull-down (20 K Ohm ±35%)

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Signal

Name

In/Out Power

Domain

Description

E_PBIAS_

BUF

VDD_SOC

/VDD_RT

Enables internally generated bias for driver PMOS in 3.3V mode. Selects strong driver with

internally generated 0.5*VDDP when VDDP is low and VCLAMP is High. Wrong setting

combination with VREF_SEL may cause electrical stress resulting in pad damage.

VREF_SE

L_[3:0]

In VDD_SOC

/VDD_RT

Select different bias levels for driver PMOS when (E_PBIAS_BUF == 1)

SCHMIT_

[1:0]

Schmitt trigger hysteresis window control

Note: VDD_SOC/ VDD_RTC power domain depends on VXVD (or VDVX)/VD* variant respectively.

Table 8.34 BDSDMEMLV Electrical Controls (BDSDMEMLV Variants)

Signal Name In/Out Power Domain Description

E_INPUT In VDD_SOC/VDD_RTC Enables receiver path I/O ZI/TZI

E_SCHMT In VDD_SOC/VDD_RTC Enables Schmitt trigger in the receiver

E_HSM In VDD_SOC/VDD_RTC Reserved.

Earlier – Enables high speed mode for the driver and receiver.

IO_RESET_N In VDD_SOC/VDD_RTC Reserved.

Earlier – Active low Reset to pad logic.

E_PREEMP In VDD_SOC/VDD_RTC Reserved.

Earlier – Pre-emphasis enable.

E_LPBK In VDD_SOC/VDD_RTC Enables loopback mode

DRV_TYPE_[0] In VDD_SOC/VDD_RTC 1x/2x I/O driver selection

DRV_TYPE_[1] In VDD_SOC/VDD_RTC Drive codes selection: COMP pad driven codes or default codes.

E_PULLU In VDD_SOC/VDD_RTC Enables weak pull-up (~18 K Ohm ±30%).

E_PULLD In VDD_SOC/VDD_RTC Enables weak pull-down (~18 K Ohm ±30%).

DRVDN_[7:0] In VDD_SOC/VDD_RTC I/O Driver Output Pull-Down drive strength code

DRVUP_[7:0] In VDD_SOC/VDD_RTC I/O Driver Output Pull-Up drive strength code

Note: VDD_SOC/VDD_RTC power domain depends on VXVD (or VDVX)/VD* variant respectively.

Table 8.35 BDPGLP, BDPGLPHVIN Electrical Controls (BDPGLP, BDPGLPHVIN Variants)

Signal

Name

In/Out Power Domain Description

E_INPUT In VDD_SOC

/VDD_RTC

Enables receiver path I/O ZI/TZI

E_SCHMT

Enables Schmitt trigger in the receiver

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Signal

Name

In/Out Power Domain Description

VDD_SOC

/VDD_RTC

E_LPBK In VDD_SOC

/VDD_RTC

Enables loopback mode A -> ZI/TZI

E_PULLU In VDD_SOC

/VDD_RTC

Enables weak pull-up (~100 K Ohm ±15%)

E_PULLD In VDD_SOC

/VDD_RTC

Enables weak pull-down (~100 K Ohm ±15%)

DRVDN[4:

In VDD_SOC

/VDD_RTC

I/O Driver Output Pull-Down drive strength code

DRVUP[4:

In VDD_SOC

/VDD_RTC

I/O Driver Output Pull-Up drive strength code

E_LPDR In VDD_SOC

/VDD_RTC

Disables most base driver fingers, leaving only minimal base driver finger. Enabled

for I C interface to meet slow rise/fall time spec of low speed modes.

E_IO_HV In VDD_SOC

/VDD_RTC

Enables open-drain pull-up capability to 3.3V. Enables 3.3V Receiver. Relevant for

BDPGLPHVIN* variant pad only.

Note: VDD_SOC/ VDD_RTC power domain depends on VXVD (or VDVX)/VD* variant respectively.

Table 8.36 BILPRST Electrical Controls (BILPRST_VD Variants)

Signal Name In/Out Power Domain Description

RCVR_SEL In VDD_RTC Selects between VDD-ONLY or VDD-AND-VDDP receivers.

0 => Selects VDD-ONLY Receiver

1 => Selects VDD-AND-VDDP Receiver

Power Sequence Controls

Power sequence controls are the specific controls to handle sequencing in and out of different power states a

MPIO pad supports.

Table 8.37 BDSDMEM Power Sequence Controls (BDSDMEMVD*, BDSDMEMVXVD)

Signal Name In/Out Power Domain Description

E_33V In VDD_RTC Selection of 1.8V/3.3V I/O output voltage swing.

SEL_DPD In VDD_TRC Latches state of I/O pin set by E_33V/E_PULLU/E_PULLD and data level shifters.

E_DPD In VDD_RTC Places pad in DPD mode by deactivating bias, clamping settings for DPD mode.

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Table 8.38 BDSDMEMLV Power Sequence Controls (BDSDMEMLV_VXVD)

Signal Name In/Out Power Domain Description

E_18V In VDD_RTC Selection of 1.8V/1.2V I/O output voltage swing.

SEL_DPD In VDD_TRC Latches state of I/O pin set by E_18V/E_PULLU/E_PULLD and data level shifters.

E_DPD In VDD_RTC Places pad in DPD mode by deactivating bias, clamping settings for DPD mode.

Table 8.39 EMMCIO_BRICK Power Sequence Controls (BDEMMC_IOBRICK)

Signal

Name

In/Out Power

Domain

Description

SEL_DPD In VDD_TRC Latches state of I/O pin set by E_18V/E_PULLU/E_PULLD and data level shifters. Disable Rx.

E_DPD In VDD_RTC Places pad in DPD mode by deactivating bias, clamping settings for DPD mode, and gating-

out inputs from core.

Table 8.40 BDPGLP Power Sequence Controls (BDPGLP_VD, BDPGLP_VDVX, BDPGLP_VXVD)

Signal Name In/Out Power Domain Description

SEL_DPD In VDD_TRC Latches state of I/O pin set by E_18V/E_PULLU/E_PULLD and data level shifters.

E_DPD In VDD_RTC Places pad in DPD mode by deactivating bias, clamping settings for DPD mode.

Notes:

For VD variants, all the pad inputs and outputs are in VDD_RTC power domain.

VDD_RTC/VDD_SOC power domain depends on VDVX/VXVD variant respectively.

Table 8.41 BDPGLPHVIN Power Sequence Controls (BDPGLPHVIN_VD, BDPGLP_HVIN_VDVX,

BDPGLP_HVIN_VXVD)

Signal Name In/Out Power

Domain

Description

SEL_DPD In VDD_TRC Latches state of I/O pin set by E_18V/E_PULLU/E_PULLD and data level shifters.

E_DPD In VDD_RTC Places pad in DPD mode by deactivating bias, clamping settings for DPD mode.

Notes: VDD_RTC/VDD_SOC power domain depends on VDVX/VXVD variant respectively.

Pad Control Unit

Pad control units are the APB clients with register banks for pad controls and PinMux selection. The pad

controls provide option to program the pad electrical characteristics depending on platform design and/or

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connected devices. Each pad control units consists of registers for multiple pads of a PAD group. The following

diagram shows the I/O of a Pad Control Unit.

Figure 8.21 Pad Control Unit and Its I/O

PinMux Scheme

The concept of PinMux logic is to share the same pin for multiple interfaces which aren’t active at the same time

in every platform. Sharing of pins using PinMux optimizes the number of pins required in SoC thus reducing the

cost of die. Xavier connects to various peripherals on different platforms, but not all peripherals in single

platform. Based on targeted market segment platform goals, we arrive at PinMuxing selection. Respective

platform software shall configure the pins at boot or post-boot stages prior to communication with related

peripheral devices.

PinMux option per pin consists of:

Sharing the pin with four different Special Functional I/Os (SFIOs) and one GPIO, i.e., a pin that is not required for

SFIO can be used by GPIO-driven software.

Override provision to float the pad outputs irrespective of the driving SFIO controller.

The Xavier PinMux Controller includes the logic and registers to select a pin for one of the four SFIO. The

following diagram shows the PinMux logic associated with a single MPIO pad. The diagram shows interface

with various units and polarity of the signals shown are at interface level. At pad level when ENB =1 the output

drivers are disabled.

List of PinMux IPs

The following table provides high level list of IPs connected with PinMux logic. Note that this also covers the

cases of interfaces which have only one SFIO usage (i.e., only one PinMux option) and possible to use as

GPIO pin. For signal level muxing details refer to Xavier customer PinMux sheet.

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Table 8.42 List of PinMux IPs

S. No Interface

Name/IO Rail

Brief Description PinMux Sheet Reference

1 SDMMC For Interfacing with WiFi modem etc or for the second

removable SD card.

SDMMC1, SDMMC3

2 EAVB Ethernet Audio Video Bridge EQOS

3 UART For connecting various peripherals like BT via UART and Audio

codec/FM etc via I S interfaces

I S

For various Audio Codec and Digital Speakers I2S1-I2S6

5 DMIC,

DSPKR, IQC

Digital Mic, Codec, DAB Interface DMIC1- DMIC5

DSPKR0, DSPKR1

IQC1, IQC2

I C

Inter Integrated Circult I2C1, I2C2, I2C3, I2C4, I2C5, I2C6,

I2C7, I2C8, I2C9, I2C10

7 QSPI QSPI interface QSP0*, QSPI1*

8 CAN Interface to the CAN PHY CAN0*, CAN1*

9 SPI Touch device, MCU connection, Serial Flash SPI*1, SPI2*, SPI3*

10 PWM Pulse Width Modulation PWM1-PWM8

11 DP-AUX DisplayPort Auxiliary DP_AUX_Ch0-3

Most of the PHYs for DP/HDMI, CSI/DSI interfaces don’t share the lanes with other protocols.

On the other hand, UPHY PHY supports multiple HSIO protocols USB3, UFS, PCIe, SATA, and CLVS-MC

(Sony Proprietary Camera interface). Depending on protocol usage of targeted platforms number of lanes,

number of PLLs, number of PCIe/USB3.0 controllers and related side bands is determined. For UPHY lane

sharing details of HSIO protocols refer to HSIO sections.

8.4.2 Functionality

Programmable Drive Strength Capabilities

This section summarizes the programmable drive strength capabilities of various pads in the granularity of pad

groups.

SDMEM pads which do not have calibration pad, do not have programmable drive strength registers. The

DRVUP_VCLAMP [6:0]/DRVDN_VCLAMP [6:0] codes are hard wired to corresponding power group VCLAMP and

GND respectively. Pins in below pad groups have 2-bit back up drive strength control.

AO_HV, AUDIO_HV

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SDMEMLV pads which do not have calibration pad, have programmable drive strength registers. Pins in below pad

groups:

UFS, EQOS

BDPGLP, BDPGLPHVIN pads which do not have calibration pads, have programmable drive strength registers. Pins

in below pad groups:

Rest all pad groups CONN, CAM etc. MPIO pad groups listed in customer PinMux sheet.

SDMEM pads which have calibration pad, drive strength driven by COMP pad and overriding and programmable

drive strength registers. Pins in below pad groups:

SDMMC1_HV, SDMMC3_HV

SDMEMLV pads which have calibration pad, drive strength driven by COMP pad and overriding and programmable

drive strength registers. Pins in below pad groups:

QSPI

Typical platform design goal is drive impedance is 50 Ohm for all the cases 1 through 5 above.

For all the pads that don’t have corresponding calibration pads (i.e., 1 to 3 above) the drive strength must be

programmed. Power On Reset default value in such cases typically works fine as the low interface speed and

trace design doesn’t need higher drive codes. Based on Si char tuned drive codes are recommended through

PROD flow which must be programmed by software as part respective interface initialization.

For all the pads having COMP pad (drive strength calibration) pad and hardware drive strength calibration logic,

respective interface initialization calls for drive strength calibration. Software must follow respective IP interface

initialization guides to ensure that drive strength calibration is done either one-time or periodic interval to

program the drive codes to compensate for PVT variation.

Pin-states and Default Pad Controls

Each of the Xavier I/O pin default pin-state is defined based on primary interface bus idle signal level

requirements. Other than functional interface pins, GPIO pins default pin-state is pull-down. There are few

exceptions like GPIOs used for button matrix require default pin-state to be pull-up to save external strong pull-

ups and platform cost. Ultimately, the Power On Reset field in the Xavier PinMux sheet captures this

information per pin including all the exceptions based on platform consideration.

Either during cold-boot or warm-boot power cycling, pin-states defaults to the reset values captured in the POR

field of the Xavier PinMux sheet. Following section provides the connection to reset types which has

implications to pin-states of pad controls.

Further, following per pin fields captured in the Xavier PinMux sheet are used to derive each pin pad control

field reset default values.

POR – Pin state at reset/power on.

Z (Pin tri-stated)

PU/1 (Pin pulled down)

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PD/0 (Pin pulled up)

Tristate_en

Passthrough (Pin active, i.e., driven value for output; transparent for input)

Tristate (Pin tri-stated)

PU/PD

Pad control setting pull down/pull Up is enabled for pad internal weak pull-down or pull-up.

e_input

Pad control setting to enable input receiver path which is irrespective of pad I/O direction.

e_io_hv

Pad control setting to select for 3.3V tolerance. Applicable for BDPGLPHVIN, open-drain capable pads.

e_lpdr

Pad control setting to turn of drivers inside pad. Applicable for BDPGLP and BDPGLPHVIN pad types.

Table 8.43 Resets Impacting Pin-state

Pins Reset connection

All pads on I/O rails excluding VDDIO_PWR_CTL L2 warm reset

Pads on VDDIO_PWR_CTL L1 warm reset

For the pins in VDDIO_PWR_CTL all the pad control registers, associated GPIO logic works on L1 warm reset

unlike all MPIO pads in various other groups.

GPIO Pin-state, Pad Controls Managed by software

Apart from the pin-states, pad controls coming up as reset defaults, following two cases where software

manages the pin-state, pad control based on platform configuration.

GPIO/special purpose pins which are part of I/O rails that are active during SC7 power state transitions shall be

managed by software.

GPIO/special purpose pins which are not part of Always-on I/O rails but require different pin-state vs the default pin-

state are managed by software as per customer PinMux configuration in Customer PinMux.

Back Drive Capability

A limited set of Xavier I/Os are back drive capable - they can withstand being driven by external device when

Xavier is not powered, without damaging the I/O. Xavier MPIO back drive capabilities used as low speed

interfaces, these GPIOs are:

3.3V tolerant only when Xavier's 1.8V-rail is ready (E_IO_HV == 1), under these circumstances only they can tolerate I

/O to be 3.3V.

note that this means that an external pull-up to 3.3V is supported because Xavier back drive capable I/O not

can’t tolerate 3.3V when the Xavier 1.8V I/O rail is OFF.

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1.8V fail-safe. When Xavier is powered off, this I/O can be pulled-high-1.8V, without any back-drive current.

List of interfaces supporting back drive capability at VDDP 1.8V only:

UART, I C, SPI ports (not all ports)

GPIOs (not all GPIO pins)

Below is list of MPIO variant I/Os which are back drive capable. Exact list of interface devices mapping to these I

/Os usage varies across platforms. Refer to PinMux sheet for the same.

Table 8.44 List of Low-Speed Back Drive I/Os

Signal/Pin Names Pad Type I/O Rail group

AO_RETENTION_N BDPGLPHVIN_EFCR90M14L_VDP1P1P1 VDDIO_SYS

SAFE_STATE BDPGLPHVIN_EFCR90M14L_VDP1P1P1 VDDIO_SYS

SHUTDOWN_N BDPGLPHVIN_EFCR90M14L_VDP1P1P1 VDDIO_SYS

SPI2_SCK BDPGLPHVIN_EFCR90M14L_VDP1P1P1 VDDIO_AO

SPI2_MISO BDPGLPHVIN_EFCR90M14L_VDP1P1P1 VDDIO_AO

SPI2_MOSI BDPGLPHVIN_EFCR90M14L_VDP1P1P1 VDDIO_AO

SPI2_CS0 BDPGLPHVIN_EFCR90M14L_VDP1P1P1 VDDIO_AO

UART3_TX BDPGLPHVIN_EFCR90M14L_VDP1P1P1 VDDIO_AO

UART3_RX BDPGLPHVIN_EFCR90M14L_VDP1P1P1 VDDIO_AO

SOC_GPIO07 BDPGLPHVIN_EFCR90M14L_VXVDP1P1P1 VDDIO_CAM

SOC_GPIO40 BDPGLPHVIN_EFCR90M14L_VXVDP1P1P1 VDDIO_CAM

SOC_GPIO41 BDPGLPHVIN_EFCR90M14L_VXVDP1P1P1 VDDIO_CAM

SOC_GPIO42 BDPGLPHVIN_EFCR90M14L_VXVDP1P1P1 VDDIO_CAM

SOC_GPIO43 BDPGLPHVIN_EFCR90M14L_VXVDP1P1P1 VDDIO_CAM

SOC_GPIO44 BDPGLPHVIN_EFCR90M14L_VXVDP1P1P1 VDDIO_CAM

SOC_GPIO45 BDPGLPHVIN_EFCR90M14L_VXVDP1P1P1 VDDIO_CAM

UART1_TX BDPGLPHVIN_EFCR90M14L_VXVDP1P1P1 VDDIO_CAM

UART1_RX BDPGLPHVIN_EFCR90M14L_VXVDP1P1P1 VDDIO_CAM

UART2_TX BDPGLPHVIN_EFCR90M14L_VXVDP1P1P1 VDDIO_UART

UART2_RX BDPGLPHVIN_EFCR90M14L_VXVDP1P1P1 VDDIO_UART

SPI3_SCK BDPGLPHVIN_EFCR90M14L_VDVXP1P1P1 VDDIO_UART

SPI3_MISO BDPGLPHVIN_EFCR90M14L_VXVDP1P1P1 VDDIO_UART

SPI3_MOSI BDPGLPHVIN_EFCR90M14L_VXVDP1P1P1 VDDIO_UART

SPI3_CS0 BDPGLPHVIN_EFCR90M14L_VDVXP1P1P1 VDDIO_UART

SPI3_CS1 BDPGLPHVIN_EFCR90M14L_VDVXP1P1P1 VDDIO_UART

The following table provides summary of Xavier back drive capability and limitations including high speed and

low speed interfaces.

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Table 8.45 Xavier I/O Back Drive Summary

Pad/brick

Category

Usage Back Drive Support

PEX_CLK PCIe Clock output Not required (output only)

MIPI4X* CSI Yes. There is possibility of 5.5 mA transient leakage per CSI I/O pair

DP_SINGLE eDP/DP/HDMI Not required (output only)

DP_AUX Display Sideband

Yes. Not required in DP-AUX mode, I C mode has support.

DDR I/O brick LPDDR4X, LPDDR4 No.

U-PHY/NVHS PCIe, SATA, UFS, USB3.

0, NVLink

No, see below details for specific protocol usage.

PCIe, USB3.1: A/C coupled plus covered with discovery mechanism.

SATA: A/C coupled; No issue.

UFS: D/C coupled, but this is a host managed interface.

NVLink: managed interface.

REF_CLK pairs: okay by limiting the voltage swing to 0.8V/0.9V.

USB2 No. External pull-up or driving the I/O when Xavier is not powered causes EOS and

life time reduction. But USB compliant connector system do not result in such back-

drive scenario.

MPIO pads with

1.8V

Low speed I/O, Side

bands

Yes (Refer to the List of Low-Speed Back Drive I/Os)

MPIO pads with

3.3V

Low speed I/O, Side

bands

No. Need platform workaround solutions.

External Wake Events

External wake events are I/O state change(s), which are defined as triggers to notify the Xavier SoC power

management logic to indicate the type of action needed. For example, HDMI interfaces define a pin called Hot

plug detect (HPD), and wake event associated with it. Upon a hot plug-in connection of HDMI, the event is

notified as pin-state value change on HPD pin. We define number of such external wake events to cater

multiple platform use cases. Upon I/O state change, “wake engine” logic in PMC registers the event and triggers

power manager hardware. For more details on wake event programming model, wake processing capabilities

refer to PMC section.

Xavier I/O pin supposed to capable as “Wake pin” is indicated with wake event numbering in PinMux sheet.

GPIO Ports and Controller Mapping

The following is the GPIO controller to different GPIO port mapping. All GPIOs part of such marked pin group (e.

g., all UART pin group GPIOs are associated with GPIO_CTL2) associated with mapped GPIO controller.

GPIOs in PEX_CTL_2 pin group need NVHS0_DVDD power supply.

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GPIOs in SYS, AO, and AO_HV pin group are on VDD_RTC (Ungated always-on core power supply).

GPIOs in rest of the pin groups are on Ungated VDD_SOC core power supply.

Table 8.46 GPIO's in Different Pad Control Groups

GPIO Controller Pad Control Groups GPIO Ports

GPIO_CTL0 PEX_CTL_2 (on NVHS0_DVDD) GG

GPIO_CTL1 DEBUG, AUDIO_HV A, V, W

GPIO_CTL2 UART, EDP, CAM M, N, P, Q, R, X , Y, Z

GPIO_CTL3 PEX_CTL, UFS, AUDIO K, L, S, T, U, FF

GPIO_CTL4 CONN, QSPI, EQOS, PWR_CTL B, C, D, E, F, G, H, I

GPIO_CTL5 SDMMC3_HV, SDMMC1_HV J, O

GPIO_AON SYS, AO, AO_HV, (All on VDD_RTC) AA, BB, CC, DD, EE

DPD

DPD refers to Xavier pads Deep Power Down state which may be the case during SC7 and/or such Xavier low

power states. In SC7 scenario, SoC Power i.e. VDD_SOC (same as VAUXC_CORE/VDD_SOC) rail is cut off.

Pad DPD control signal SEL_DPD assertion enable the latches inside the pad to store pad A/EN/E_PULLU

/E_PULLD pad controls. If I/O rail is on, latched values are driven out during SC7. So, the Xavier i/o state prior

to entering to SC7/low power state is retained while the pad is in DPD mode.

Essentially, I/O DPD sequencing on/off consists of:

Pads DPD mode handled by IP/PMC hardware managed.

I/O or core rail power on/off managed by software in combination with platform power tree design.

SC7 is a low-power/standby state in which Xavier maintains much of its I/O state while most of the core logic is

powered off. It’s possible that pads are transitioned in to DPD mode in many other scenarios beyond Xavier

SC7 and shall not be inferred as one-to-one correspondence. For example, some pads in DPD mode may be

completely powered down including i/o rails while others still powered. External wakes, platform back drive

usage cases are platform variant.

MPIO Pad DPD Sequence

Following diagram sequencing, timing relations of power sequence signals that are necessary to transition a

MPIO pad transition in and out of DPD mode. All MPIO pads follow same DPD sequence driven by PMC logic.

Xavier Series SoC Technical Reference Manual

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Figure 8.22 MPIO Pad DPD Sequence Diagram

DPD Controls and Mechanisms

Xavier pads and hardware support several types of DPD control mechanisms. Always-ON MPIO pads and non-

AON MPIO pads have different schemes of overriding during SC7 entry/exit. Override mechanism details to be

referred from DPD controls in PMC section, however below summary presents overview based on PMC

hardware implementation in different categories.

Categories of signals are:

Category of pads that don’t have DPD mode support at all. Pads that are associated with PMIC for system

initialization and Reset don’t enter DPD mode during SC7 are such examples.

Table 8.47 I/Os Not Supporting DPD

Type of DPD Capability I/Os Not Supporting DPD thus not Entering in DPD

PMC global DPD override support N/A

I/O rail category: AO or Non-AO Always-On I/O rail

Usage System reset and JTAG inputs

List of I/Os

SYS_RESET_N

NVDBG_SEL

JTAG_TRST_

JTAG_TMS

JTAG_TCK

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Type of DPD Capability I/Os Not Supporting DPD thus not Entering in DPD

JTAG_TDI

NVJTAG_SEL

Category of pads that their DPD controls are tied off to 1’b0 with JTAG overrides. These are the set of pads that

should not go into DPD state because of their critical functional nature and power management.

Table 8.48 I/Os Not Entering DPD as Result of Tie-off

Type of DPD Capability I/Os Not Entering in DPD as Result of (SEL_DPD/E_DPD=0) Tie-off

PMC global DPD override support N/A

I/O rail category: AO or Non-AO Always-on I/O rail category

Usage System mgmt. (PMIC control), Clock inputs, JTAG output

List of I/Os SHUTDOWN_N

PMU_INT_N

SOC_PWR_REQ

CLK_32K_IN

JTAG_TDO

Category of pads that they have per pin DPD software controls. These are the set of I/Os in always-on I/O rails. Also,

these I/Os have per pin DPD override masks that enable to exclude the I/O from SC7 entry/exit PMC global DPD

sequencing.

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Table 8.49 PMC DPD Control Specifics per I/O Names

Type of DPD Capability

I/Os which can enter in to DPD and have per pin DPD req control

PMC Global DPD Override Support Yes

I/O Rail Category: AO or Non-AO

Always-on I/O rail category

Usage

System mgmt. (Misc and thermal, notifications), LSIO ports – UART, SPI2, I C, and

CAN interfaces

List of I/Os and PMC DPD Control

Specifics

I/O Name

PMC DPD Control Name

TOUCH_CLK (PWM4) TOUCH_CLK

SAFE_STATE SAFE_STATE

VCOMP_ALERT VCOMP_ALERT

PWR_I2C_SCL PWR_I2C_SCL

PWR_I2C_SDA PWR_I2C_SDA

AO_RETENTION_N AO_RETENTION

BATT_OC BATT_OC

POWER_ON POWER_ON

SPI2_SCK SPI2_SCK

SPI2_MISO SPI2_MISO

SPI2_MOSI SPI2_MOSI

SPI2_CS0 SPI2_CS0

UART3_TX UART3_TX

UART3_RX UART3_RX

GEN2_I2C_SCL GEN2_I2C_SCL

GEN2_I2C_SDA GEN2_I2C_SDA

GEN8_I2C_SCL GEN8_I2C_SCL

GEN8_I2C_SDA GEN8_I2C_SDA

CAN1_DOUT CAN1_DOUT

CAN1_DIN CAN1_DIN

CAN0_DOUT CAN0_DOUT

CAN0_DIN CAN0_DIN

CAN0_STB CAN0_STB

CAN0_EN CAN0_EN

CAN0_WAKE CAN0_WAKE

CAN0_ERR CAN0_ERR

CAN1_STB CAN1_STB

CAN1_EN CAN1_EN

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CAN1_WAKE CAN1_WAKE

CAN1_ERR CAN1_ERR

Rest of MPIO pads which can be transitioned to DPD state by pin group wise DPD controls. All such I/Os go through

PMC global DPD sequencing during SC7 entry/exit irrespective of software DPD control programming.

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Table 8.50 PMC DPD Control Specifics per I/O Group of Interface Names

Type of DPD Capability

I/Os which can enter in to DPD and

have per group DPD req control. Few

exceptions include per I/O or I/F

controls.

PMC Global DPD Override Support No

I/O Rail Category: AO or Non-AO

Non-AO I/O rail category

Usage Rest of LSIO ports, GPIOs

List of I/Os and PMC DPD Control

Specifics

I/O Group or Pin/Interface Name

PMC DPD Control Name

EQOS EQOS

SDMMC1_HV SDMMC1_HV

SDMMC3_HV SDMMC3_HV

SDMMC4 SDMMC4

QSPI SPI

CONN (excluding UART4, PWM5,

PWM6, PWM7 pins)

CONN

AUDIO (excluding DAP3 and DAP5

pins)

AUDIO

AUDIO_HV AUDIO_HV

DEBUG DBG

CAM CAM

PWR_CTL PWR_CTL

UART excluding UART5 interface,

PWM2, PWM3 pins

UART

UFS UFS

PEX_CTL excluding PEX_L0_RST_N

/PEX_L1_RST_N pins

PEX_CNTRL

PEX_CLK PEX_CLK1, PEX_CLK2, PEX_CLK3,

PEX_CLK_BIAS

PEX_CTL2 excluding PEX_L5_RST_N PEX_CTL_2

VDDIO_PEX_CLK_2 PEX_CLK_2, PEX_CLK_2_BIAS

HDMI_DP0 brick HDMI_DP0

HDMI_DP1 brick HDMI_DP1

HDMI_DP2 brick HDMI_DP2

HDMI_DP3 brick HDMI_DP3

EDP Excluding SOC_GPIO53 EDP

CSI bias pad MIPI_BIAS

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CSI per brick A CSIA

CSI per brick B CSIB

CSI per brick C CSIC

CSI per brick D CSID

CSI per brick E CSIE

CSI per brick F CSIF

CSI per brick G CSIG

CSI per brick H CSIH

I/O: PEX_L0_RST_N PEX_L0_RST_N

I/O: PEX_L1_RST_N PEX_L1_RST_N

I/O: PEX_L5_RST_N PEX_L5_RST_N

I/O: SOC_GPIO53 (DGPU_PWR_EN) SOC_GPIO53

I/O: GP_PWM2 GP_PWM2

I/O: GP_PWM3 GP_PWM3

I/O: SOC_GPIO12 (PWM5) SOC_GPIO12

I/O: SOC_GPIO13 (PWM6) SOC_GPIO13

I/O: SOC_GPIO10 (PWM7) SOC_GPIO10

I/F: UART4 interface pins UART4

I/F: UART5 interface pins UART5

I/F: DAP3 interface pins DAP3

I/F: DAP5 interface pins DAP5

Set of analog and high-speed interface pads. These are the cases of pads that may not have DPD mode like other

Xavier MPIO/GPIO pads, instead there is a power down mode which is used for low power mode. Some others have

DPD mode, but either way such DPD/Power down mode is not controlled by PMC during SC7 entry/exit, instead the

IP logic that is interfacing this has got appropriate clamps or managed to put the pad in low power state. List of such

high-speed I/Os are:

Display sidebands: BDDPAUX

Memory interface pads: LP4X_IOBRICK, LP4X_CDB, LP4X_COMP, and LP4X_RESET

USB2 interface pads: BDUSB2

USB2 bias pad: BDUSB2_BIAS

PCIe/SATA/NvMe/UFS, NVLink interface pads: UPHYDS_PLL4DS12, UPHYDS_PLL1DS8

Refer to respective I/O sections for details on low power management.

PEX_CLK Pad DPD Controls

PEX_CLK related DPD control manage two clock pairs, one each from each of x3 bricks due to legacy

implementation reasons. This section depicts the DPD software controls mapping to the physical bricks/lanes

and thus Xavier I/O's.

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Figure 8.23 PEX CLKOUT Pads Software DPD Control Mapping

For BOPEXCLK 3x pad instances PEX_CLK1/2/3 are the DPD controls.

Table 8.51 BOPEXCLK 3x DPD Control

BOPEXCLK 3x Corresponding DPD control

Instance1 E_DPD_0, Instance2 E_DPD_0 PEX_CLK1

Instance1 E_DPD_1, Instance2 E_DPD_1 PEX_CLK2

Instance1 E_DPD_2, Instance2 E_DPD_2 PEX_CLK3

Instance1 E_DPD_BIAS, INSTANCE2 E_DPD_BIAS PEX_CLK_BIAS

For BOPEXCLK 1x pad: Controls are PEX_CLK_2_BIAS and PEX_CLK_2.

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Table 8.52 BOPEXCLK 1x DPD Control

BOPEXCLK 1x Corresponding DPD control

E_DPD PEX_CLK_2

E_DPD_BIAS PEX_CLK_2_BIAS

8.4.3 Programming Guidelines

Some controller instances make their set of signals available on two or more sets of MPIO’s. To say it another

way, such controllers have more than one “interface.”

Note: Before using any controller, make sure that the PinMux registers are programmed to bring out the

controller’s signals on a maximum of one interface.

PinMux Programming

PinMuxing configurations are static. Pimuxing provides the flexibility to choose a pin for different function across

different platforms, but not to change them dynamically.

In specific cases, based on use case requirement it is needed to change a pin from SFIO to GPIO or vice versa.

Although PinMux selection dynamic changing is not supported, SFIO to GPIO or vice versa changes are

allowed. Subsection outlines the PinMux programming, SFIO/GPIO switching programming and such pad

control programming guidelines.

Changing a PinMux Selection

PinMux programming to select the pin function is part of respective I/O initialization. Below sequence are a

reference and confines to general purpose pad I/Os which are shared by multiple low speed interface

controllers (SFIO).

Ensure that all the interface controllers sharing the pins are in in-active state, so that possible glitches do not result

corruption in downstream logic.

Change the PADCTL_<padctl_group>_<ball_name> .PM value to desired I/O function enumerated per pin.

Initialize the respective SFIO controller and follow required SFIO interface programming guide.

Driving Source Change from SFIO to GPIO

Pads are by-default owned by SFIO Primary function or Alternative options can be switched as software driven

GPIO as follows:

Configure the pad’s GPIO specific registers for correct value for output mode with the correct value as specified in

GPIO section. This ensures the new source is ready with the correct value.

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Change the pad control register i.e. PADCTL_<padctl_group>_<Ball_Name>.GPIO_SF_SEL bit field register

corresponding a pin to 1’b0 for GPIO selection.

Follow the GPIO controller programming model depending on desired GPIO function as specified in GPIO section

(Input or output to a value or input with interrupt etc.).

Driving Source Change from GPIO to SFIO

Pads currently set up in GPIO mode may be switched back to SFIO function as follows:

Change the pad control register i.e., PADCTL_<padctl_group>_<Ball_Name>.GPIO_SF_SEL bit field register

corresponding a pin to “1” for SFIO selection.

Initialize the respective SFIO controller and follow required SFIO interface programming guide.

Programming Sequence for Input Mode

After cold boot based on platform configuration (typically obtained from the Boot Loader) different LSIO

functional controllers must be mapped to specific I/O pin. The following is the programming sequence for that:

Set PM field as per PinMux selection in pad control register PADCTL_<padctl_group>_<ball_name>_*.PM =

0x0: Primary

0x1: Alt1

0x2: Alt2

0x3: Alt3

Set SFIO/GPIO selection to SFIO selection, (PADCTL_<padctl_group>_<ball_name>_*.GPIO_SFIO_SEL =

HSIO) (nothing but SFIO).

Set (PADCTL_<padctl_group>_<ball_name>_* .TRISTATE = TRISTATE) to disable SoC functional logic

driving the I/O.

Set (PADCTL_<padctl_group>_<ball_name>_* .E_INPUT= ENABLE) to turn on input receiver.

The specific I/O controllers driving the I/Os is configured and activated.

Programming Sequence for Output Mode and Bi-directional Mode

Normal Push-pull Pad

Set PM field as per PinMux selection in pad control register PADCTL_<padctl_group>_<ball_name>_*.PM =

0x0: Primary

0x1: Alt1

0x2: Alt2

0x3: Alt3

Set SFIO/GPIO selection to SFIO selection, (PADCTL_<padctl_group>_<ball_name>_*.GPIO_SFIO_SEL =

HSIO) (nothing but SFIO).

Set (PADCTL_<padctl_group>_<ball_name>_* .TRISTATE = PASSTHROUGH) to enable selected SFIO

functional logic driving the I/Os.

Set (PADCTL_<padctl_group>_<ball_name>_* .E_INPUT = ENABLE) for bidirectional configuration, or

Set (PADCTL_<padctl_group>_<ball_name>_* .E_INPUT = DISABALE) for output only configuration

The specific I/O controllers driving I/O is thus configured and activated.

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Open-drain Pad

Open drain pads are used to emulate Wired-AND functionality, where in multiple drivers can be shorted on the

board with an external pull-up. These pads don’t drive active HIGH, instead it drives active LOW or float the pin.

Platform pull-up shall ensure correct value on the node i.e., if all the drivers are floating it is at Logic1 and if any

of the drivers are driving active LOW, bus state is at Logic0. Such pads require a different programming

sequence. So, any logic (both functional or software based GPIO) shall never the program/drive pads to Active

1. Both the ST pads and DD pads able to operate in open drain Mode. But the DD pads have specific control to

tolerate the I/O swing of 3.3V.

3.3V Tolerance and Open-drain Operation

Configure the pad for 3.3V swing tolerance by enabling the E_IO_HV pad control, i.e.

(PADCTL_<padctl_group>_<ball_name>_*.E_IO_HV = 1). Applicable to DD pads when it has to tolerate 3.3V levels.

Typically other than the PMIC interface, which is guaranteed to operate at 1.8V for all the other DD pads pad control

field E_IO_HV is set to 1 as reset default to ensure they come with 3.3V tolerance mode. E_IO_HV pad control must

be set to 1 before I/O can be pulled to > 1.8V.

Set (PADCTL_<pactcl_group>_<ball_ame>_*.TRISTATE = TRISTATE). Even when the functional logic driving

Logic1, the pad is in open drain driver mode and it is floated through an external pull-up. Enabling internal pull-up is

ignored by the pad when the E_IO_HV is set though this is not the recommended.

1.8V Tolerance and Open-drain Operation

To emulate open drain in 1.8V mode of operation: Platform design to float the pad with external pull-up or

program (PADCTL_<padctl_group>_<ball_name>.PUPD = PULLUP)

Configure the Pad for 1.8V swing tolerance by setting (PADCTL_<padctl_group>_<ball_name>.E_IO_HV = 0).

To drive High Impedance into the pad set (PADCTL_<pactcl_group>_<ball_ame>_*.TRISTATE = TRISTATE).

1.8V Tolerance/Driving and Push-pull Operation

Since DD pads can be operated in normal push pull mode as well as open drain mode to emulate the push pull

mode the following configuration is followed.

To put the open-drain pad in 1.8V push-pull mode operation:

Set (PADCTL_<padctl_group>_<ball_name>.E_IO_HV = DISABLE).

Set (PADCTL_<padctl_group>_<ball_name>_* .TRISTATE = PASSTHROUGH) to enable functional logic driving

/sampling the I/O.

Set (PADCTL_<padctl_group>_<ball_name>_* .E_INPUT = ENABLE) for bi-directional mode of operation.

The specific I/O controllers driving the I/O is configured and activated

Pad Control Programming

Set Pad to High Impedance State

To select the pad for drive high impedance state:

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Set (PADCTL_<padctl_group>_<ball_name>_* .TRISTATE = TRISTATE).

Ensure (PADCTL_<padctl_group>_<ball_name>_* .PUPD == 0) to ensure internal pull-up/pull-down is disabled.

Pad Controls Wrong Programming Causing Electrical Damage

E_PBIAS_BUF, VREF_SEL pad controls to SDMEM* pads

E_PBIAS_BUF and VREF_SEL programming should follow below rules as listed in cell document. For VDD33

and VDD18 in the same direction or high VDD33 along with low VDD18 case, follow the rules below to prevent

overstress.

When (VDD33 - 0.91 * VDD18 > 1.98V), E_PBIAS_BUF must be 0;

When (VDD33 - 0.83 * VDD18 > 1.98V) && (E_PBIAS_BUF = 1), VREF_SEL must < 1;

When (VDD33 - 0.77 * VDD18 > 1.98V) && (E_PBIAS_BUF = 1), VREF_SEL must < 2;

When (VDD33 - 0.71 * VDD18 > 1.98V) && (E_PBIAS_BUF = 1), VREF_SEL must < 3;

Pad Controls Sequencing Requirements

To avoid remote chances of leakage and long-term reliability E_33V need to be set before supplying 3.3V to the 1.8V

/3.3V dual voltage supported pads.

SDMMC1/SDMMC3 for removable card usage is covered by SD card voltage switching sequence.

For cases, the I/O voltage usage is limited to 1.8V pad control programming through Xavier

Customer PinMux is adequate.E_IO_HV=0 to be programmed by PinMux initialization driver for back drive capable I

/Os using BDPGLPHVIN pads. Otherwise, the pad remains in open drain mode and doesn't function as push-pull

driver.

Pad Control Settings per PinMux Selection

As these pad control settings are applicable only when a PinMux SFIO is chosen, it could be different from reset

default settings. Although these shall be covered in respective interface section programming guidelines, based

on platform requirements pad electrical settings are tuned via customer PinMux sheet. Software uses generated

files out of PinMux sheet for initialization during boot.

Unused I/O Programming

Unused general purpose I/Os in a platform may be left unconnected however pad controls must be set per

below guideline to avoid leakage and/or noise especially when I/O power supply is ON. Programming steps for

different I/Os is summarized as below.

Table 8.53 Unused I/O Programming with I/O Power Supply ON

PHY/BRICK PAD Control Programming requirement when I/O is unused but I/O power supply is ON

MPIO pads

Following is done by platform Xavier Customer PinMux. So required pad control programming is automatically done

through PinMux driver in MB1. No further software steps are needed.

TRI-STATE enable, (PADCTL_<power_group>_<IO>_0.TRISTATE = 1)

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PHY/BRICK PAD Control Programming requirement when I/O is unused but I/O power supply is ON

Input path disable, (PADCTL_<power_group>_<IO>_0.E_INPUT = 1)

Weak pull-down enable, (PADCTL_<power_group>_<IO>_0.PUPD = 1)

DDR I/O

Brick

Park the unused bricks in DPD mode as per the EMC programming guide.

DDR COMP

Pads

Park the unused bricks in DPD mode as per the EMC programming guide.

DDR_RESET

_PAD

Park the unused bricks in DPD mode as per the EMC programming guide.

HSIO UPHY Park the unused brick lanes in IDDQ mode.

Set IDDQ and RESET to asserted via per lane UPHY PADCTL registers.

Enable pulldowns in the UPHY PADCTL registers.

NVHS UPHY Park the unused brick in IDDQ mode.

Set IDDQ and RESET to asserted via UPHY PADCTL register.

Enable pulldowns in the UPHY PADCTL registers.

USB2 pads Park unused bricks in DPD mode.

Set PD* to 1 via XUSB PADCTL register XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0

Enable weak pull-down by programming following bit fields.

(XUSB_AO_UTMIP_SLEEPWALK_CFG_0. MASTER_ENABLE = 1)

(XUSB_AO_UTMIP_SLEEPWALK_0. USBOP_RPD_A = 1)

(XUSB_AO_UTMIP_SLEEPWALK_0. USBON_RPD_A = 1)

USB2 BIAS

pad

Power down the BIAS pad if all the USB2 bricks are not used (less likely)

Set (XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0.PD = 1).

MIPI CSI

PHY

Park the unused bricks in DPD mode to keep the PAD in quiescent state.

Program bit fields corresponding to unused bricks in PMC registers – PMC_IMPL_IO_DPD_REQ_0,

PMC_IMPL_IO_DPD2_REQ_0

Enable weak pulldowns in the pad.

(NVCSI_PHY_0_NVCSI_CIL_<A-H>_PAD_CONFIG_0.SPARE_CLK_<A-H> = 1)

(NVCSI_PHY_0_NVCSI_CIL_<A-H>_PAD_CONFIG_0.SPARE_IO1_<A-H> = 1)

(NVCSI_PHY_0_NVCSI_CIL_<A-H>_PAD_CONFIG_0.SPARE_IO0_<A-H> = 1)

MIPI BIAS

pad

Park the BIAS pad in DPD mode if none of the CSI ports are used.

Program the MIPI_BIAS bit field in PMC to enable DPD

DP/HDMI

Combo PHY

Power down different elements in the PHY following the sequence below.

Set override for power down signals from register:

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PHY/BRICK PAD Control Programming requirement when I/O is unused but I/O power supply is ON

SOR_NV_PDISP_SOR_PLL2_0_AUX2_OVERRIDE_POWERDOWN

SOR_NV_PDISP_SOR_PLL2_0_AUX1_SEQ_PLLCAPPD_OVERRIDE

Disable the Tx lanes, CAL, and wait for > 5 µs

Set PDCAL to 1 through SOR reg:

SOR_NV_PDISP_SOR_DP_PADCTL0_0_PAD_CAL_PD_POWERDOWN

Set PD_TX* to 1 through SOR reg:

SOR_NV_PDISP_SOR_DP_PADCTL0_0_PD_TXD_0..3_YES

Set PDPORT to 1 through SOR reg:

SOR_NV_PDISP_SOR_PLL2_0_AUX7_PORT_POWERDOWN_ENABLE

Disable the PLL / charge-pump / VCO, and wait for > 5 µs.

Set PLLCAPPD to 1 through SOR reg:

SOR_NV_PDISP_SOR_PLL2_0_AUX8_SEQ_PLLCAPPD_ENFORCE_ENABLE

Set PLLVCOPD to 1 through SOR reg: SOR_NV_PDISP_SOR_PLL0_0_VCOPD_ASSERT

Set PDPLL to 1 through SOR reg:

SOR_NV_PDISP_SOR_PLL0_0_PWR_OFF

Assert PDBG to disable bandgap, and wait for > 5 µs.

Set PDBG to 1 through SOR reg:

SOR_NV_PDISP_SOR_PLL2_0_AUX6_BANDGAP_POWERDOWN_ENABLE

Assert DPD master power down control.

Set E_DPD to 1 through PMC reg: PMC_IMPL_IO_DPD_REQ_0_HDMI_DP0..3_ON

DP AUX

pads

Park the unused bricks in DPD/Power down state.

Set DPAUX_HYBRID_SPARE_0_PAD_PWR_POWERDOWN to `1’ corresponding to the DP-AUX

channel.

PEX CLK out

pads

Park the unused lanes in DPD mode.

Set corresponding bit fields in PMC register PMC_IMPL_IO_DPD_REQ_0

DPD Sequencing

When certain interface is not required to be active, group of pads associated with the interface may be put in

power down (DPD) state to save power. Based on MPIO pad capabilities, and functional requirements:

All non-AO groups of MPIO pads enter in to DPD state as part of SC7 entry and exit DPD state as part of SC7 entry

by PMC hardware.

All AO groups of MPIO pads do not enter in to DPD state as part of SC7 entry and do exit DPD state as part of SC7

exit by PMC hardware.

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Below is a reference guide for generic MPIO pad DPD sequencing during system active, PMC “Pad controls”

sections software programming sequence shall be referred for precise programming steps. Steps outline for

typical MPIO interface DPD entry and exit:

DPD Entry:

Software: Bring the I/O interface to Bus IDLE state. I/O controllers are brought into IDLE state and subsequently the

values they are driving towards the pads are stable.

Software: Program the PMC_IMPL_SEL_DPD_TIM_0 register as per SEL_DPD and E_DPD timing requirements.

There are two pad control pins i.e., E_DPD and SEL_DPD which are driven with proper timing as per the Pad data

sheet.

Software: Set PMC PMC_IMPL_IO_DPD[DPD2/DPD7/DPD8]_REQ_0 register bit field(s) corresponding to the group

of pads or interface. DPD controls and mechanisms lists all such PMC DPD software knobs.

Hardware: PMC runs the state machine to drive the DPD sequence control pins to enter i in DPD state.

SEL_DPD is asserted which triggers the pad to latch the pad inputs.

E_DPD is asserted based on PMC_IMPL_SEL_DPD_TIM_0 configuration.

Hardware: I/O state prior to entering to DPD is maintained while in DPD.

DPD Exit:

Software: Enable clocks and initialize respective I/O controller.

Software: Clear PMC PMC_IMPL_IO_DPD[DPD2/DPD7/DPD8] _REQ_0 register bit field(s) corresponding to the

group of pads or interface. DPD controls and mechanisms lists all such PMC DPD software knobs.

Hardware: PMC runs the state machine to drive the DPD sequence control pins to exit the DPD state.

SEL_DPD is de-asserted which triggers the pad to latch the pad inputs.

E_DPD is de-asserted based on PMC_IMPL_SEL_DPD_TIM_0 configuration.

Software: Proceeds with I/O interface programming for required interface operation.

MPIO Pad DPD State Output Tweaking

In such cases the following sequence should be performed:

SC7-entry-init: Configure the pad’s GPIO specific registers for desired pin state.

SC7-entry-init: Change the pin to GPIO (as on output)

SC7-entry-init: Drive the desired value

SC7-entry-init: Trigger to DPD mode by setting bit i.e., PMC_IMPL_DPDx_REQ in PMC to sample the correct value

Proceed with SC7 – entry sequence

SC7-exit: Do the PinMux recovery

SC7-exit: Change the pin from GPIO to SFIO and associate with the respective controller

SC7-exit Ensure the controller is configured to drive correct value what is getting driven in the pad so that there is no

glitch when the pad is coming out of DPD

SC7-exit: Bring the pads out of DPD

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PHY/Brick SC7 Entry/Exit

Most of the unused PHY/Bricks I/O states are parked to tri-state and hence they are put into low power state

during SC7 and brought out of power down modes during SC7 exit. Refer to respective HSIO/DDR architecture

documents for the same.

Bringing I/O Rails Down during SC7

To realize lowest possible leakage power, it’s possible to power down I/O rails in conjunction with Xavier low

power states such as SC7. Xavier I/O rails may be shared with the interfacing device and hence the possibility

of powering off I/O rails goes case by case based on interface/platform.

Discrete Pad’s I/O Rails in SC7

Normally the I/O rails of the discrete pads are ON during SC7 to support wakes etc. However, to aggressively

reduce system power it may be turned OFF in specific platforms depending on use case requirements. I/O rail

power on/off has special considerations with regards to power sequencing and duly meeting MPIO pad

functional requirements as listed in DPD controls handling and low power state aspects.

Important note with regards to turning ON I/O rails:

MPIO pads VDDP supply must not be powered ON while the pad is in DPD mode. Deep sleep exit turning ON I/O

rails has modification in Xavier. Reset is asserted to exit the DPD mode (rather to say ensure MPIO pad is not in DPD

mode) before I/O rails are powered ON. See the Power Management Controller chapter for more details.

PHY/Bricks I/O Rail in SC7

Bricks are put in their respective low power mode and the control mechanism differs for each brick. The low

power mode mechanisms of different bricks are captured in Low Power Modes for PHYs as a reference.

Respective software drivers for the brick like Display Driver, Camera Driver puts the bricks in low power mode

when iinterface is IDLE. Low power/DPD programming shall refer to respective HSIO/DDR architecture

documents.

Wake Events Configuration

To enable wake triggering when wake capable pad is in active state, the E_INPUT pad control needs to be

programmed HIGH to enable receiver path in pad.

However, such wake capable pad is in DPD state (E_DPD = 1, SEL_DPD = 1) enables receiver path to trigger

wake irrespective of E_INPUT pad control setting. To avoid corner case scenarios of missing wake events

during DPD and active states, it’s recommended to set E_INPUT = 1 setting for wake capable pads. It is

required to setup E_INPUT = 1 (Enable) by software post-boot for all the wake event supported pads relevant

for a platform.

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Most of the mechanical buttons act as SC7 wake source which means their key press to be de-bounced during

SC7. Beyond which the wake events must be protected from noise spikes. So, wake sensing logic in PMC does

glitch filtering and de-bounce capability. Wake programming consists of various signaling, routing and masking

DEBOUNCE selection:

DEBOUNCE_CLK = 1 kHz: Any wake events width less than 31 µs is ignored.

DEBOUNCE_CLK = 32 kHz: Any wake events width less than 31 µs is ignored.

DE-GLITCH:

If enabled, Glitches <= 2 nS are filtered out.

Refer to PMC section titled “Wake Programming Model.”

PCIe C5 Sidebands on NVHS0_DVDD Power Supply

NVLink controller and logic associated with are partitioned in to NVHS0_DVDD supply to be able to run NVLink

at high speeds irrespective of core DVFS. Refer to the “PCIe INIT” in the HSIO section for details in initialization

steps required prior to accessing PCIe L5 side-band pad controls or GPIO registers. Required programming

steps are covered in HSIO section.

It is required that:

NVHS0_DVDD rail must be powered for PCIe C5/SLVS interfaces

Resets driven CAR registers need to be cleared.

8.4.4 PinMux Registers

Refer to "Reading Register Tables" in the Introduction chapter for the register table protocol as well as

recommendations for accessing registers.

The register descriptions below give the offset of each register within the PinMux address range. The Base

Addresses of the registers in the PinMux are specified in the Address Map section of the Xavier TRM.

CAM PAD Control Registers

PADCTL_CAM_EXTPERIPH2_CLK_0

Offset: 0x0

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_EXTPERIPH2_CLK_0

Reset: 0x00000414 (0bxxxx,xxxx,xxxx,xxxx,xxx0,x1x0,x0x1,0100)

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Bit Reset Description

12 DISABLE

E_SCHMT:

= DISABLE0

= ENABLE1

10 SFIO

GPIO_SF_SEL:

= GPIO0

= SFIO1

8 DISABLE E_LPDR:

= DISABLE0

= ENABLE1

6 DISABLE E_INPUT:

= DISABLE0

= ENABLE1

4 TRISTATE TRISTATE:

= PASSTHROUGH0

= TRISTATE1

3:2 PULL_DOWN PUPD:

= NONE0

= PULL_DOWN1

= PULL_UP2

= RSVD3

1:0 EXTPERIPH2

PM:

= EXTPERIPH20

= RSVD11

= RSVD22

= RSVD33

PADCTL_CAM_CFG2TMC_EXTPERIPH2_CLK_0

Offset: 0x4

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_EXTPERIPH2_CLK_0

Reset: 0x00000000 (0bxxxx,xxx0,0000,xxx0,0000,xxxx,xxxx,xxxx)

Bit Reset Description

24:20 0x0 CFG_CAL_DRVUP

16:12 0x0 CFG_CAL_DRVDN

PADCTL_CAM_EXTPERIPH1_CLK_0

Offset: 0x8

Read/Write: RW

Parity Protection: N

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SCR Protection: SCR_EXTPERIPH1_CLK_0

Reset: 0x00000414 (0bxxxx,xxxx,xxxx,xxxx,xxx0,x1x0,x0x1,0100)

Bit Reset Description

12 DISABLE

E_SCHMT:

= DISABLE0

= ENABLE1

10 SFIO

GPIO_SF_SEL:

= GPIO0

= SFIO1

8 DISABLE E_LPDR:

= DISABLE0

= ENABLE1

6 DISABLE E_INPUT:

= DISABLE0

= ENABLE1

4 TRISTATE TRISTATE:

= PASSTHROUGH0

= TRISTATE1

3:2 PULL_DOWN PUPD:

= NONE0

= PULL_DOWN1

= PULL_UP2

= RSVD3

1:0 EXTPERIPH1

PM:

= EXTPERIPH10

= RSVD11

= RSVD22

= RSVD33

PADCTL_CAM_CFG2TMC_EXTPERIPH1_CLK_0

Offset: 0xc

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_EXTPERIPH1_CLK_0

Reset: 0x00000000 (0bxxxx,xxx0,0000,xxx0,0000,xxxx,xxxx,xxxx)

Bit Reset Description

24:20 0x0 CFG_CAL_DRVUP

16:12 0x0 CFG_CAL_DRVDN

PADCTL_CAM_CAM_I2C_SDA_0

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Offset: 0x10

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_CAM_I2C_SDA_0

Reset: 0x00001570 (0bxxxx,xxxx,xxxx,xxxx,xxx1,x1x1,x111,0000)

Bit Reset Description

12 ENABLE

E_SCHMT:

= DISABLE0

= ENABLE1

10 SFIO

GPIO_SF_SEL:

= GPIO0

= SFIO1

8 ENABLE

E_LPDR:

= DISABLE0

= ENABLE1

6 ENABLE

E_INPUT:

= DISABLE0

= ENABLE1

5 ENABLE E_IO_HV:

= DISABLE0

= ENABLE1

4 TRISTATE TRISTATE:

= PASSTHROUGH0

= TRISTATE1

3:2 NONE PUPD:

= NONE0

= PULL_DOWN1

= PULL_UP2

= RSVD3

1:0 I2C3

PM:

= I2C30

= RSVD11

= RSVD22

= RSVD33

PADCTL_CAM_CFG2TMC_CAM_I2C_SDA_0

Offset: 0x14

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_CAM_I2C_SDA_0

Reset: 0x00000000 (0bxxxx,xxx0,0000,xxx0,0000,xxxx,xxxx,xxxx)

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Bit Reset Description

24:20 0x0 CFG_CAL_DRVUP

16:12 0x0

CFG_CAL_DRVDN

PADCTL_CAM_CAM_I2C_SCL_0

Offset: 0x18

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_CAM_I2C_SCL_0

Reset: 0x00001570 (0bxxxx,xxxx,xxxx,xxxx,xxx1,x1x1,x111,0000)

Bit Reset Description

12 ENABLE E_SCHMT:

= DISABLE0

= ENABLE1

10 SFIO GPIO_SF_SEL:

= GPIO0

= SFIO1

8 ENABLE E_LPDR:

= DISABLE0

= ENABLE1

6 ENABLE

E_INPUT:

= DISABLE0

= ENABLE1

5 ENABLE

E_IO_HV:

= DISABLE0

= ENABLE1

4 TRISTATE

TRISTATE:

= PASSTHROUGH0

= TRISTATE1

3:2 NONE

PUPD:

= NONE0

= PULL_DOWN1

= PULL_UP2

= RSVD3

1:0 I2C3 PM:

= I2C30

= RSVD11

= RSVD22

= RSVD33

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PADCTL_CAM_CFG2TMC_CAM_I2C_SCL_0

Offset: 0x1c

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_CAM_I2C_SCL_0

Reset: 0x00000000 (0bxxxx,xxx0,0000,xxx0,0000,xxxx,xxxx,xxxx)

Bit Reset Description

24:20 0x0 CFG_CAL_DRVUP

16:12 0x0 CFG_CAL_DRVDN

PADCTL_CAM_SOC_GPIO40_0

Offset: 0x20

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_SOC_GPIO40_0

Reset: 0x00000474 (0bxxxx,xxxx,xxxx,xxxx,xxx0,x1x0,x111,0100)

Bit Reset Description

12 DISABLE E_SCHMT:

= DISABLE0

= ENABLE1

10 SFIO GPIO_SF_SEL:

= GPIO0

= SFIO1

8 DISABLE E_LPDR:

= DISABLE0

= ENABLE1

6 ENABLE

E_INPUT:

= DISABLE0

= ENABLE1

5 ENABLE

E_IO_HV:

= DISABLE0

= ENABLE1

4 TRISTATE

TRISTATE:

= PASSTHROUGH0

= TRISTATE1

3:2 PULL_DOWN

PUPD:

= NONE0

= PULL_DOWN1

= PULL_UP2

= RSVD3

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Bit Reset Description

1:0 VGP1 PM:

= VGP10

= SLVS1

= RSVD22

= RSVD33

PADCTL_CAM_CFG2TMC_SOC_GPIO40_0

Offset: 0x24

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_SOC_GPIO40_0

Reset: 0x00000000 (0bxxxx,xxx0,0000,xxx0,0000,xxxx,xxxx,xxxx)

Bit Reset Description

24:20 0x0 CFG_CAL_DRVUP

16:12 0x0 CFG_CAL_DRVDN

PADCTL_CAM_SOC_GPIO41_0

Offset: 0x28

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_SOC_GPIO41_0

Reset: 0x00000474 (0bxxxx,xxxx,xxxx,xxxx,xxx0,x1x0,x111,0100)

Bit Reset Description

12 DISABLE E_SCHMT:

= DISABLE0

= ENABLE1

10 SFIO GPIO_SF_SEL:

= GPIO0

= SFIO1

8 DISABLE E_LPDR:

= DISABLE0

= ENABLE1

6 ENABLE

E_INPUT:

= DISABLE0

= ENABLE1

5 ENABLE

E_IO_HV:

= DISABLE0

= ENABLE1

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Bit Reset Description

4 TRISTATE

TRISTATE:

= PASSTHROUGH0

= TRISTATE1

3:2 PULL_DOWN

PUPD:

= NONE0

= PULL_DOWN1

= PULL_UP2

= RSVD3

1:0 VGP2 PM:

= VGP20

= EXTPERIPH31

= RSVD22

= RSVD33

PADCTL_CAM_CFG2TMC_SOC_GPIO41_0

Offset: 0x2c

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_SOC_GPIO41_0

Reset: 0x00000000 (0bxxxx,xxx0,0000,xxx0,0000,xxxx,xxxx,xxxx)

Bit Reset Description

24:20 0x0 CFG_CAL_DRVUP

16:12 0x0 CFG_CAL_DRVDN

PADCTL_CAM_SOC_GPIO42_0

Offset: 0x30

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_SOC_GPIO42_0

Reset: 0x00000474 (0bxxxx,xxxx,xxxx,xxxx,xxx0,x1x0,x111,0100)

Bit Reset Description

12 DISABLE E_SCHMT:

= DISABLE0

= ENABLE1

10 SFIO GPIO_SF_SEL:

= GPIO0

= SFIO1

DISABLE

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Bit Reset Description

E_LPDR:

= DISABLE0

= ENABLE1

6 ENABLE E_INPUT:

= DISABLE0

= ENABLE1

5 ENABLE E_IO_HV:

= DISABLE0

= ENABLE1

4 TRISTATE TRISTATE:

= PASSTHROUGH0

= TRISTATE1

3:2 PULL_DOWN

PUPD:

= NONE0

= PULL_DOWN1

= PULL_UP2

= RSVD3

1:0 VGP3 PM:

= VGP30

= EXTPERIPH41

= RSVD22

= RSVD33

PADCTL_CAM_CFG2TMC_SOC_GPIO42_0

Offset: 0x34

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_SOC_GPIO42_0

Reset: 0x00000000 (0bxxxx,xxx0,0000,xxx0,0000,xxxx,xxxx,xxxx)

Bit Reset Description

24:20 0x0 CFG_CAL_DRVUP

16:12 0x0 CFG_CAL_DRVDN

PADCTL_CAM_SOC_GPIO43_0

Offset: 0x38

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_SOC_GPIO43_0

Reset: 0x00000474 (0bxxxx,xxxx,xxxx,xxxx,xxx0,x1x0,x111,0100)

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Bit Reset Description

12 DISABLE E_SCHMT:

= DISABLE0

= ENABLE1

10 SFIO GPIO_SF_SEL:

= GPIO0

= SFIO1

8 DISABLE E_LPDR:

= DISABLE0

= ENABLE1

6 ENABLE E_INPUT:

= DISABLE0

= ENABLE1

5 ENABLE

E_IO_HV:

= DISABLE0

= ENABLE1

4 TRISTATE

TRISTATE:

= PASSTHROUGH0

= TRISTATE1

3:2 PULL_DOWN

PUPD:

= NONE0

= PULL_DOWN1

= PULL_UP2

= RSVD3

1:0 VGP4 PM:

= VGP40

= SLVS1

= RSVD22

= RSVD33

PADCTL_CAM_CFG2TMC_SOC_GPIO43_0

Offset: 0x3c

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_SOC_GPIO43_0

Reset: 0x00000000 (0bxxxx,xxx0,0000,xxx0,0000,xxxx,xxxx,xxxx)

Bit Reset Description

24:20 0x0 CFG_CAL_DRVUP

16:12 0x0

CFG_CAL_DRVDN

PADCTL_CAM_SOC_GPIO44_0

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Offset: 0x40

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_SOC_GPIO44_0

Reset: 0x00000474 (0bxxxx,xxxx,xxxx,xxxx,xxx0,x1x0,x111,0100)

Bit Reset Description

12 DISABLE

E_SCHMT:

= DISABLE0

= ENABLE1

10 SFIO

GPIO_SF_SEL:

= GPIO0

= SFIO1

8 DISABLE E_LPDR:

= DISABLE0

= ENABLE1

6 ENABLE E_INPUT:

= DISABLE0

= ENABLE1

5 ENABLE E_IO_HV:

= DISABLE0

= ENABLE1

4 TRISTATE TRISTATE:

= PASSTHROUGH0

= TRISTATE1

3:2 PULL_DOWN PUPD:

= NONE0

= PULL_DOWN1

= PULL_UP2

= RSVD3

1:0 VGP5

PM:

= VGP50

= GP1

= RSVD22

= RSVD33

PADCTL_CAM_CFG2TMC_SOC_GPIO44_0

Offset: 0x44

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_SOC_GPIO44_0

Reset: 0x00000000 (0bxxxx,xxx0,0000,xxx0,0000,xxxx,xxxx,xxxx)

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Bit Reset Description

24:20 0x0 CFG_CAL_DRVUP

16:12 0x0

CFG_CAL_DRVDN

PADCTL_CAM_SOC_GPIO45_0

Offset: 0x48

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_SOC_GPIO45_0

Reset: 0x00000474 (0bxxxx,xxxx,xxxx,xxxx,xxx0,x1x0,x111,0100)

Bit Reset Description

12 DISABLE E_SCHMT:

= DISABLE0

= ENABLE1

10 SFIO GPIO_SF_SEL:

= GPIO0

= SFIO1

8 DISABLE E_LPDR:

= DISABLE0

= ENABLE1

6 ENABLE E_INPUT:

= DISABLE0

= ENABLE1

5 ENABLE

E_IO_HV:

= DISABLE0

= ENABLE1

4 TRISTATE

TRISTATE:

= PASSTHROUGH0

= TRISTATE1

3:2 PULL_DOWN

PUPD:

= NONE0

= PULL_DOWN1

= PULL_UP2

= RSVD3

1:0 VGP6 PM:

= VGP60

= RSVD11

= RSVD22

= RSVD33

PADCTL_CAM_CFG2TMC_SOC_GPIO45_0

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Offset: 0x4c

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_SOC_GPIO45_0

Reset: 0x00000000 (0bxxxx,xxx0,0000,xxx0,0000,xxxx,xxxx,xxxx)

Bit Reset Description

24:20 0x0 CFG_CAL_DRVUP

16:12 0x0 CFG_CAL_DRVDN

PADCTL_CAM_SOC_GPIO20_0

Offset: 0x50

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_SOC_GPIO20_0

Reset: 0x00000454 (0bxxxx,xxxx,xxxx,xxxx,xxx0,x1x0,x1x1,0100)

Bit Reset Description

12 DISABLE E_SCHMT:

= DISABLE0

= ENABLE1

10 SFIO GPIO_SF_SEL:

= GPIO0

= SFIO1

8 DISABLE E_LPDR:

= DISABLE0

= ENABLE1

6 ENABLE

E_INPUT:

= DISABLE0

= ENABLE1

4 TRISTATE

TRISTATE:

= PASSTHROUGH0

= TRISTATE1

3:2 PULL_DOWN PUPD:

= NONE0

= PULL_DOWN1

= PULL_UP2

= RSVD3

1:0

RSVD0

PM:

= RSVD00

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Bit Reset Description

= RSVD11

= RSVD22

= RSVD33

PADCTL_CAM_CFG2TMC_SOC_GPIO20_0

Offset: 0x54

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_SOC_GPIO20_0

Reset: 0x00000000 (0bxxxx,xxx0,0000,xxx0,0000,xxxx,xxxx,xxxx)

Bit Reset Description

24:20 0x0

CFG_CAL_DRVUP

16:12 0x0

CFG_CAL_DRVDN

PADCTL_CAM_SOC_GPIO21_0

Offset: 0x58

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_SOC_GPIO21_0

Reset: 0x00000454 (0bxxxx,xxxx,xxxx,xxxx,xxx0,x1x0,x1x1,0100)

Bit Reset Description

12 DISABLE E_SCHMT:

= DISABLE0

= ENABLE1

10 SFIO GPIO_SF_SEL:

= GPIO0

= SFIO1

8 DISABLE

E_LPDR:

= DISABLE0

= ENABLE1

6 ENABLE

E_INPUT:

= DISABLE0

= ENABLE1

4 TRISTATE TRISTATE:

= PASSTHROUGH0

= TRISTATE1

3:2

PULL_DOWN

PUPD:

= NONE0

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Bit Reset Description

= PULL_DOWN1

= PULL_UP2

= RSVD3

1:0 RSVD0 PM:

= RSVD00

= RSVD11

= RSVD22

= RSVD33

PADCTL_CAM_CFG2TMC_SOC_GPIO21_0

Offset: 0x5c

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_SOC_GPIO21_0

Reset: 0x00000000 (0bxxxx,xxx0,0000,xxx0,0000,xxxx,xxxx,xxxx)

Bit Reset Description

24:20 0x0

CFG_CAL_DRVUP

16:12 0x0 CFG_CAL_DRVDN

PADCTL_CAM_SOC_GPIO22_0

Offset: 0x60

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_SOC_GPIO22_0

Reset: 0x00000454 (0bxxxx,xxxx,xxxx,xxxx,xxx0,x1x0,x1x1,0100)

Bit Reset Description

12 DISABLE E_SCHMT:

= DISABLE0

= ENABLE1

10 SFIO GPIO_SF_SEL:

= GPIO0

= SFIO1

8 DISABLE

E_LPDR:

= DISABLE0

= ENABLE1

6 ENABLE

E_INPUT:

= DISABLE0

= ENABLE1

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Bit Reset Description

4 TRISTATE

TRISTATE:

= PASSTHROUGH0

= TRISTATE1

3:2 PULL_DOWN

PUPD:

= NONE0

= PULL_DOWN1

= PULL_UP2

= RSVD3

1:0 RSVD0 PM:

= RSVD00

= NV1

= RSVD22

= RSVD33

PADCTL_CAM_CFG2TMC_SOC_GPIO22_0

Offset: 0x64

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_SOC_GPIO22_0

Reset: 0x00000000 (0bxxxx,xxx0,0000,xxx0,0000,xxxx,xxxx,xxxx)

Bit Reset Description

24:20 0x0 CFG_CAL_DRVUP

16:12 0x0 CFG_CAL_DRVDN

PADCTL_CAM_SOC_GPIO23_0

Offset: 0x68

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_SOC_GPIO23_0

Reset: 0x00000440 (0bxxxx,xxxx,xxxx,xxxx,xxx0,x1x0,x1x0,0000)

Bit Reset Description

12 DISABLE E_SCHMT:

= DISABLE0

= ENABLE1

10 SFIO GPIO_SF_SEL:

= GPIO0

= SFIO1

DISABLE

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Bit Reset Description

E_LPDR:

= DISABLE0

= ENABLE1

6 ENABLE E_INPUT:

= DISABLE0

= ENABLE1

4 PASSTHROUGH TRISTATE:

= PASSTHROUGH0

= TRISTATE1

3:2 NONE PUPD:

= NONE0

= PULL_DOWN1

= PULL_UP2

= RSVD3

1:0 RSVD0

PM:

= RSVD00

= WDT1

= RSVD22

= RSVD33

PADCTL_CAM_CFG2TMC_SOC_GPIO23_0

Offset: 0x6c

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_SOC_GPIO23_0

Reset: 0x00000000 (0bxxxx,xxx0,0000,xxx0,0000,xxxx,xxxx,xxxx)

Bit Reset Description

24:20 0x0 CFG_CAL_DRVUP

16:12 0x0 CFG_CAL_DRVDN

PADCTL_CAM_SOC_GPIO04_0

Offset: 0x70

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_SOC_GPIO04_0

Reset: 0x00000454 (0bxxxx,xxxx,xxxx,xxxx,xxx0,x1x0,x1x1,0100)

Bit Reset Description

DISABLE

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Bit Reset Description

E_SCHMT:

= DISABLE0

= ENABLE1

10 SFIO

GPIO_SF_SEL:

= GPIO0

= SFIO1

8 DISABLE

E_LPDR:

= DISABLE0

= ENABLE1

6 ENABLE E_INPUT:

= DISABLE0

= ENABLE1

4 TRISTATE TRISTATE:

= PASSTHROUGH0

= TRISTATE1

3:2 PULL_DOWN PUPD:

= NONE0

= PULL_DOWN1

= PULL_UP2

= RSVD3

1:0 RSVD0 PM:

= RSVD00

= RSVD11

= RSVD22

= RSVD33

PADCTL_CAM_CFG2TMC_SOC_GPIO04_0

Offset: 0x74

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_SOC_GPIO04_0

Reset: 0x00000000 (0bxxxx,xxx0,0000,xxx0,0000,xxxx,xxxx,xxxx)

Bit Reset Description

24:20 0x0

CFG_CAL_DRVUP

16:12 0x0

CFG_CAL_DRVDN

PADCTL_CAM_SOC_GPIO05_0

Offset: 0x78

Read/Write: RW

Parity Protection: N

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SCR Protection: SCR_SOC_GPIO05_0

Reset: 0x00000454 (0bxxxx,xxxx,xxxx,xxxx,xxx0,x1x0,x1x1,0100)

Bit Reset Description

12 DISABLE

E_SCHMT:

= DISABLE0

= ENABLE1

10 SFIO

GPIO_SF_SEL:

= GPIO0

= SFIO1

8 DISABLE E_LPDR:

= DISABLE0

= ENABLE1

6 ENABLE E_INPUT:

= DISABLE0

= ENABLE1

4 TRISTATE TRISTATE:

= PASSTHROUGH0

= TRISTATE1

3:2 PULL_DOWN PUPD:

= NONE0

= PULL_DOWN1

= PULL_UP2

= RSVD3

1:0 RSVD0

PM:

= RSVD00

= IGPU1

= RSVD22

= RSVD33

PADCTL_CAM_CFG2TMC_SOC_GPIO05_0

Offset: 0x7c

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_SOC_GPIO05_0

Reset: 0x00000000 (0bxxxx,xxx0,0000,xxx0,0000,xxxx,xxxx,xxxx)

Bit Reset Description

24:20 0x0 CFG_CAL_DRVUP

16:12 0x0 CFG_CAL_DRVDN

PADCTL_CAM_SOC_GPIO06_0

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Offset: 0x80

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_SOC_GPIO06_0

Reset: 0x00000454 (0bxxxx,xxxx,xxxx,xxxx,xxx0,x1x0,x1x1,0100)

Bit Reset Description

12 DISABLE

E_SCHMT:

= DISABLE0

= ENABLE1

10 SFIO

GPIO_SF_SEL:

= GPIO0

= SFIO1

8 DISABLE

E_LPDR:

= DISABLE0

= ENABLE1

6 ENABLE

E_INPUT:

= DISABLE0

= ENABLE1

4 TRISTATE TRISTATE:

= PASSTHROUGH0

= TRISTATE1

3:2 PULL_DOWN PUPD:

= NONE0

= PULL_DOWN1

= PULL_UP2

= RSVD3

1:0 RSVD0

PM:

= RSVD00

= RSVD11

= RSVD22

= RSVD33

PADCTL_CAM_CFG2TMC_SOC_GPIO06_0

Offset: 0x84

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_SOC_GPIO06_0

Reset: 0x00000000 (0bxxxx,xxx0,0000,xxx0,0000,xxxx,xxxx,xxxx)

Bit Reset Description

24:20 0x0 CFG_CAL_DRVUP

16:12 0x0

CFG_CAL_DRVDN

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PADCTL_CAM_SOC_GPIO07_0

Offset: 0x88

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_SOC_GPIO07_0

Reset: 0x00000474 (0bxxxx,xxxx,xxxx,xxxx,xxx0,x1x0,x111,0100)

Bit Reset Description

12 DISABLE

E_SCHMT:

= DISABLE0

= ENABLE1

10 SFIO

GPIO_SF_SEL:

= GPIO0

= SFIO1

8 DISABLE E_LPDR:

= DISABLE0

= ENABLE1

6 ENABLE E_INPUT:

= DISABLE0

= ENABLE1

5 ENABLE E_IO_HV:

= DISABLE0

= ENABLE1

4 TRISTATE TRISTATE:

= PASSTHROUGH0

= TRISTATE1

3:2 PULL_DOWN PUPD:

= NONE0

= PULL_DOWN1

= PULL_UP2

= RSVD3

1:0 RSVD0

PM:

= RSVD00

= SATA1

= SOC2

= RSVD33

PADCTL_CAM_CFG2TMC_SOC_GPIO07_0

Offset: 0x8c

Read/Write: RW

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Parity Protection: N

SCR Protection: SCR_SOC_GPIO07_0

Reset: 0x00000000 (0bxxxx,xxx0,0000,xxx0,0000,xxxx,xxxx,xxxx)

Bit Reset Description

24:20 0x0 CFG_CAL_DRVUP

16:12 0x0 CFG_CAL_DRVDN

PADCTL_CAM_UART1_CTS_0

Offset: 0x90

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_UART1_CTS_0

Reset: 0x00000458 (0bxxxx,xxxx,xxxx,xxxx,xxx0,x1x0,x1x1,1000)

Bit Reset Description

12 DISABLE E_SCHMT:

= DISABLE0

= ENABLE1

10 SFIO GPIO_SF_SEL:

= GPIO0

= SFIO1

8 DISABLE E_LPDR:

= DISABLE0

= ENABLE1

6 ENABLE E_INPUT:

= DISABLE0

= ENABLE1

4 TRISTATE TRISTATE:

= PASSTHROUGH0

= TRISTATE1

3:2 PULL_UP

PUPD:

= NONE0

= PULL_DOWN1

= PULL_UP2

= RSVD3

1:0 UARTA PM:

= UARTA0

= RSVD11

= RSVD22

= RSVD33

PADCTL_CAM_CFG2TMC_UART1_CTS_0

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Offset: 0x94

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_UART1_CTS_0

Reset: 0x00000000 (0bxxxx,xxx0,0000,xxx0,0000,xxxx,xxxx,xxxx)

Bit Reset Description

24:20 0x0 CFG_CAL_DRVUP

16:12 0x0 CFG_CAL_DRVDN

PADCTL_CAM_UART1_RTS_0

Offset: 0x98

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_UART1_RTS_0

Reset: 0x00000414 (0bxxxx,xxxx,xxxx,xxxx,xxx0,x1x0,x0x1,0100)

Bit Reset Description

12 DISABLE E_SCHMT:

= DISABLE0

= ENABLE1

10 SFIO GPIO_SF_SEL:

= GPIO0

= SFIO1

8 DISABLE E_LPDR:

= DISABLE0

= ENABLE1

6 DISABLE

E_INPUT:

= DISABLE0

= ENABLE1

4 TRISTATE

TRISTATE:

= PASSTHROUGH0

= TRISTATE1

3:2 PULL_DOWN

PUPD:

= NONE0

= PULL_DOWN1

= PULL_UP2

= RSVD3

1:0

UARTA

PM:

= UARTA0

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Bit Reset Description

= RSVD11

= RSVD22

= RSVD33

PADCTL_CAM_CFG2TMC_UART1_RTS_0

Offset: 0x9c

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_UART1_RTS_0

Reset: 0x00000000 (0bxxxx,xxx0,0000,xxx0,0000,xxxx,xxxx,xxxx)

Bit Reset Description

24:20 0x0

CFG_CAL_DRVUP

16:12 0x0 CFG_CAL_DRVDN

PADCTL_CAM_UART1_RX_0

Offset: 0xa0

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_UART1_RX_0

Reset: 0x00000470 (0bxxxx,xxxx,xxxx,xxxx,xxx0,x1x0,x111,0000)

Bit Reset Description

12 DISABLE E_SCHMT:

= DISABLE0

= ENABLE1

10 SFIO

GPIO_SF_SEL:

= GPIO0

= SFIO1

8 DISABLE

E_LPDR:

= DISABLE0

= ENABLE1

6 ENABLE

E_INPUT:

= DISABLE0

= ENABLE1

5 ENABLE

E_IO_HV:

= DISABLE0

= ENABLE1

TRISTATE

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Bit Reset Description

TRISTATE:

= PASSTHROUGH0

= TRISTATE1

3:2 NONE PUPD:

= NONE0

= PULL_DOWN1

= PULL_UP2

= RSVD3

1:0 UARTA PM:

= UARTA0

= RSVD11

= RSVD22

= RSVD33

PADCTL_CAM_CFG2TMC_UART1_RX_0

Offset: 0xa4

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_UART1_RX_0

Reset: 0x00000000 (0bxxxx,xxx0,0000,xxx0,0000,xxxx,xxxx,xxxx)

Bit Reset Description

24:20 0x0

CFG_CAL_DRVUP

16:12 0x0

CFG_CAL_DRVDN

PADCTL_CAM_UART1_TX_0

Offset: 0xa8

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_UART1_TX_0

Reset: 0x00000434 (0bxxxx,xxxx,xxxx,xxxx,xxx0,x1x0,x011,0100)

Bit Reset Description

12 DISABLE

E_SCHMT:

= DISABLE0

= ENABLE1

10 SFIO

GPIO_SF_SEL:

= GPIO0

= SFIO1

DISABLE

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Bit Reset Description

E_LPDR:

= DISABLE0

= ENABLE1

6 DISABLE

E_INPUT:

= DISABLE0

= ENABLE1

5 ENABLE

E_IO_HV:

= DISABLE0

= ENABLE1

4 TRISTATE TRISTATE:

= PASSTHROUGH0

= TRISTATE1

3:2 PULL_DOWN PUPD:

= NONE0

= PULL_DOWN1

= PULL_UP2

= RSVD3

1:0 UARTA PM:

= UARTA0

= RSVD11

= RSVD22

= RSVD33

PADCTL_CAM_CFG2TMC_UART1_TX_0

Offset: 0xac

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_UART1_TX_0

Reset: 0x00000000 (0bxxxx,xxx0,0000,xxx0,0000,xxxx,xxxx,xxxx)

Bit Reset Description

24:20 0x0

CFG_CAL_DRVUP

16:12 0x0

CFG_CAL_DRVDN

Audio PAD Control Registers

PADCTL_AUDIO_SOC_GPIO33_0

Offset: 0x0

Read/Write: RW

Parity Protection: N

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SCR Protection: SCR_SOC_GPIO33_0

Reset: 0x00000458 (0bxxxx,xxxx,xxxx,xxxx,xxx0,x1x0,x1x1,1000)

Bit Reset Description

12 DISABLE

E_SCHMT:

= DISABLE0

= ENABLE1

10 SFIO

GPIO_SF_SEL:

= GPIO0

= SFIO1

8 DISABLE E_LPDR:

= DISABLE0

= ENABLE1

6 ENABLE E_INPUT:

= DISABLE0

= ENABLE1

4 TRISTATE TRISTATE:

= PASSTHROUGH0

= TRISTATE1

3:2 PULL_UP PUPD:

= NONE0

= PULL_DOWN1

= PULL_UP2

= RSVD3

1:0 RSVD0

PM:

= RSVD00

= SPDIF1

= RSVD22

= RSVD33

PADCTL_AUDIO_CFG2TMC_SOC_GPIO33_0

Offset: 0x4

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_SOC_GPIO33_0

Reset: 0x00000000 (0bxxxx,xxx0,0000,xxx0,0000,xxxx,xxxx,xxxx)

Bit Reset Description

24:20 0x0 CFG_CAL_DRVUP

16:12 0x0 CFG_CAL_DRVDN

PADCTL_AUDIO_SOC_GPIO32_0

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Offset: 0x8

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_SOC_GPIO32_0

Reset: 0x00000454 (0bxxxx,xxxx,xxxx,xxxx,xxx0,x1x0,x1x1,0100)

Bit Reset Description

12 DISABLE

E_SCHMT:

= DISABLE0

= ENABLE1

10 SFIO

GPIO_SF_SEL:

= GPIO0

= SFIO1

8 DISABLE

E_LPDR:

= DISABLE0

= ENABLE1

6 ENABLE

E_INPUT:

= DISABLE0

= ENABLE1

4 TRISTATE TRISTATE:

= PASSTHROUGH0

= TRISTATE1

3:2 PULL_DOWN PUPD:

= NONE0

= PULL_DOWN1

= PULL_UP2

= RSVD3

1:0 RSVD0

PM:

= RSVD00

= SPDIF1

= RSVD22

= RSVD33

PADCTL_AUDIO_CFG2TMC_SOC_GPIO32_0

Offset: 0xc

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_SOC_GPIO32_0

Reset: 0x00000000 (0bxxxx,xxx0,0000,xxx0,0000,xxxx,xxxx,xxxx)

Bit Reset Description

24:20 0x0 CFG_CAL_DRVUP

16:12 0x0

CFG_CAL_DRVDN

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PADCTL_AUDIO_SOC_GPIO31_0

Offset: 0x10

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_SOC_GPIO31_0

Reset: 0x00000454 (0bxxxx,xxxx,xxxx,xxxx,xxx0,x1x0,x1x1,0100)

Bit Reset Description

12 DISABLE

E_SCHMT:

= DISABLE0

= ENABLE1

10 SFIO

GPIO_SF_SEL:

= GPIO0

= SFIO1

8 DISABLE E_LPDR:

= DISABLE0

= ENABLE1

6 ENABLE E_INPUT:

= DISABLE0

= ENABLE1

4 TRISTATE TRISTATE:

= PASSTHROUGH0

= TRISTATE1

3:2 PULL_DOWN PUPD:

= NONE0

= PULL_DOWN1

= PULL_UP2

= RSVD3

1:0 RSVD0

PM:

= RSVD00

= SDMMC11

= RSVD22

= RSVD33

PADCTL_AUDIO_CFG2TMC_SOC_GPIO31_0

Offset: 0x14

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_SOC_GPIO31_0

Reset: 0x00000000 (0bxxxx,xxx0,0000,xxx0,0000,xxxx,xxxx,xxxx)

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Bit Reset Description

24:20 0x0 CFG_CAL_DRVUP

16:12 0x0 CFG_CAL_DRVDN

PADCTL_AUDIO_SOC_GPIO30_0

Offset: 0x18

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_SOC_GPIO30_0

Reset: 0x00000454 (0bxxxx,xxxx,xxxx,xxxx,xxx0,x1x0,x1x1,0100)

Bit Reset Description

12 DISABLE

E_SCHMT:

= DISABLE0

= ENABLE1

10 SFIO

GPIO_SF_SEL:

= GPIO0

= SFIO1

8 DISABLE E_LPDR:

= DISABLE0

= ENABLE1

6 ENABLE E_INPUT:

= DISABLE0

= ENABLE1

4 TRISTATE TRISTATE:

= PASSTHROUGH0

= TRISTATE1

3:2 PULL_DOWN PUPD:

= NONE0

= PULL_DOWN1

= PULL_UP2

= RSVD3

1:0 RSVD0

PM:

= RSVD00

= RSVD11

= RSVD22

= RSVD33

PADCTL_AUDIO_CFG2TMC_SOC_GPIO30_0

Offset: 0x1c

Read/Write: RW

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Parity Protection: N

SCR Protection: SCR_SOC_GPIO30_0

Reset: 0x00000000 (0bxxxx,xxx0,0000,xxx0,0000,xxxx,xxxx,xxxx)

Bit Reset Description

24:20 0x0

CFG_CAL_DRVUP

16:12 0x0

CFG_CAL_DRVDN

PADCTL_AUDIO_AUD_MCLK_0

Offset: 0x20

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_AUD_MCLK_0

Reset: 0x00000414 (0bxxxx,xxxx,xxxx,xxxx,xxx0,x1x0,x0x1,0100)

Bit Reset Description

12 DISABLE

E_SCHMT:

= DISABLE0

= ENABLE1

10 SFIO

GPIO_SF_SEL:

= GPIO0

= SFIO1

8 DISABLE

E_LPDR:

= DISABLE0

= ENABLE1

6 DISABLE

E_INPUT:

= DISABLE0

= ENABLE1

4 TRISTATE TRISTATE:

= PASSTHROUGH0

= TRISTATE1

3:2 PULL_DOWN PUPD:

= NONE0

= PULL_DOWN1

= PULL_UP2

= RSVD3

1:0 AUD

PM:

= AUD0

= RSVD11

= RSVD22

= RSVD33

PADCTL_AUDIO_CFG2TMC_AUD_MCLK_0

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Offset: 0x24

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_AUD_MCLK_0

Reset: 0x00000000 (0bxxxx,xxx0,0000,xxx0,0000,xxxx,xxxx,xxxx)

Bit Reset Description

24:20 0x0 CFG_CAL_DRVUP

16:12 0x0

CFG_CAL_DRVDN

PADCTL_AUDIO_DAP1_FS_0

Offset: 0x28

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_DAP1_FS_0

Reset: 0x00000454 (0bxxxx,xxxx,xxxx,xxxx,xxx0,x1x0,x1x1,0100)

Bit Reset Description

12 DISABLE

E_SCHMT:

= DISABLE0

= ENABLE1

10 SFIO

GPIO_SF_SEL:

= GPIO0

= SFIO1

8 DISABLE E_LPDR:

= DISABLE0

= ENABLE1

6 ENABLE E_INPUT:

= DISABLE0

= ENABLE1

4 TRISTATE TRISTATE:

= PASSTHROUGH0

= TRISTATE1

3:2 PULL_DOWN PUPD:

= NONE0

= PULL_DOWN1

= PULL_UP2

= RSVD3

1:0

I2S1

PM:

= I2S10

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Bit Reset Description

= RSVD11

= RSVD22

= RSVD33

PADCTL_AUDIO_CFG2TMC_DAP1_FS_0

Offset: 0x2c

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_DAP1_FS_0

Reset: 0x00000000 (0bxxxx,xxx0,0000,xxx0,0000,xxxx,xxxx,xxxx)

Bit Reset Description

24:20 0x0 CFG_CAL_DRVUP

16:12 0x0 CFG_CAL_DRVDN

PADCTL_AUDIO_DAP1_DIN_0

Offset: 0x30

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_DAP1_DIN_0

Reset: 0x00000454 (0bxxxx,xxxx,xxxx,xxxx,xxx0,x1x0,x1x1,0100)

Bit Reset Description

12 DISABLE E_SCHMT:

= DISABLE0

= ENABLE1

10 SFIO GPIO_SF_SEL:

= GPIO0

= SFIO1

8 DISABLE E_LPDR:

= DISABLE0

= ENABLE1

6 ENABLE E_INPUT:

= DISABLE0

= ENABLE1

4 TRISTATE TRISTATE:

= PASSTHROUGH0

= TRISTATE1

3:2

PULL_DOWN

PUPD:

= NONE0

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Bit Reset Description

= PULL_DOWN1

= PULL_UP2

= RSVD3

1:0 I2S1

PM:

= I2S10

= RSVD11

= RSVD22

= RSVD33

PADCTL_AUDIO_CFG2TMC_DAP1_DIN_0

Offset: 0x34

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_DAP1_DIN_0

Reset: 0x00000000 (0bxxxx,xxx0,0000,xxx0,0000,xxxx,xxxx,xxxx)

Bit Reset Description

24:20 0x0 CFG_CAL_DRVUP

16:12 0x0 CFG_CAL_DRVDN

PADCTL_AUDIO_DAP1_DOUT_0

Offset: 0x38

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_DAP1_DOUT_0

Reset: 0x00000414 (0bxxxx,xxxx,xxxx,xxxx,xxx0,x1x0,x0x1,0100)

Bit Reset Description

12 DISABLE

E_SCHMT:

= DISABLE0

= ENABLE1

10 SFIO

GPIO_SF_SEL:

= GPIO0

= SFIO1

8 DISABLE E_LPDR:

= DISABLE0

= ENABLE1

6 DISABLE E_INPUT:

= DISABLE0

= ENABLE1

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Bit Reset Description

4 TRISTATE TRISTATE:

= PASSTHROUGH0

= TRISTATE1

3:2 PULL_DOWN PUPD:

= NONE0

= PULL_DOWN1

= PULL_UP2

= RSVD3

1:0 I2S1

PM:

= I2S10

= RSVD11

= RSVD22

= RSVD33

PADCTL_AUDIO_CFG2TMC_DAP1_DOUT_0

Offset: 0x3c

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_DAP1_DOUT_0

Reset: 0x00000000 (0bxxxx,xxx0,0000,xxx0,0000,xxxx,xxxx,xxxx)

Bit Reset Description

24:20 0x0 CFG_CAL_DRVUP

16:12 0x0

CFG_CAL_DRVDN

PADCTL_AUDIO_DAP1_SCLK_0

Offset: 0x40

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_DAP1_SCLK_0

Reset: 0x00000454 (0bxxxx,xxxx,xxxx,xxxx,xxx0,x1x0,x1x1,0100)

Bit Reset Description

12 DISABLE

E_SCHMT:

= DISABLE0

= ENABLE1

10 SFIO

GPIO_SF_SEL:

= GPIO0

= SFIO1

DISABLE

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Bit Reset Description

E_LPDR:

= DISABLE0

= ENABLE1

6 ENABLE

E_INPUT:

= DISABLE0

= ENABLE1

4 TRISTATE

TRISTATE:

= PASSTHROUGH0

= TRISTATE1

3:2 PULL_DOWN

PUPD:

= NONE0

= PULL_DOWN1

= PULL_UP2

= RSVD3

1:0 I2S1 PM:

= I2S10

= RSVD11

= RSVD22

= RSVD33

PADCTL_AUDIO_CFG2TMC_DAP1_SCLK_0

Offset: 0x44

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_DAP1_SCLK_0

Reset: 0x00000000 (0bxxxx,xxx0,0000,xxx0,0000,xxxx,xxxx,xxxx)

Bit Reset Description

24:20 0x0

CFG_CAL_DRVUP

16:12 0x0

CFG_CAL_DRVDN

PADCTL_AUDIO_DAP3_FS_0

Offset: 0x48

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_DAP3_FS_0

Reset: 0x00000454 (0bxxxx,xxxx,xxxx,xxxx,xxx0,x1x0,x1x1,0100)

Bit Reset Description

DISABLE

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Bit Reset Description

E_SCHMT:

= DISABLE0

= ENABLE1

10 SFIO GPIO_SF_SEL:

= GPIO0

= SFIO1

8 DISABLE E_LPDR:

= DISABLE0

= ENABLE1

6 ENABLE E_INPUT:

= DISABLE0

= ENABLE1

4 TRISTATE

TRISTATE:

= PASSTHROUGH0

= TRISTATE1

3:2 PULL_DOWN

PUPD:

= NONE0

= PULL_DOWN1

= PULL_UP2

= RSVD3

1:0 I2S3 PM:

= I2S30

= DMIC21

= RSVD22

= RSVD33

PADCTL_AUDIO_CFG2TMC_DAP3_FS_0

Offset: 0x4c

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_DAP3_FS_0

Reset: 0x00000000 (0bxxxx,xxx0,0000,xxx0,0000,xxxx,xxxx,xxxx)

Bit Reset Description

24:20 0x0 CFG_CAL_DRVUP

16:12 0x0 CFG_CAL_DRVDN

PADCTL_AUDIO_DAP3_DIN_0

Offset: 0x50

Read/Write: RW

Parity Protection: N

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SCR Protection: SCR_DAP3_DIN_0

Reset: 0x00000454 (0bxxxx,xxxx,xxxx,xxxx,xxx0,x1x0,x1x1,0100)

Bit Reset Description

12 DISABLE E_SCHMT:

= DISABLE0

= ENABLE1

10 SFIO GPIO_SF_SEL:

= GPIO0

= SFIO1

8 DISABLE E_LPDR:

= DISABLE0

= ENABLE1

6 ENABLE

E_INPUT:

= DISABLE0

= ENABLE1

4 TRISTATE

TRISTATE:

= PASSTHROUGH0

= TRISTATE1

3:2 PULL_DOWN

PUPD:

= NONE0

= PULL_DOWN1

= PULL_UP2

= RSVD3

1:0 I2S3 PM:

= I2S30

= DMIC21

= RSVD22

= RSVD33

PADCTL_AUDIO_CFG2TMC_DAP3_DIN_0

Offset: 0x54

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_DAP3_DIN_0

Reset: 0x00000000 (0bxxxx,xxx0,0000,xxx0,0000,xxxx,xxxx,xxxx)

Bit Reset Description

24:20 0x0 CFG_CAL_DRVUP

16:12 0x0 CFG_CAL_DRVDN

PADCTL_AUDIO_DAP3_DOUT_0

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Offset: 0x58

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_DAP3_DOUT_0

Reset: 0x00000414 (0bxxxx,xxxx,xxxx,xxxx,xxx0,x1x0,x0x1,0100)

Bit Reset Description

12 DISABLE E_SCHMT:

= DISABLE0

= ENABLE1

10 SFIO GPIO_SF_SEL:

= GPIO0

= SFIO1

8 DISABLE E_LPDR:

= DISABLE0

= ENABLE1

6 DISABLE E_INPUT:

= DISABLE0

= ENABLE1

4 TRISTATE TRISTATE:

= PASSTHROUGH0

= TRISTATE1

3:2 PULL_DOWN

PUPD:

= NONE0

= PULL_DOWN1

= PULL_UP2

= RSVD3

1:0 I2S3 PM:

= I2S30

= DMIC11

= RSVD22

= RSVD33

PADCTL_AUDIO_CFG2TMC_DAP3_DOUT_0

Offset: 0x5c

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_DAP3_DOUT_0

Reset: 0x00000000 (0bxxxx,xxx0,0000,xxx0,0000,xxxx,xxxx,xxxx)

Bit Reset Description

24:20 0x0 CFG_CAL_DRVUP

16:12 0x0 CFG_CAL_DRVDN

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PADCTL_AUDIO_DAP3_SCLK_0

Offset: 0x60

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_DAP3_SCLK_0

Reset: 0x00000454 (0bxxxx,xxxx,xxxx,xxxx,xxx0,x1x0,x1x1,0100)

Bit Reset Description

12 DISABLE E_SCHMT:

= DISABLE0

= ENABLE1

10 SFIO GPIO_SF_SEL:

= GPIO0

= SFIO1

8 DISABLE E_LPDR:

= DISABLE0

= ENABLE1

6 ENABLE

E_INPUT:

= DISABLE0

= ENABLE1

4 TRISTATE

TRISTATE:

= PASSTHROUGH0

= TRISTATE1

3:2 PULL_DOWN

PUPD:

= NONE0

= PULL_DOWN1

= PULL_UP2

= RSVD3

1:0 I2S3 PM:

= I2S30

= DMIC11

= RSVD22

= RSVD33

PADCTL_AUDIO_CFG2TMC_DAP3_SCLK_0

Offset: 0x64

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_DAP3_SCLK_0

Reset: 0x00000000 (0bxxxx,xxx0,0000,xxx0,0000,xxxx,xxxx,xxxx)

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Bit Reset Description

24:20 0x0 CFG_CAL_DRVUP

16:12 0x0

CFG_CAL_DRVDN

PADCTL_AUDIO_DAP5_FS_0

Offset: 0x68

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_DAP5_FS_0

Reset: 0x00000454 (0bxxxx,xxxx,xxxx,xxxx,xxx0,x1x0,x1x1,0100)

Bit Reset Description

12 DISABLE E_SCHMT:

= DISABLE0

= ENABLE1

10 SFIO GPIO_SF_SEL:

= GPIO0

= SFIO1

8 DISABLE E_LPDR:

= DISABLE0

= ENABLE1

6 ENABLE

E_INPUT:

= DISABLE0

= ENABLE1

4 TRISTATE

TRISTATE:

= PASSTHROUGH0

= TRISTATE1

3:2 PULL_DOWN

PUPD:

= NONE0

= PULL_DOWN1

= PULL_UP2

= RSVD3

1:0 I2S5 PM:

= I2S50

= DMIC41

= DSPK12

= RSVD33

PADCTL_AUDIO_CFG2TMC_DAP5_FS_0

Offset: 0x6c

Read/Write: RW

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Parity Protection: N

SCR Protection: SCR_DAP5_FS_0

Reset: 0x00000000 (0bxxxx,xxx0,0000,xxx0,0000,xxxx,xxxx,xxxx)

Bit Reset Description

24:20 0x0 CFG_CAL_DRVUP

16:12 0x0 CFG_CAL_DRVDN

PADCTL_AUDIO_DAP5_DIN_0

Offset: 0x70

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_DAP5_DIN_0

Reset: 0x00000454 (0bxxxx,xxxx,xxxx,xxxx,xxx0,x1x0,x1x1,0100)

Bit Reset Description

12 DISABLE E_SCHMT:

= DISABLE0

= ENABLE1

10 SFIO GPIO_SF_SEL:

= GPIO0

= SFIO1

8 DISABLE E_LPDR:

= DISABLE0

= ENABLE1

6 ENABLE E_INPUT:

= DISABLE0

= ENABLE1

4 TRISTATE TRISTATE:

= PASSTHROUGH0

= TRISTATE1

3:2 PULL_DOWN

PUPD:

= NONE0

= PULL_DOWN1

= PULL_UP2

= RSVD3

1:0 I2S5 PM:

= I2S50

= DMIC41

= DSPK12

= RSVD33

PADCTL_AUDIO_CFG2TMC_DAP5_DIN_0

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Offset: 0x74

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_DAP5_DIN_0

Reset: 0x00000000 (0bxxxx,xxx0,0000,xxx0,0000,xxxx,xxxx,xxxx)

Bit Reset Description

24:20 0x0 CFG_CAL_DRVUP

16:12 0x0 CFG_CAL_DRVDN

PADCTL_AUDIO_DAP5_DOUT_0

Offset: 0x78

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_DAP5_DOUT_0

Reset: 0x00000414 (0bxxxx,xxxx,xxxx,xxxx,xxx0,x1x0,x0x1,0100)

Bit Reset Description

12 DISABLE E_SCHMT:

= DISABLE0

= ENABLE1

10 SFIO GPIO_SF_SEL:

= GPIO0

= SFIO1

8 DISABLE E_LPDR:

= DISABLE0

= ENABLE1

6 DISABLE

E_INPUT:

= DISABLE0

= ENABLE1

4 TRISTATE

TRISTATE:

= PASSTHROUGH0

= TRISTATE1

3:2 PULL_DOWN

PUPD:

= NONE0

= PULL_DOWN1

= PULL_UP2

= RSVD3

1:0

I2S5

PM:

= I2S50

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Bit Reset Description

= DSPK01

= RSVD22

= RSVD33

PADCTL_AUDIO_CFG2TMC_DAP5_DOUT_0

Offset: 0x7c

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_DAP5_DOUT_0

Reset: 0x00000000 (0bxxxx,xxx0,0000,xxx0,0000,xxxx,xxxx,xxxx)

Bit Reset Description

24:20 0x0

CFG_CAL_DRVUP

16:12 0x0 CFG_CAL_DRVDN

PADCTL_AUDIO_DAP5_SCLK_0

Offset: 0x80

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_DAP5_SCLK_0

Reset: 0x00000454 (0bxxxx,xxxx,xxxx,xxxx,xxx0,x1x0,x1x1,0100)

Bit Reset Description

12 DISABLE E_SCHMT:

= DISABLE0

= ENABLE1

10 SFIO

GPIO_SF_SEL:

= GPIO0

= SFIO1

8 DISABLE

E_LPDR:

= DISABLE0

= ENABLE1

6 ENABLE

E_INPUT:

= DISABLE0

= ENABLE1

4 TRISTATE

TRISTATE:

= PASSTHROUGH0

= TRISTATE1

3:2

PULL_DOWN

PUPD:

= NONE0

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Bit Reset Description

= PULL_DOWN1

= PULL_UP2

= RSVD3

1:0 I2S5 PM:

= I2S50

= DSPK01

= RSVD22

= RSVD33

PADCTL_AUDIO_CFG2TMC_DAP5_SCLK_0

Offset: 0x84

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_DAP5_SCLK_0

Reset: 0x00000000 (0bxxxx,xxx0,0000,xxx0,0000,xxxx,xxxx,xxxx)

Bit Reset Description

24:20 0x0 CFG_CAL_DRVUP

16:12 0x0 CFG_CAL_DRVDN

Audio High Voltage PAD Control Registers

PADCTL_AUDIO_HV_DAP6_FS_0

Offset: 0x0

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_DAP6_FS_0

Reset: 0x0000c454 (0b0000,0000,0000,xxx0,1100,x10x,x1x1,0100)

Bit Reset Description

31:28 0x0 SPARE_VDD

27:24 0x0 SPARE_VAUXC

23:20 0x0 RFU_IN

16:15 0x1 SCHMITT

14:13

DEFAULT_DRIVE_1X

DRV_TYPE:

DRV_TYPE[0]:

0 = 1X driver;

1 = 2X driver;

DRV_TYPE[1]:

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Bit Reset Description

0 = Driving codes from BDSDMEMCOMP;

1 = Default driving codes;

= COMP_DRIVE_1X0

= COMP_DRIVE_2X1

= DEFAULT_DRIVE_1X2

= DEFAULT_DRIVE_2X3

12 DISABLE E_SCHMT:

= DISABLE0

= ENABLE1

10 SFIO GPIO_SF_SEL:

= GPIO0

= SFIO1

9 DISABLE E_PBIAS_BUF:

= DISABLE0

= ENABLE1

6 ENABLE E_INPUT:

= DISABLE0

= ENABLE1

4 TRISTATE

TRISTATE:

= PASSTHROUGH0

= TRISTATE1

3:2 PULL_DOWN

PUPD:

= NONE0

= PULL_DOWN1

= PULL_UP2

= RSVD3

1:0 I2S6 PM:

= I2S60

= IQC11

= RSVD22

= RSVD33

PADCTL_AUDIO_HV_CFG2TMC_DAP6_FS_0

Offset: 0x4

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_DAP6_FS_0

Reset: 0x00000000 (0b0000,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:30 0x0 CFG_CAL_DRVUP_DEF

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Bit Reset Description

29:28 0x0 CFG_CAL_DRVDN_DEF

PADCTL_AUDIO_HV_DAP6_DIN_0

Offset: 0x8

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_DAP6_DIN_0

Reset: 0x0000c454 (0b0000,0000,0000,xxx0,1100,x10x,x1x1,0100)

Bit Reset Description

31:28 0x0 SPARE_VDD

27:24 0x0

SPARE_VAUXC

23:20 0x0

RFU_IN

16:15 0x1

SCHMITT

14:13 DEFAULT_DRIVE_1X DRV_TYPE:

DRV_TYPE[0]:

0 = 1X driver;

1 = 2X driver;

DRV_TYPE[1]:

0 = Driving codes from BDSDMEMCOMP;

1 = Default driving codes;

= COMP_DRIVE_1X0

= COMP_DRIVE_2X1

= DEFAULT_DRIVE_1X2

= DEFAULT_DRIVE_2X3

12 DISABLE E_SCHMT:

= DISABLE0

= ENABLE1

10 SFIO

GPIO_SF_SEL:

= GPIO0

= SFIO1

9 DISABLE

E_PBIAS_BUF:

= DISABLE0

= ENABLE1

6 ENABLE E_INPUT:

= DISABLE0

= ENABLE1

4 TRISTATE TRISTATE:

= PASSTHROUGH0

= TRISTATE1

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Bit Reset Description

3:2 PULL_DOWN

PUPD:

= NONE0

= PULL_DOWN1

= PULL_UP2

= RSVD3

1:0 I2S6 PM:

= I2S60

= IQC11

= RSVD22

= RSVD33

PADCTL_AUDIO_HV_CFG2TMC_DAP6_DIN_0

Offset: 0xc

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_DAP6_DIN_0

Reset: 0x00000000 (0b0000,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:30 0x0 CFG_CAL_DRVUP_DEF

29:28 0x0 CFG_CAL_DRVDN_DEF

PADCTL_AUDIO_HV_DAP6_DOUT_0

Offset: 0x10

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_DAP6_DOUT_0

Reset: 0x0000c414 (0b0000,0000,0000,xxx0,1100,x10x,x0x1,0100)

Bit Reset Description

31:28 0x0 SPARE_VDD

27:24 0x0 SPARE_VAUXC

23:20 0x0

RFU_IN

16:15 0x1

SCHMITT

14:13

DEFAULT_DRIVE_1X

DRV_TYPE:

DRV_TYPE[0]:

0 = 1X driver;

1 = 2X driver;

DRV_TYPE[1]:

0 = Driving codes from BDSDMEMCOMP;

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Bit Reset Description

1 = Default driving codes;

= COMP_DRIVE_1X0

= COMP_DRIVE_2X1

= DEFAULT_DRIVE_1X2

= DEFAULT_DRIVE_2X3

12 DISABLE E_SCHMT:

= DISABLE0

= ENABLE1

10 SFIO GPIO_SF_SEL:

= GPIO0

= SFIO1

9 DISABLE E_PBIAS_BUF:

= DISABLE0

= ENABLE1

6 DISABLE

E_INPUT:

= DISABLE0

= ENABLE1

4 TRISTATE

TRISTATE:

= PASSTHROUGH0

= TRISTATE1

3:2 PULL_DOWN PUPD:

= NONE0

= PULL_DOWN1

= PULL_UP2

= RSVD3

1:0 I2S6 PM:

= I2S60

= IQC11

= RSVD22

= RSVD33

PADCTL_AUDIO_HV_CFG2TMC_DAP6_DOUT_0

Offset: 0x14

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_DAP6_DOUT_0

Reset: 0x00000000 (0b0000,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:30 0x0

CFG_CAL_DRVUP_DEF

29:28 0x0 CFG_CAL_DRVDN_DEF

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PADCTL_AUDIO_HV_DAP6_SCLK_0

Offset: 0x18

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_DAP6_SCLK_0

Reset: 0x0000c454 (0b0000,0000,0000,xxx0,1100,x10x,x1x1,0100)

Bit Reset Description

31:28 0x0 SPARE_VDD

27:24 0x0 SPARE_VAUXC

23:20 0x0 RFU_IN

16:15 0x1 SCHMITT

14:13 DEFAULT_DRIVE_1X DRV_TYPE:

DRV_TYPE[0]:

0 = 1X driver;

1 = 2X driver;

DRV_TYPE[1]:

0 = Driving codes from BDSDMEMCOMP;

1 = Default driving codes;

= COMP_DRIVE_1X0

= COMP_DRIVE_2X1

= DEFAULT_DRIVE_1X2

= DEFAULT_DRIVE_2X3

12 DISABLE E_SCHMT:

= DISABLE0

= ENABLE1

10 SFIO GPIO_SF_SEL:

= GPIO0

= SFIO1

9 DISABLE E_PBIAS_BUF:

= DISABLE0

= ENABLE1

6 ENABLE E_INPUT:

= DISABLE0

= ENABLE1

4 TRISTATE

TRISTATE:

= PASSTHROUGH0

= TRISTATE1

3:2

PULL_DOWN

PUPD:

= NONE0

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Bit Reset Description

= PULL_DOWN1

= PULL_UP2

= RSVD3

1:0 I2S6 PM:

= I2S60

= IQC11

= RSVD22

= RSVD33

PADCTL_AUDIO_HV_CFG2TMC_DAP6_SCLK_0

Offset: 0x1c

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_DAP6_SCLK_0

Reset: 0x00000000 (0b0000,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:30 0x0

CFG_CAL_DRVUP_DEF

29:28 0x0 CFG_CAL_DRVDN_DEF

PADCTL_AUDIO_HV_DAP4_FS_0

Offset: 0x20

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_DAP4_FS_0

Reset: 0x0000c454 (0b0000,0000,0000,xxx0,1100,x10x,x1x1,0100)

Bit Reset Description

31:28 0x0 SPARE_VDD

27:24 0x0 SPARE_VAUXC

23:20 0x0 RFU_IN

16:15 0x1

SCHMITT

14:13

DEFAULT_DRIVE_1X

DRV_TYPE:

DRV_TYPE[0]:

0 = 1X driver;

1 = 2X driver;

DRV_TYPE[1]:

0 = Driving codes from BDSDMEMCOMP;

1 = Default driving codes;

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Bit Reset Description

= COMP_DRIVE_1X0

= COMP_DRIVE_2X1

= DEFAULT_DRIVE_1X2

= DEFAULT_DRIVE_2X3

12 DISABLE E_SCHMT:

= DISABLE0

= ENABLE1

10 SFIO GPIO_SF_SEL:

= GPIO0

= SFIO1

9 DISABLE E_PBIAS_BUF:

= DISABLE0

= ENABLE1

6 ENABLE

E_INPUT:

= DISABLE0

= ENABLE1

4 TRISTATE

TRISTATE:

= PASSTHROUGH0

= TRISTATE1

3:2 PULL_DOWN PUPD:

= NONE0

= PULL_DOWN1

= PULL_UP2

= RSVD3

1:0 I2S4 PM:

= I2S40

= IQC21

= RSVD22

= RSVD33

PADCTL_AUDIO_HV_CFG2TMC_DAP4_FS_0

Offset: 0x24

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_DAP4_FS_0

Reset: 0x00000000 (0b0000,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:30 0x0

CFG_CAL_DRVUP_DEF

29:28 0x0 CFG_CAL_DRVDN_DEF

PADCTL_AUDIO_HV_DAP4_DIN_0

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Offset: 0x28

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_DAP4_DIN_0

Reset: 0x0000c454 (0b0000,0000,0000,xxx0,1100,x10x,x1x1,0100)

Bit Reset Description

31:28 0x0 SPARE_VDD

27:24 0x0 SPARE_VAUXC

23:20 0x0 RFU_IN

16:15 0x1 SCHMITT

14:13 DEFAULT_DRIVE_1X DRV_TYPE:

DRV_TYPE[0]:

0 = 1X driver;

1 = 2X driver;

DRV_TYPE[1]:

0 = Driving codes from BDSDMEMCOMP;

1 = Default driving codes;

= COMP_DRIVE_1X0

= COMP_DRIVE_2X1

= DEFAULT_DRIVE_1X2

= DEFAULT_DRIVE_2X3

12 DISABLE E_SCHMT:

= DISABLE0

= ENABLE1

10 SFIO GPIO_SF_SEL:

= GPIO0

= SFIO1

9 DISABLE E_PBIAS_BUF:

= DISABLE0

= ENABLE1

6 ENABLE E_INPUT:

= DISABLE0

= ENABLE1

4 TRISTATE

TRISTATE:

= PASSTHROUGH0

= TRISTATE1

3:2 PULL_DOWN

PUPD:

= NONE0

= PULL_DOWN1

= PULL_UP2

= RSVD3

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Bit Reset Description

1:0 I2S4 PM:

= I2S40

= IQC21

= RSVD22

= RSVD33

PADCTL_AUDIO_HV_CFG2TMC_DAP4_DIN_0

Offset: 0x2c

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_DAP4_DIN_0

Reset: 0x00000000 (0b0000,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:30 0x0

CFG_CAL_DRVUP_DEF

29:28 0x0

CFG_CAL_DRVDN_DEF

PADCTL_AUDIO_HV_DAP4_DOUT_0

Offset: 0x30

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_DAP4_DOUT_0

Reset: 0x0000c414 (0b0000,0000,0000,xxx0,1100,x10x,x0x1,0100)

Bit Reset Description

31:28 0x0

SPARE_VDD

27:24 0x0 SPARE_VAUXC

23:20 0x0 RFU_IN

16:15 0x1 SCHMITT

14:13 DEFAULT_DRIVE_1X DRV_TYPE:

DRV_TYPE[0]:

0 = 1X driver;

1 = 2X driver;

DRV_TYPE[1]:

0 = Driving codes from BDSDMEMCOMP;

1 = Default driving codes;

= COMP_DRIVE_1X0

= COMP_DRIVE_2X1

= DEFAULT_DRIVE_1X2

= DEFAULT_DRIVE_2X3

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Bit Reset Description

12 DISABLE E_SCHMT:

= DISABLE0

= ENABLE1

10 SFIO GPIO_SF_SEL:

= GPIO0

= SFIO1

9 DISABLE E_PBIAS_BUF:

= DISABLE0

= ENABLE1

6 DISABLE E_INPUT:

= DISABLE0

= ENABLE1

4 TRISTATE TRISTATE:

= PASSTHROUGH0

= TRISTATE1

3:2 PULL_DOWN

PUPD:

= NONE0

= PULL_DOWN1

= PULL_UP2

= RSVD3

1:0 I2S4 PM:

= I2S40

= IQC21

= RSVD22

= RSVD33

PADCTL_AUDIO_HV_CFG2TMC_DAP4_DOUT_0

Offset: 0x34

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_DAP4_DOUT_0

Reset: 0x00000000 (0b0000,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:30 0x0 CFG_CAL_DRVUP_DEF

29:28 0x0 CFG_CAL_DRVDN_DEF

PADCTL_AUDIO_HV_DAP4_SCLK_0

Offset: 0x38

Read/Write: RW

Parity Protection: N

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SCR Protection: SCR_DAP4_SCLK_0

Reset: 0x0000c454 (0b0000,0000,0000,xxx0,1100,x10x,x1x1,0100)

Bit Reset Description

31:28 0x0 SPARE_VDD

27:24 0x0 SPARE_VAUXC

23:20 0x0

RFU_IN

16:15 0x1

SCHMITT

14:13 DEFAULT_DRIVE_1X

DRV_TYPE:

DRV_TYPE[0]:

0 = 1X driver;

1 = 2X driver;

DRV_TYPE[1]:

0 = Driving codes from BDSDMEMCOMP;

1 = Default driving codes;

= COMP_DRIVE_1X0

= COMP_DRIVE_2X1

= DEFAULT_DRIVE_1X2

= DEFAULT_DRIVE_2X3

12 DISABLE

E_SCHMT:

= DISABLE0

= ENABLE1

10 SFIO

GPIO_SF_SEL:

= GPIO0

= SFIO1

9 DISABLE E_PBIAS_BUF:

= DISABLE0

= ENABLE1

6 ENABLE E_INPUT:

= DISABLE0

= ENABLE1

4 TRISTATE TRISTATE:

= PASSTHROUGH0

= TRISTATE1

3:2 PULL_DOWN PUPD:

= NONE0

= PULL_DOWN1

= PULL_UP2

= RSVD3

1:0

I2S4

PM:

= I2S40

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Bit Reset Description

= IQC21

= RSVD22

= RSVD33

PADCTL_AUDIO_HV_CFG2TMC_DAP4_SCLK_0

Offset: 0x3c

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_DAP4_SCLK_0

Reset: 0x00000000 (0b0000,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:30 0x0 CFG_CAL_DRVUP_DEF

29:28 0x0 CFG_CAL_DRVDN_DEF

CONN PAD Control Registers

PADCTL_CONN_DAP2_DIN_0

Offset: 0x0

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_DAP2_DIN_0

Reset: 0x00000454 (0bxxxx,xxxx,xxxx,xxxx,xxx0,x1x0,x1x1,0100)

Bit Reset Description

12 DISABLE

E_SCHMT:

= DISABLE0

= ENABLE1

10 SFIO GPIO_SF_SEL:

= GPIO0

= SFIO1

8 DISABLE E_LPDR:

= DISABLE0

= ENABLE1

6 ENABLE E_INPUT:

= DISABLE0

= ENABLE1

TRISTATE

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Bit Reset Description

TRISTATE:

= PASSTHROUGH0

= TRISTATE1

3:2 PULL_DOWN

PUPD:

= NONE0

= PULL_DOWN1

= PULL_UP2

= RSVD3

1:0 I2S2 PM:

= I2S20

= RSVD11

= RSVD22

= RSVD33

PADCTL_CONN_CFG2TMC_DAP2_DIN_0

Offset: 0x4

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_DAP2_DIN_0

Reset: 0x00000000 (0bxxxx,xxx0,0000,xxx0,0000,xxxx,xxxx,xxxx)

Bit Reset Description

24:20 0x0 CFG_CAL_DRVUP

16:12 0x0 CFG_CAL_DRVDN

PADCTL_CONN_DAP2_DOUT_0

Offset: 0x8

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_DAP2_DOUT_0

Reset: 0x00000414 (0bxxxx,xxxx,xxxx,xxxx,xxx0,x1x0,x0x1,0100)

Bit Reset Description

12 DISABLE E_SCHMT:

= DISABLE0

= ENABLE1

10 SFIO GPIO_SF_SEL:

= GPIO0

= SFIO1

DISABLE

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Bit Reset Description

E_LPDR:

= DISABLE0

= ENABLE1

6 DISABLE E_INPUT:

= DISABLE0

= ENABLE1

4 TRISTATE TRISTATE:

= PASSTHROUGH0

= TRISTATE1

3:2 PULL_DOWN PUPD:

= NONE0

= PULL_DOWN1

= PULL_UP2

= RSVD3

1:0 I2S2

PM:

= I2S20

= RSVD11

= RSVD22

= RSVD33

PADCTL_CONN_CFG2TMC_DAP2_DOUT_0

Offset: 0xc

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_DAP2_DOUT_0

Reset: 0x00000000 (0bxxxx,xxx0,0000,xxx0,0000,xxxx,xxxx,xxxx)

Bit Reset Description

24:20 0x0 CFG_CAL_DRVUP

16:12 0x0 CFG_CAL_DRVDN

PADCTL_CONN_DAP2_FS_0

Offset: 0x10

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_DAP2_FS_0

Reset: 0x00000454 (0bxxxx,xxxx,xxxx,xxxx,xxx0,x1x0,x1x1,0100)

Bit Reset Description

DISABLE

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Bit Reset Description

E_SCHMT:

= DISABLE0

= ENABLE1

10 SFIO

GPIO_SF_SEL:

= GPIO0

= SFIO1

8 DISABLE

E_LPDR:

= DISABLE0

= ENABLE1

6 ENABLE

E_INPUT:

= DISABLE0

= ENABLE1

4 TRISTATE TRISTATE:

= PASSTHROUGH0

= TRISTATE1

3:2 PULL_DOWN PUPD:

= NONE0

= PULL_DOWN1

= PULL_UP2

= RSVD3

1:0 I2S2

PM:

= I2S20

= RSVD11

= RSVD22

= RSVD33

PADCTL_CONN_CFG2TMC_DAP2_FS_0

Offset: 0x14

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_DAP2_FS_0

Reset: 0x00000000 (0bxxxx,xxx0,0000,xxx0,0000,xxxx,xxxx,xxxx)

Bit Reset Description

24:20 0x0 CFG_CAL_DRVUP

16:12 0x0

CFG_CAL_DRVDN

PADCTL_CONN_DAP2_SCLK_0

Offset: 0x18

Read/Write: RW

Parity Protection: N

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SCR Protection: SCR_DAP2_SCLK_0

Reset: 0x00000454 (0bxxxx,xxxx,xxxx,xxxx,xxx0,x1x0,x1x1,0100)

Bit Reset Description

12 DISABLE

E_SCHMT:

= DISABLE0

= ENABLE1

10 SFIO

GPIO_SF_SEL:

= GPIO0

= SFIO1

8 DISABLE

E_LPDR:

= DISABLE0

= ENABLE1

6 ENABLE E_INPUT:

= DISABLE0

= ENABLE1

4 TRISTATE TRISTATE:

= PASSTHROUGH0

= TRISTATE1

3:2 PULL_DOWN PUPD:

= NONE0

= PULL_DOWN1

= PULL_UP2

= RSVD3

1:0 I2S2

PM:

= I2S20

= RSVD11

= RSVD22

= RSVD33

PADCTL_CONN_CFG2TMC_DAP2_SCLK_0

Offset: 0x1c

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_DAP2_SCLK_0

Reset: 0x00000000 (0bxxxx,xxx0,0000,xxx0,0000,xxxx,xxxx,xxxx)

Bit Reset Description

24:20 0x0 CFG_CAL_DRVUP

16:12 0x0

CFG_CAL_DRVDN

PADCTL_CONN_UART4_CTS_0

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Offset: 0x20

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_UART4_CTS_0

Reset: 0x00000458 (0bxxxx,xxxx,xxxx,xxxx,xxx0,x1x0,x1x1,1000)

Bit Reset Description

12 DISABLE E_SCHMT:

= DISABLE0

= ENABLE1

10 SFIO

GPIO_SF_SEL:

= GPIO0

= SFIO1

8 DISABLE

E_LPDR:

= DISABLE0

= ENABLE1

6 ENABLE E_INPUT:

= DISABLE0

= ENABLE1

4 TRISTATE TRISTATE:

= PASSTHROUGH0

= TRISTATE1

3:2 PULL_UP PUPD:

= NONE0

= PULL_DOWN1

= PULL_UP2

= RSVD3

1:0 UARTD PM:

= UARTD0

= RSVD11

= RSVD22

= RSVD33

PADCTL_CONN_CFG2TMC_UART4_CTS_0

Offset: 0x24

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_UART4_CTS_0

Reset: 0x00000000 (0bxxxx,xxx0,0000,xxx0,0000,xxxx,xxxx,xxxx)

Bit Reset Description

24:20 0x0

CFG_CAL_DRVUP

16:12 0x0

CFG_CAL_DRVDN

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PADCTL_CONN_UART4_RTS_0

Offset: 0x28

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_UART4_RTS_0

Reset: 0x00000414 (0bxxxx,xxxx,xxxx,xxxx,xxx0,x1x0,x0x1,0100)

Bit Reset Description

12 DISABLE

E_SCHMT:

= DISABLE0

= ENABLE1

10 SFIO

GPIO_SF_SEL:

= GPIO0

= SFIO1

8 DISABLE

E_LPDR:

= DISABLE0

= ENABLE1

6 DISABLE E_INPUT:

= DISABLE0

= ENABLE1

4 TRISTATE TRISTATE:

= PASSTHROUGH0

= TRISTATE1

3:2 PULL_DOWN PUPD:

= NONE0

= PULL_DOWN1

= PULL_UP2

= RSVD3

1:0 UARTD

PM:

= UARTD0

= RSVD11

= RSVD22

= RSVD33

PADCTL_CONN_CFG2TMC_UART4_RTS_0

Offset: 0x2c

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_UART4_RTS_0

Reset: 0x00000000 (0bxxxx,xxx0,0000,xxx0,0000,xxxx,xxxx,xxxx)

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Bit Reset Description

24:20 0x0

CFG_CAL_DRVUP

16:12 0x0 CFG_CAL_DRVDN

PADCTL_CONN_UART4_RX_0

Offset: 0x30

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_UART4_RX_0

Reset: 0x00000454 (0bxxxx,xxxx,xxxx,xxxx,xxx0,x1x0,x1x1,0100)

Bit Reset Description

12 DISABLE

E_SCHMT:

= DISABLE0

= ENABLE1

10 SFIO

GPIO_SF_SEL:

= GPIO0

= SFIO1

8 DISABLE

E_LPDR:

= DISABLE0

= ENABLE1

6 ENABLE E_INPUT:

= DISABLE0

= ENABLE1

4 TRISTATE TRISTATE:

= PASSTHROUGH0

= TRISTATE1

3:2 PULL_DOWN PUPD:

= NONE0

= PULL_DOWN1

= PULL_UP2

= RSVD3

1:0 UARTD

PM:

= UARTD0

= RSVD11

= RSVD22

= RSVD33

PADCTL_CONN_CFG2TMC_UART4_RX_0

Offset: 0x34

Read/Write: RW

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Parity Protection: N

SCR Protection: SCR_UART4_RX_0

Reset: 0x00000000 (0bxxxx,xxx0,0000,xxx0,0000,xxxx,xxxx,xxxx)

Bit Reset Description

24:20 0x0

CFG_CAL_DRVUP

16:12 0x0

CFG_CAL_DRVDN

PADCTL_CONN_UART4_TX_0

Offset: 0x38

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_UART4_TX_0

Reset: 0x00000414 (0bxxxx,xxxx,xxxx,xxxx,xxx0,x1x0,x0x1,0100)

Bit Reset Description

12 DISABLE E_SCHMT:

= DISABLE0

= ENABLE1

10 SFIO

GPIO_SF_SEL:

= GPIO0

= SFIO1

8 DISABLE

E_LPDR:

= DISABLE0

= ENABLE1

6 DISABLE E_INPUT:

= DISABLE0

= ENABLE1

4 TRISTATE TRISTATE:

= PASSTHROUGH0

= TRISTATE1

3:2 PULL_DOWN PUPD:

= NONE0

= PULL_DOWN1

= PULL_UP2

= RSVD3

1:0 UARTD PM:

= UARTD0

= RSVD11

= RSVD22

= RSVD33

PADCTL_CONN_CFG2TMC_UART4_TX_0

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Offset: 0x3c

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_UART4_TX_0

Reset: 0x00000000 (0bxxxx,xxx0,0000,xxx0,0000,xxxx,xxxx,xxxx)

Bit Reset Description

24:20 0x0

CFG_CAL_DRVUP

16:12 0x0

CFG_CAL_DRVDN

PADCTL_CONN_SOC_GPIO03_0

Offset: 0x40

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_SOC_GPIO03_0

Reset: 0x00000458 (0bxxxx,xxxx,xxxx,xxxx,xxx0,x1x0,x1x1,1000)

Bit Reset Description

12 DISABLE

E_SCHMT:

= DISABLE0

= ENABLE1

10 SFIO

GPIO_SF_SEL:

= GPIO0

= SFIO1

8 DISABLE

E_LPDR:

= DISABLE0

= ENABLE1

6 ENABLE E_INPUT:

= DISABLE0

= ENABLE1

4 TRISTATE TRISTATE:

= PASSTHROUGH0

= TRISTATE1

3:2 PULL_UP PUPD:

= NONE0

= PULL_DOWN1

= PULL_UP2

= RSVD3

1:0

RSVD0

PM:

= RSVD00

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Bit Reset Description

= RSVD11

= RSVD22

= RSVD33

PADCTL_CONN_CFG2TMC_SOC_GPIO03_0

Offset: 0x44

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_SOC_GPIO03_0

Reset: 0x00000000 (0bxxxx,xxx0,0000,xxx0,0000,xxxx,xxxx,xxxx)

Bit Reset Description

24:20 0x0 CFG_CAL_DRVUP

16:12 0x0 CFG_CAL_DRVDN

PADCTL_CONN_SOC_GPIO02_0

Offset: 0x48

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_SOC_GPIO02_0

Reset: 0x00000454 (0bxxxx,xxxx,xxxx,xxxx,xxx0,x1x0,x1x1,0100)

Bit Reset Description

12 DISABLE

E_SCHMT:

= DISABLE0

= ENABLE1

10 SFIO GPIO_SF_SEL:

= GPIO0

= SFIO1

8 DISABLE E_LPDR:

= DISABLE0

= ENABLE1

6 ENABLE E_INPUT:

= DISABLE0

= ENABLE1

4 TRISTATE TRISTATE:

= PASSTHROUGH0

= TRISTATE1

3:2

PULL_DOWN

PUPD:

= NONE0

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Bit Reset Description

= PULL_DOWN1

= PULL_UP2

= RSVD3

1:0 RSVD0

PM:

= RSVD00

= RSVD11

= RSVD22

= RSVD33

PADCTL_CONN_CFG2TMC_SOC_GPIO02_0

Offset: 0x4c

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_SOC_GPIO02_0

Reset: 0x00000000 (0bxxxx,xxx0,0000,xxx0,0000,xxxx,xxxx,xxxx)

Bit Reset Description

24:20 0x0 CFG_CAL_DRVUP

16:12 0x0

CFG_CAL_DRVDN

PADCTL_CONN_SOC_GPIO01_0

Offset: 0x50

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_SOC_GPIO01_0

Reset: 0x00000458 (0bxxxx,xxxx,xxxx,xxxx,xxx0,x1x0,x1x1,1000)

Bit Reset Description

12 DISABLE

E_SCHMT:

= DISABLE0

= ENABLE1

10 SFIO GPIO_SF_SEL:

= GPIO0

= SFIO1

8 DISABLE E_LPDR:

= DISABLE0

= ENABLE1

6 ENABLE E_INPUT:

= DISABLE0

= ENABLE1

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Bit Reset Description

4 TRISTATE TRISTATE:

= PASSTHROUGH0

= TRISTATE1

3:2 PULL_UP PUPD:

= NONE0

= PULL_DOWN1

= PULL_UP2

= RSVD3

1:0 RSVD0 PM:

= RSVD00

= RSVD11

= RSVD22

= RSVD33

PADCTL_CONN_CFG2TMC_SOC_GPIO01_0

Offset: 0x54

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_SOC_GPIO01_0

Reset: 0x00000000 (0bxxxx,xxx0,0000,xxx0,0000,xxxx,xxxx,xxxx)

Bit Reset Description

24:20 0x0

CFG_CAL_DRVUP

16:12 0x0

CFG_CAL_DRVDN

PADCTL_CONN_SOC_GPIO00_0

Offset: 0x58

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_SOC_GPIO00_0

Reset: 0x00000458 (0bxxxx,xxxx,xxxx,xxxx,xxx0,x1x0,x1x1,1000)

Bit Reset Description

12 DISABLE

E_SCHMT:

= DISABLE0

= ENABLE1

10 SFIO

GPIO_SF_SEL:

= GPIO0

= SFIO1

DISABLE

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Bit Reset Description

E_LPDR:

= DISABLE0

= ENABLE1

6 ENABLE

E_INPUT:

= DISABLE0

= ENABLE1

4 TRISTATE

TRISTATE:

= PASSTHROUGH0

= TRISTATE1

3:2 PULL_UP PUPD:

= NONE0

= PULL_DOWN1

= PULL_UP2

= RSVD3

1:0 RSVD0 PM:

= RSVD00

= RSVD11

= RSVD22

= RSVD33

PADCTL_CONN_CFG2TMC_SOC_GPIO00_0

Offset: 0x5c

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_SOC_GPIO00_0

Reset: 0x00000000 (0bxxxx,xxx0,0000,xxx0,0000,xxxx,xxxx,xxxx)

Bit Reset Description

24:20 0x0

CFG_CAL_DRVUP

16:12 0x0 CFG_CAL_DRVDN

PADCTL_CONN_GEN1_I2C_SCL_0

Offset: 0x60

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_GEN1_I2C_SCL_0

Reset: 0x00001570 (0bxxxx,xxxx,xxxx,xxxx,xxx1,x1x1,x111,0000)

Bit Reset Description

ENABLE

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Bit Reset Description

E_SCHMT:

= DISABLE0

= ENABLE1

10 SFIO GPIO_SF_SEL:

= GPIO0

= SFIO1

8 ENABLE E_LPDR:

= DISABLE0

= ENABLE1

6 ENABLE E_INPUT:

= DISABLE0

= ENABLE1

5 ENABLE E_IO_HV:

= DISABLE0

= ENABLE1

4 TRISTATE

TRISTATE:

= PASSTHROUGH0

= TRISTATE1

3:2 NONE

PUPD:

= NONE0

= PULL_DOWN1

= PULL_UP2

= RSVD3

1:0 I2C1 PM:

= I2C10

= RSVD11

= RSVD22

= RSVD33

PADCTL_CONN_CFG2TMC_GEN1_I2C_SCL_0

Offset: 0x64

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_GEN1_I2C_SCL_0

Reset: 0x00000000 (0bxxxx,xxx0,0000,xxx0,0000,xxxx,xxxx,xxxx)

Bit Reset Description

24:20 0x0

CFG_CAL_DRVUP

16:12 0x0 CFG_CAL_DRVDN

PADCTL_CONN_GEN1_I2C_SDA_0

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Offset: 0x68

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_GEN1_I2C_SDA_0

Reset: 0x00001570 (0bxxxx,xxxx,xxxx,xxxx,xxx1,x1x1,x111,0000)

Bit Reset Description

12 ENABLE

E_SCHMT:

= DISABLE0

= ENABLE1

10 SFIO

GPIO_SF_SEL:

= GPIO0

= SFIO1

8 ENABLE

E_LPDR:

= DISABLE0

= ENABLE1

6 ENABLE

E_INPUT:

= DISABLE0

= ENABLE1

5 ENABLE E_IO_HV:

= DISABLE0

= ENABLE1

4 TRISTATE TRISTATE:

= PASSTHROUGH0

= TRISTATE1

3:2 NONE PUPD:

= NONE0

= PULL_DOWN1

= PULL_UP2

= RSVD3

1:0 I2C1

PM:

= I2C10

= RSVD11

= RSVD22

= RSVD33

PADCTL_CONN_CFG2TMC_GEN1_I2C_SDA_0

Offset: 0x6c

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_GEN1_I2C_SDA_0

Reset: 0x00000000 (0bxxxx,xxx0,0000,xxx0,0000,xxxx,xxxx,xxxx)

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Bit Reset Description

24:20 0x0 CFG_CAL_DRVUP

16:12 0x0

CFG_CAL_DRVDN

PADCTL_CONN_SOC_GPIO08_0

Offset: 0x70

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_SOC_GPIO08_0

Reset: 0x00000454 (0bxxxx,xxxx,xxxx,xxxx,xxx0,x1x0,x1x1,0100)

Bit Reset Description

12 DISABLE E_SCHMT:

= DISABLE0

= ENABLE1

10 SFIO GPIO_SF_SEL:

= GPIO0

= SFIO1

8 DISABLE E_LPDR:

= DISABLE0

= ENABLE1

6 ENABLE

E_INPUT:

= DISABLE0

= ENABLE1

4 TRISTATE

TRISTATE:

= PASSTHROUGH0

= TRISTATE1

3:2 PULL_DOWN

PUPD:

= NONE0

= PULL_DOWN1

= PULL_UP2

= RSVD3

1:0 RSVD0 PM:

= RSVD00

= CCLA1

= RSVD22

= RSVD33

PADCTL_CONN_CFG2TMC_SOC_GPIO08_0

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Offset: 0x74

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_SOC_GPIO08_0

Reset: 0x00000000 (0bxxxx,xxx0,0000,xxx0,0000,xxxx,xxxx,xxxx)

Bit Reset Description

24:20 0x0 CFG_CAL_DRVUP

16:12 0x0 CFG_CAL_DRVDN

PADCTL_CONN_SOC_GPIO09_0

Offset: 0x78

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_SOC_GPIO09_0

Reset: 0x00000454 (0bxxxx,xxxx,xxxx,xxxx,xxx0,x1x0,x1x1,0100)

Bit Reset Description

12 DISABLE E_SCHMT:

= DISABLE0

= ENABLE1

10 SFIO GPIO_SF_SEL:

= GPIO0

= SFIO1

8 DISABLE E_LPDR:

= DISABLE0

= ENABLE1

6 ENABLE

E_INPUT:

= DISABLE0

= ENABLE1

4 TRISTATE

TRISTATE:

= PASSTHROUGH0

= TRISTATE1

3:2 PULL_DOWN PUPD:

= NONE0

= PULL_DOWN1

= PULL_UP2

= RSVD3

1:0 RSVD0 PM:

= RSVD00

= RSVD11

= RSVD22

= RSVD33

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PADCTL_CONN_CFG2TMC_SOC_GPIO09_0

Offset: 0x7c

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_SOC_GPIO09_0

Reset: 0x00000000 (0bxxxx,xxx0,0000,xxx0,0000,xxxx,xxxx,xxxx)

Bit Reset Description

24:20 0x0

CFG_CAL_DRVUP

16:12 0x0 CFG_CAL_DRVDN

PADCTL_CONN_SOC_GPIO10_0

Offset: 0x80

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_SOC_GPIO10_0

Reset: 0x00000410 (0bxxxx,xxxx,xxxx,xxxx,xxx0,x1x0,x0x1,0000)

Bit Reset Description

12 DISABLE E_SCHMT:

= DISABLE0

= ENABLE1

10 SFIO

GPIO_SF_SEL:

= GPIO0

= SFIO1

8 DISABLE

E_LPDR:

= DISABLE0

= ENABLE1

6 DISABLE

E_INPUT:

= DISABLE0

= ENABLE1

4 TRISTATE

TRISTATE:

= PASSTHROUGH0

= TRISTATE1

3:2 NONE PUPD:

= NONE0

= PULL_DOWN1

= PULL_UP2

= RSVD3

1:0

PM:

= GP0

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Bit Reset Description

= RSVD11

= RSVD22

= RSVD33

PADCTL_CONN_CFG2TMC_SOC_GPIO10_0

Offset: 0x84

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_SOC_GPIO10_0

Reset: 0x00000000 (0bxxxx,xxx0,0000,xxx0,0000,xxxx,xxxx,xxxx)

Bit Reset Description

24:20 0x0

CFG_CAL_DRVUP

16:12 0x0 CFG_CAL_DRVDN

PADCTL_CONN_SOC_GPIO11_0

Offset: 0x88

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_SOC_GPIO11_0

Reset: 0x00000454 (0bxxxx,xxxx,xxxx,xxxx,xxx0,x1x0,x1x1,0100)

Bit Reset Description

12 DISABLE E_SCHMT:

= DISABLE0

= ENABLE1

10 SFIO

GPIO_SF_SEL:

= GPIO0

= SFIO1

8 DISABLE

E_LPDR:

= DISABLE0

= ENABLE1

6 ENABLE

E_INPUT:

= DISABLE0

= ENABLE1

4 TRISTATE

TRISTATE:

= PASSTHROUGH0

= TRISTATE1

3:2

PULL_DOWN

PUPD:

= NONE0

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Bit Reset Description

= PULL_DOWN1

= PULL_UP2

= RSVD3

1:0 RSVD0 PM:

= RSVD00

= SDMMC11

= RSVD22

= RSVD33

PADCTL_CONN_CFG2TMC_SOC_GPIO11_0

Offset: 0x8c

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_SOC_GPIO11_0

Reset: 0x00000000 (0bxxxx,xxx0,0000,xxx0,0000,xxxx,xxxx,xxxx)

Bit Reset Description

24:20 0x0 CFG_CAL_DRVUP

16:12 0x0 CFG_CAL_DRVDN

PADCTL_CONN_SOC_GPIO12_0

Offset: 0x90

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_SOC_GPIO12_0

Reset: 0x00000410 (0bxxxx,xxxx,xxxx,xxxx,xxx0,x1x0,x0x1,0000)

Bit Reset Description

12 DISABLE E_SCHMT:

= DISABLE0

= ENABLE1

10 SFIO GPIO_SF_SEL:

= GPIO0

= SFIO1

8 DISABLE E_LPDR:

= DISABLE0

= ENABLE1

6 DISABLE

E_INPUT:

= DISABLE0

= ENABLE1

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Bit Reset Description

4 TRISTATE TRISTATE:

= PASSTHROUGH0

= TRISTATE1

3:2 NONE

PUPD:

= NONE0

= PULL_DOWN1

= PULL_UP2

= RSVD3

1:0 RSVD0 PM:

= RSVD00

= GP1

= RSVD22

= RSVD33

PADCTL_CONN_CFG2TMC_SOC_GPIO12_0

Offset: 0x94

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_SOC_GPIO12_0

Reset: 0x00000000 (0bxxxx,xxx0,0000,xxx0,0000,xxxx,xxxx,xxxx)

Bit Reset Description

24:20 0x0 CFG_CAL_DRVUP

16:12 0x0 CFG_CAL_DRVDN

PADCTL_CONN_SOC_GPIO13_0

Offset: 0x98

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_SOC_GPIO13_0

Reset: 0x00000410 (0bxxxx,xxxx,xxxx,xxxx,xxx0,x1x0,x0x1,0000)

Bit Reset Description

12 DISABLE E_SCHMT:

= DISABLE0

= ENABLE1

10 SFIO GPIO_SF_SEL:

= GPIO0

= SFIO1

DISABLE

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Bit Reset Description

E_LPDR:

= DISABLE0

= ENABLE1

6 DISABLE E_INPUT:

= DISABLE0

= ENABLE1

4 TRISTATE TRISTATE:

= PASSTHROUGH0

= TRISTATE1

3:2 NONE PUPD:

= NONE0

= PULL_DOWN1

= PULL_UP2

= RSVD3

1:0 RSVD0

PM:

= RSVD00

= GP1

= RSVD22

= RSVD33

PADCTL_CONN_CFG2TMC_SOC_GPIO13_0

Offset: 0x9c

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_SOC_GPIO13_0

Reset: 0x00000000 (0bxxxx,xxx0,0000,xxx0,0000,xxxx,xxxx,xxxx)

Bit Reset Description

24:20 0x0 CFG_CAL_DRVUP

16:12 0x0 CFG_CAL_DRVDN

PADCTL_CONN_SOC_GPIO14_0

Offset: 0xa0

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_SOC_GPIO14_0

Reset: 0x00000454 (0bxxxx,xxxx,xxxx,xxxx,xxx0,x1x0,x1x1,0100)

Bit Reset Description

DISABLE

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Bit Reset Description

E_SCHMT:

= DISABLE0

= ENABLE1

10 SFIO

GPIO_SF_SEL:

= GPIO0

= SFIO1

8 DISABLE

E_LPDR:

= DISABLE0

= ENABLE1

6 ENABLE

E_INPUT:

= DISABLE0

= ENABLE1

4 TRISTATE TRISTATE:

= PASSTHROUGH0

= TRISTATE1

3:2 PULL_DOWN PUPD:

= NONE0

= PULL_DOWN1

= PULL_UP2

= RSVD3

1:0 RSVD0

PM:

= RSVD00

= RSVD11

= RSVD22

= RSVD33

PADCTL_CONN_CFG2TMC_SOC_GPIO14_0

Offset: 0xa4

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_SOC_GPIO14_0

Reset: 0x00000000 (0bxxxx,xxx0,0000,xxx0,0000,xxxx,xxxx,xxxx)

Bit Reset Description

24:20 0x0 CFG_CAL_DRVUP

16:12 0x0

CFG_CAL_DRVDN

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Debug PAD Control Registers

PADCTL_DEBUG_DIRECTDC1_OUT7_0

Offset: 0x8

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_DIRECTDC1_OUT7_0

Reset: 0x00022414 (0bxxxx,xxxx,0000,xx1x,0010,x10x,x0x1,0100)

Bit Reset Description

23:20 0x0 RFU_IN

17 IORESET IO_RESET:

= NORMAL0

= IORESET1

15 DISABLE E_PREEMP:

= DISABLE0

= ENABLE1

14:13 COMP_DRIVE_2X DRV_TYPE:

DRV_TYPE[0]:

0 = 1X driver;

1 = 2X driver;

DRV_TYPE[1]:

0 = Driving codes from BDSDMEMCOMP;

1 = Default driving codes;

= COMP_DRIVE_1X0

= COMP_DRIVE_2X1

= DEFAULT_DRIVE_1X2

= DEFAULT_DRIVE_2X3

12 DISABLE E_SCHMT:

= DISABLE0

= ENABLE1

10 SFIO

GPIO_SF_SEL:

= GPIO0

= SFIO1

9 DISABLE

E_HSM:

= DISABLE0

= ENABLE1

6 DISABLE

E_INPUT:

= DISABLE0

= ENABLE1

TRISTATE

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Bit Reset Description

TRISTATE:

= PASSTHROUGH0

= TRISTATE1

3:2 PULL_DOWN

PUPD:

= NONE0

= PULL_DOWN1

= PULL_UP2

= RSVD3

1:0 DIRECTDC1 PM:

= DIRECTDC10

= RSVD11

= RSVD22

= RSVD33

PADCTL_DEBUG_DIRECTDC1_OUT6_0

Offset: 0x10

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_DIRECTDC1_OUT6_0

Reset: 0x00022414 (0bxxxx,xxxx,0000,xx1x,0010,x10x,x0x1,0100)

Bit Reset Description

23:20 0x0 RFU_IN

17 IORESET

IO_RESET:

= NORMAL0

= IORESET1

15 DISABLE E_PREEMP:

= DISABLE0

= ENABLE1

14:13 COMP_DRIVE_2X DRV_TYPE:

DRV_TYPE[0]:

0 = 1X driver;

1 = 2X driver;

DRV_TYPE[1]:

0 = Driving codes from BDSDMEMCOMP;

1 = Default driving codes;

= COMP_DRIVE_1X0

= COMP_DRIVE_2X1

= DEFAULT_DRIVE_1X2

= DEFAULT_DRIVE_2X3

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Bit Reset Description

12 DISABLE E_SCHMT:

= DISABLE0

= ENABLE1

10 SFIO GPIO_SF_SEL:

= GPIO0

= SFIO1

9 DISABLE E_HSM:

= DISABLE0

= ENABLE1

6 DISABLE E_INPUT:

= DISABLE0

= ENABLE1

4 TRISTATE TRISTATE:

= PASSTHROUGH0

= TRISTATE1

3:2 PULL_DOWN

PUPD:

= NONE0

= PULL_DOWN1

= PULL_UP2

= RSVD3

1:0 DIRECTDC1 PM:

= DIRECTDC10

= RSVD11

= RSVD22

= RSVD33

PADCTL_DEBUG_DIRECTDC1_OUT5_0

Offset: 0x18

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_DIRECTDC1_OUT5_0

Reset: 0x00022414 (0bxxxx,xxxx,0000,xx1x,0010,x10x,x0x1,0100)

Bit Reset Description

23:20 0x0 RFU_IN

17 IORESET

IO_RESET:

= NORMAL0

= IORESET1

DISABLE

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Bit Reset Description

E_PREEMP:

= DISABLE0

= ENABLE1

14:13 COMP_DRIVE_2X

DRV_TYPE:

DRV_TYPE[0]:

0 = 1X driver;

1 = 2X driver;

DRV_TYPE[1]:

0 = Driving codes from BDSDMEMCOMP;

1 = Default driving codes;

= COMP_DRIVE_1X0

= COMP_DRIVE_2X1

= DEFAULT_DRIVE_1X2

= DEFAULT_DRIVE_2X3

12 DISABLE

E_SCHMT:

= DISABLE0

= ENABLE1

10 SFIO

GPIO_SF_SEL:

= GPIO0

= SFIO1

9 DISABLE E_HSM:

= DISABLE0

= ENABLE1

6 DISABLE E_INPUT:

= DISABLE0

= ENABLE1

4 TRISTATE TRISTATE:

= PASSTHROUGH0

= TRISTATE1

3:2 PULL_DOWN PUPD:

= NONE0

= PULL_DOWN1

= PULL_UP2

= RSVD3

1:0 DIRECTDC1

PM:

= DIRECTDC10

= RSVD11

= RSVD22

= RSVD33

PADCTL_DEBUG_DIRECTDC1_OUT4_0

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Offset: 0x20

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_DIRECTDC1_OUT4_0

Reset: 0x00022414 (0bxxxx,xxxx,0000,xx1x,0010,x10x,x0x1,0100)

Bit Reset Description

23:20 0x0 RFU_IN

17 IORESET

IO_RESET:

= NORMAL0

= IORESET1

15 DISABLE E_PREEMP:

= DISABLE0

= ENABLE1

14:13 COMP_DRIVE_2X DRV_TYPE:

DRV_TYPE[0]:

0 = 1X driver;

1 = 2X driver;

DRV_TYPE[1]:

0 = Driving codes from BDSDMEMCOMP;

1 = Default driving codes;

= COMP_DRIVE_1X0

= COMP_DRIVE_2X1

= DEFAULT_DRIVE_1X2

= DEFAULT_DRIVE_2X3

12 DISABLE E_SCHMT:

= DISABLE0

= ENABLE1

10 SFIO GPIO_SF_SEL:

= GPIO0

= SFIO1

9 DISABLE E_HSM:

= DISABLE0

= ENABLE1

6 DISABLE

E_INPUT:

= DISABLE0

= ENABLE1

4 TRISTATE

TRISTATE:

= PASSTHROUGH0

= TRISTATE1

3:2

PULL_DOWN

PUPD:

= NONE0

= PULL_DOWN1

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Bit Reset Description

= PULL_UP2

= RSVD3

1:0 DIRECTDC1 PM:

= DIRECTDC10

= RSVD11

= RSVD22

= RSVD33

PADCTL_DEBUG_DIRECTDC1_OUT3_0

Offset: 0x28

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_DIRECTDC1_OUT3_0

Reset: 0x00022414 (0bxxxx,xxxx,0000,xx1x,0010,x10x,x0x1,0100)

Bit Reset Description

23:20 0x0 RFU_IN

17 IORESET

IO_RESET:

= NORMAL0

= IORESET1

15 DISABLE E_PREEMP:

= DISABLE0

= ENABLE1

14:13 COMP_DRIVE_2X DRV_TYPE:

DRV_TYPE[0]:

0 = 1X driver;

1 = 2X driver;

DRV_TYPE[1]:

0 = Driving codes from BDSDMEMCOMP;

1 = Default driving codes;

= COMP_DRIVE_1X0

= COMP_DRIVE_2X1

= DEFAULT_DRIVE_1X2

= DEFAULT_DRIVE_2X3

12 DISABLE E_SCHMT:

= DISABLE0

= ENABLE1

10 SFIO GPIO_SF_SEL:

= GPIO0

= SFIO1

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Bit Reset Description

9 DISABLE E_HSM:

= DISABLE0

= ENABLE1

6 DISABLE E_INPUT:

= DISABLE0

= ENABLE1

4 TRISTATE TRISTATE:

= PASSTHROUGH0

= TRISTATE1

3:2 PULL_DOWN PUPD:

= NONE0

= PULL_DOWN1

= PULL_UP2

= RSVD3

1:0 DIRECTDC1

PM:

= DIRECTDC10

= RSVD11

= RSVD22

= RSVD33

PADCTL_DEBUG_DIRECTDC1_OUT2_0

Offset: 0x30

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_DIRECTDC1_OUT2_0

Reset: 0x00022414 (0bxxxx,xxxx,0000,xx1x,0010,x10x,x0x1,0100)

Bit Reset Description

23:20 0x0

RFU_IN

17 IORESET

IO_RESET:

= NORMAL0

= IORESET1

15 DISABLE

E_PREEMP:

= DISABLE0

= ENABLE1

14:13

COMP_DRIVE_2X

DRV_TYPE:

DRV_TYPE[0]:

0 = 1X driver;

1 = 2X driver;

DRV_TYPE[1]:

0 = Driving codes from BDSDMEMCOMP;

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Bit Reset Description

1 = Default driving codes;

= COMP_DRIVE_1X0

= COMP_DRIVE_2X1

= DEFAULT_DRIVE_1X2

= DEFAULT_DRIVE_2X3

12 DISABLE

E_SCHMT:

= DISABLE0

= ENABLE1

10 SFIO GPIO_SF_SEL:

= GPIO0

= SFIO1

9 DISABLE E_HSM:

= DISABLE0

= ENABLE1

6 DISABLE E_INPUT:

= DISABLE0

= ENABLE1

4 TRISTATE TRISTATE:

= PASSTHROUGH0

= TRISTATE1

3:2 PULL_DOWN PUPD:

= NONE0

= PULL_DOWN1

= PULL_UP2

= RSVD3

1:0 DIRECTDC1

PM:

= DIRECTDC10

= RSVD11

= RSVD22

= RSVD33

PADCTL_DEBUG_DIRECTDC1_OUT1_0

Offset: 0x38

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_DIRECTDC1_OUT1_0

Reset: 0x00022414 (0bxxxx,xxxx,0000,xx1x,0010,x10x,x0x1,0100)

Bit Reset Description

23:20 0x0

RFU_IN

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Bit Reset Description

17 IORESET IO_RESET:

= NORMAL0

= IORESET1

15 DISABLE E_PREEMP:

= DISABLE0

= ENABLE1

14:13 COMP_DRIVE_2X DRV_TYPE:

DRV_TYPE[0]:

0 = 1X driver;

1 = 2X driver;

DRV_TYPE[1]:

0 = Driving codes from BDSDMEMCOMP;

1 = Default driving codes;

= COMP_DRIVE_1X0

= COMP_DRIVE_2X1

= DEFAULT_DRIVE_1X2

= DEFAULT_DRIVE_2X3

12 DISABLE E_SCHMT:

= DISABLE0

= ENABLE1

10 SFIO

GPIO_SF_SEL:

= GPIO0

= SFIO1

9 DISABLE

E_HSM:

= DISABLE0

= ENABLE1

6 DISABLE

E_INPUT:

= DISABLE0

= ENABLE1

4 TRISTATE

TRISTATE:

= PASSTHROUGH0

= TRISTATE1

3:2 PULL_DOWN PUPD:

= NONE0

= PULL_DOWN1

= PULL_UP2

= RSVD3

1:0 DIRECTDC1 PM:

= DIRECTDC10

= RSVD11

= RSVD22

= RSVD33

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PADCTL_DEBUG_DIRECTDC1_OUT0_0

Offset: 0x40

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_DIRECTDC1_OUT0_0

Reset: 0x00022414 (0bxxxx,xxxx,0000,xx1x,0010,x10x,x0x1,0100)

Bit Reset Description

23:20 0x0 RFU_IN

17 IORESET

IO_RESET:

= NORMAL0

= IORESET1

15 DISABLE E_PREEMP:

= DISABLE0

= ENABLE1

14:13 COMP_DRIVE_2X DRV_TYPE:

DRV_TYPE[0]:

0 = 1X driver;

1 = 2X driver;

DRV_TYPE[1]:

0 = Driving codes from BDSDMEMCOMP;

1 = Default driving codes;

= COMP_DRIVE_1X0

= COMP_DRIVE_2X1

= DEFAULT_DRIVE_1X2

= DEFAULT_DRIVE_2X3

12 DISABLE E_SCHMT:

= DISABLE0

= ENABLE1

10 SFIO GPIO_SF_SEL:

= GPIO0

= SFIO1

9 DISABLE E_HSM:

= DISABLE0

= ENABLE1

6 DISABLE

E_INPUT:

= DISABLE0

= ENABLE1

4 TRISTATE

TRISTATE:

= PASSTHROUGH0

= TRISTATE1

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Bit Reset Description

3:2 PULL_DOWN PUPD:

= NONE0

= PULL_DOWN1

= PULL_UP2

= RSVD3

1:0 DIRECTDC1 PM:

= DIRECTDC10

= RSVD11

= RSVD22

= RSVD33

PADCTL_DEBUG_DIRECTDC1_IN_0

Offset: 0x48

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_DIRECTDC1_IN_0

Reset: 0x00022454 (0bxxxx,xxxx,0000,xx1x,0010,x10x,x1x1,0100)

Bit Reset Description

23:20 0x0 RFU_IN

17 IORESET IO_RESET:

= NORMAL0

= IORESET1

15 DISABLE E_PREEMP:

= DISABLE0

= ENABLE1

14:13 COMP_DRIVE_2X

DRV_TYPE:

DRV_TYPE[0]:

0 = 1X driver;

1 = 2X driver;

DRV_TYPE[1]:

0 = Driving codes from BDSDMEMCOMP;

1 = Default driving codes;

= COMP_DRIVE_1X0

= COMP_DRIVE_2X1

= DEFAULT_DRIVE_1X2

= DEFAULT_DRIVE_2X3

12 DISABLE

E_SCHMT:

= DISABLE0

= ENABLE1

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Bit Reset Description

10 SFIO

GPIO_SF_SEL:

= GPIO0

= SFIO1

9 DISABLE

E_HSM:

= DISABLE0

= ENABLE1

6 ENABLE

E_INPUT:

= DISABLE0

= ENABLE1

4 TRISTATE

TRISTATE:

= PASSTHROUGH0

= TRISTATE1

3:2 PULL_DOWN PUPD:

= NONE0

= PULL_DOWN1

= PULL_UP2

= RSVD3

1:0 DIRECTDC1 PM:

= DIRECTDC10

= RSVD11

= RSVD22

= RSVD33

PADCTL_DEBUG_DIRECTDC1_CLK_0

Offset: 0x50

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_DIRECTDC1_CLK_0

Reset: 0x00022414 (0bxxxx,xxxx,0000,xx1x,0010,x10x,x0x1,0100)

Bit Reset Description

23:20 0x0 RFU_IN

17 IORESET IO_RESET:

= NORMAL0

= IORESET1

15 DISABLE E_PREEMP:

= DISABLE0

= ENABLE1

14:13

COMP_DRIVE_2X

DRV_TYPE:

DRV_TYPE[0]:

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Bit Reset Description

0 = 1X driver;

1 = 2X driver;

DRV_TYPE[1]:

0 = Driving codes from BDSDMEMCOMP;

1 = Default driving codes;

= COMP_DRIVE_1X0

= COMP_DRIVE_2X1

= DEFAULT_DRIVE_1X2

= DEFAULT_DRIVE_2X3

12 DISABLE E_SCHMT:

= DISABLE0

= ENABLE1

10 SFIO GPIO_SF_SEL:

= GPIO0

= SFIO1

9 DISABLE

E_HSM:

= DISABLE0

= ENABLE1

6 DISABLE

E_INPUT:

= DISABLE0

= ENABLE1

4 TRISTATE

TRISTATE:

= PASSTHROUGH0

= TRISTATE1

3:2 PULL_DOWN

PUPD:

= NONE0

= PULL_DOWN1

= PULL_UP2

= RSVD3

1:0 DIRECTDC1 PM:

= DIRECTDC10

= RSVD11

= RSVD22

= RSVD33

PADCTL_DEBUG_DIRECTDC_COMP_0

Offset: 0x58

Read/Write: RW

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Parity Protection: N

SCR Protection: SCR_DIRECTDC_COMP_0

Reset: 0x00002000 (0bxxxx,xxxx,0000,xxxx,x01x,xxxx,xxx0,xx00)

Bit Reset Description

23:20 0x0 RFU_IN

14:13 COMP_DRIVE_2X DRV_TYPE:

DRV_TYPE[0]:

0 = 1X driver;

1 = 2X driver;

DRV_TYPE[1]:

0 = Driving codes from BDSDMEMCOMP;

1 = Default driving codes;

= COMP_DRIVE_1X0

= COMP_DRIVE_2X1

= DEFAULT_DRIVE_1X2

= DEFAULT_DRIVE_2X3

4 PASSTHROUGH TRISTATE:

= PASSTHROUGH0

= TRISTATE1

1:0 DIRECTDC PM:

= DIRECTDC0

= RSVD11

= RSVD22

= RSVD33

SDMMC4 PAD Control Registers

PADCTL_SDMMC4_EMMC4_PAD_0

Offset: 0x0

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_EMMC4_PAD_0

Reset: 0x00000000 (0bxxxx,xxxx,xxxx,xxxx,xxx0,xxxx,xx0x,xxxx)

Bit Reset Description

12 DISABLE

E_SCHMT:

= DISABLE0

= ENABLE1

DISABLE

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Bit Reset Description

E_PREEMP:

= DISABLE0

= ENABLE1

PADCTL_SDMMC4_EMMC4_PAD_CLK_0

Offset: 0x8

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_EMMC4_PAD_CLK_0

Reset: 0x00002060 (0bxxxx,xxxx,xxxx,xxxx,x01x,xxxx,x11x,00xx)

Bit Reset Description

14:13 COMP_DRIVE_2X

DRV_TYPE:

Unused DRV_TYPE registers Not used for EMMC4 pads

DRV_TYPE[0]:

0 = 1X driver;

1 = 2X driver;

DRV_TYPE[1]:

0 = Driving codes from BDSDMEMCOMP;

1 = Default driving codes;

= COMP_DRIVE_1X0

= COMP_DRIVE_2X1

= DEFAULT_DRIVE_1X2

= DEFAULT_DRIVE_2X3

6 ENABLE E_INPUT:

= DISABLE0

= ENABLE1

5 ENABLE E_DEEP_LPBK:

= DISABLE0

= ENABLE1

3:2 NONE PUPD:

= NONE0

= PULL_DOWN1

= PULL_UP2

= RSVD3

PADCTL_SDMMC4_EMMC4_PAD_CMD_0

Offset: 0x10

Read/Write: RW

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Parity Protection: N

SCR Protection: SCR_EMMC4_PAD_CMD_0

Reset: 0x00002048 (0bxxxx,xxxx,xxxx,xxxx,x01x,xxxx,x1xx,10xx)

Bit Reset Description

14:13 COMP_DRIVE_2X DRV_TYPE:

Unused DRV_TYPE registers Not used for EMMC4 pads

DRV_TYPE[0]:

0 = 1X driver;

1 = 2X driver;

DRV_TYPE[1]:

0 = Driving codes from BDSDMEMCOMP;

1 = Default driving codes;

= COMP_DRIVE_1X0

= COMP_DRIVE_2X1

= DEFAULT_DRIVE_1X2

= DEFAULT_DRIVE_2X3

6 ENABLE

E_INPUT:

= DISABLE0

= ENABLE1

3:2 PULL_UP

PUPD:

= NONE0

= PULL_DOWN1

= PULL_UP2

= RSVD3

PADCTL_SDMMC4_EMMC4_PAD_DQS_0

Offset: 0x18

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_EMMC4_PAD_DQS_0

Reset: 0x00000044 (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,x1xx,01xx)

Bit Reset Description

6 ENABLE

E_INPUT:

= DISABLE0

= ENABLE1

3:2 PULL_DOWN

PUPD:

= NONE0

= PULL_DOWN1

= PULL_UP2

= RSVD3

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PADCTL_SDMMC4_EMMC4_PAD_DAT7_0

Offset: 0x20

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_EMMC4_PAD_DAT7_0

Reset: 0x00002048 (0bxxxx,xxxx,xxxx,xxxx,x01x,xxxx,x1xx,10xx)

Bit Reset Description

14:13 COMP_DRIVE_2X DRV_TYPE:

Unused DRV_TYPE registers Not used for EMMC4 pads

DRV_TYPE[0]:

0 = 1X driver;

1 = 2X driver;

DRV_TYPE[1]:

0 = Driving codes from BDSDMEMCOMP;

1 = Default driving codes;

= COMP_DRIVE_1X0

= COMP_DRIVE_2X1

= DEFAULT_DRIVE_1X2

= DEFAULT_DRIVE_2X3

6 ENABLE E_INPUT:

= DISABLE0

= ENABLE1

3:2 PULL_UP PUPD:

= NONE0

= PULL_DOWN1

= PULL_UP2

= RSVD3

PADCTL_SDMMC4_EMMC4_PAD_DAT6_0

Offset: 0x28

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_EMMC4_PAD_DAT6_0

Reset: 0x00002048 (0bxxxx,xxxx,xxxx,xxxx,x01x,xxxx,x1xx,10xx)

Bit Reset Description

14:13

COMP_DRIVE_2X

DRV_TYPE:

Unused DRV_TYPE registers Not used for EMMC4 pads

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Bit Reset Description

DRV_TYPE[0]:

0 = 1X driver;

1 = 2X driver;

DRV_TYPE[1]:

0 = Driving codes from BDSDMEMCOMP;

1 = Default driving codes;

= COMP_DRIVE_1X0

= COMP_DRIVE_2X1

= DEFAULT_DRIVE_1X2

= DEFAULT_DRIVE_2X3

6 ENABLE E_INPUT:

= DISABLE0

= ENABLE1

3:2 PULL_UP PUPD:

= NONE0

= PULL_DOWN1

= PULL_UP2

= RSVD3

PADCTL_SDMMC4_EMMC4_PAD_DAT5_0

Offset: 0x30

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_EMMC4_PAD_DAT5_0

Reset: 0x00002048 (0bxxxx,xxxx,xxxx,xxxx,x01x,xxxx,x1xx,10xx)

Bit Reset Description

14:13 COMP_DRIVE_2X DRV_TYPE:

Unused DRV_TYPE registers Not used for EMMC4 pads

DRV_TYPE[0]:

0 = 1X driver;

1 = 2X driver;

DRV_TYPE[1]:

0 = Driving codes from BDSDMEMCOMP;

1 = Default driving codes;

= COMP_DRIVE_1X0

= COMP_DRIVE_2X1

= DEFAULT_DRIVE_1X2

= DEFAULT_DRIVE_2X3

ENABLE

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Bit Reset Description

E_INPUT:

= DISABLE0

= ENABLE1

3:2 PULL_UP PUPD:

= NONE0

= PULL_DOWN1

= PULL_UP2

= RSVD3

PADCTL_SDMMC4_EMMC4_PAD_DAT4_0

Offset: 0x38

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_EMMC4_PAD_DAT4_0

Reset: 0x00002048 (0bxxxx,xxxx,xxxx,xxxx,x01x,xxxx,x1xx,10xx)

Bit Reset Description

14:13 COMP_DRIVE_2X DRV_TYPE:

Unused DRV_TYPE registers Not used for EMMC4 pads

DRV_TYPE[0]:

0 = 1X driver;

1 = 2X driver;

DRV_TYPE[1]:

0 = Driving codes from BDSDMEMCOMP;

1 = Default driving codes;

= COMP_DRIVE_1X0

= COMP_DRIVE_2X1

= DEFAULT_DRIVE_1X2

= DEFAULT_DRIVE_2X3

6 ENABLE E_INPUT:

= DISABLE0

= ENABLE1

3:2 PULL_UP

PUPD:

= NONE0

= PULL_DOWN1

= PULL_UP2

= RSVD3

PADCTL_SDMMC4_EMMC4_PAD_DAT3_0

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Offset: 0x40

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_EMMC4_PAD_DAT3_0

Reset: 0x00002048 (0bxxxx,xxxx,0000,xxxx,x01x,xxxx,x1xx,10xx)

Bit Reset Description

23:20 0x0

RFU_IN

14:13 COMP_DRIVE_2X DRV_TYPE:

Unused DRV_TYPE registers Not used for EMMC4 pads

DRV_TYPE[0]:

0 = 1X driver;

1 = 2X driver;

DRV_TYPE[1]:

0 = Driving codes from BDSDMEMCOMP;

1 = Default driving codes;

= COMP_DRIVE_1X0

= COMP_DRIVE_2X1

= DEFAULT_DRIVE_1X2

= DEFAULT_DRIVE_2X3

6 ENABLE

E_INPUT:

= DISABLE0

= ENABLE1

3:2 PULL_UP

PUPD:

= NONE0

= PULL_DOWN1

= PULL_UP2

= RSVD3

PADCTL_SDMMC4_EMMC4_PAD_DAT2_0

Offset: 0x48

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_EMMC4_PAD_DAT2_0

Reset: 0x00002048 (0bxxxx,xxxx,0000,xxxx,x01x,xxxx,x1xx,10xx)

Bit Reset Description

23:20 0x0 RFU_IN

14:13

COMP_DRIVE_2X

DRV_TYPE:

Unused DRV_TYPE registers Not used for EMMC4 pads

DRV_TYPE[0]:

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Bit Reset Description

0 = 1X driver;

1 = 2X driver;

DRV_TYPE[1]:

0 = Driving codes from BDSDMEMCOMP;

1 = Default driving codes;

= COMP_DRIVE_1X0

= COMP_DRIVE_2X1

= DEFAULT_DRIVE_1X2

= DEFAULT_DRIVE_2X3

6 ENABLE E_INPUT:

= DISABLE0

= ENABLE1

3:2 PULL_UP PUPD:

= NONE0

= PULL_DOWN1

= PULL_UP2

= RSVD3

PADCTL_SDMMC4_EMMC4_PAD_DAT1_0

Offset: 0x50

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_EMMC4_PAD_DAT1_0

Reset: 0x00002048 (0bxxxx,xxxx,0000,xxxx,x01x,xxxx,x1xx,10xx)

Bit Reset Description

23:20 0x0 RFU_IN

14:13 COMP_DRIVE_2X DRV_TYPE:

Unused DRV_TYPE registers Not used for EMMC4 pads

DRV_TYPE[0]:

0 = 1X driver;

1 = 2X driver;

DRV_TYPE[1]:

0 = Driving codes from BDSDMEMCOMP;

1 = Default driving codes;

= COMP_DRIVE_1X0

= COMP_DRIVE_2X1

= DEFAULT_DRIVE_1X2

= DEFAULT_DRIVE_2X3

ENABLE

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Bit Reset Description

E_INPUT:

= DISABLE0

= ENABLE1

3:2 PULL_UP

PUPD:

= NONE0

= PULL_DOWN1

= PULL_UP2

= RSVD3

PADCTL_SDMMC4_EMMC4_PAD_DAT0_0

Offset: 0x58

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_EMMC4_PAD_DAT0_0

Reset: 0x00002048 (0bxxxx,xxxx,0000,xxxx,x01x,xxxx,x1xx,10xx)

Bit Reset Description

23:20 0x0

RFU_IN

14:13 COMP_DRIVE_2X DRV_TYPE:

Unused DRV_TYPE registers Not used for EMMC4 pads

DRV_TYPE[0]:

0 = 1X driver;

1 = 2X driver;

DRV_TYPE[1]:

0 = Driving codes from BDSDMEMCOMP;

1 = Default driving codes;

= COMP_DRIVE_1X0

= COMP_DRIVE_2X1

= DEFAULT_DRIVE_1X2

= DEFAULT_DRIVE_2X3

6 ENABLE

E_INPUT:

= DISABLE0

= ENABLE1

3:2 PULL_UP PUPD:

= NONE0

= PULL_DOWN1

= PULL_UP2

= RSVD3

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APEX_CTL PAD Control Registers

PADCTL_PEX_CTL_PEX_L2_CLKREQ_N_0

Offset: 0x0

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_PEX_L2_CLKREQ_N_0

Reset: 0x00000570 (0bxxxx,xxxx,xxxx,xxxx,xxx0,x1x1,x111,0000)

Bit Reset Description

12 DISABLE E_SCHMT:

= DISABLE0

= ENABLE1

10 SFIO GPIO_SF_SEL:

= GPIO0

= SFIO1

8 ENABLE

E_LPDR:

= DISABLE0

= ENABLE1

6 ENABLE

E_INPUT:

= DISABLE0

= ENABLE1

5 ENABLE

E_IO_HV:

= DISABLE0

= ENABLE1

4 TRISTATE

TRISTATE:

= PASSTHROUGH0

= TRISTATE1

3:2 NONE PUPD:

= NONE0

= PULL_DOWN1

= PULL_UP2

= RSVD3

1:0 PE2 PM:

= PE20

= RSVD11

= RSVD22

= RSVD33

PADCTL_PEX_CTL_CFG2TMC_PEX_L2_CLKREQ_N_0

Offset: 0x4

Read/Write: RW

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Parity Protection: N

SCR Protection: SCR_PEX_L2_CLKREQ_N_0

Reset: 0x00000000 (0bxxxx,xxx0,0000,xxx0,0000,xxxx,xxxx,xxxx)

Bit Reset Description

24:20 0x0 CFG_CAL_DRVUP

16:12 0x0 CFG_CAL_DRVDN

PADCTL_PEX_CTL_PEX_WAKE_N_0

Offset: 0x8

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_PEX_WAKE_N_0

Reset: 0x00000570 (0bxxxx,xxxx,xxxx,xxxx,xxx0,x1x1,x111,0000)

Bit Reset Description

12 DISABLE E_SCHMT:

= DISABLE0

= ENABLE1

10 SFIO GPIO_SF_SEL:

= GPIO0

= SFIO1

8 ENABLE E_LPDR:

= DISABLE0

= ENABLE1

6 ENABLE E_INPUT:

= DISABLE0

= ENABLE1

5 ENABLE

E_IO_HV:

= DISABLE0

= ENABLE1

4 TRISTATE

TRISTATE:

= PASSTHROUGH0

= TRISTATE1

3:2 NONE

PUPD:

= NONE0

= PULL_DOWN1

= PULL_UP2

= RSVD3

1:0

RSVD0

PM:

= RSVD00

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Bit Reset Description

= RSVD11

= RSVD22

= RSVD33

PADCTL_PEX_CTL_CFG2TMC_PEX_WAKE_N_0

Offset: 0xc

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_PEX_WAKE_N_0

Reset: 0x00000000 (0bxxxx,xxx0,0000,xxx0,0000,xxxx,xxxx,xxxx)

Bit Reset Description

24:20 0x0 CFG_CAL_DRVUP

16:12 0x0 CFG_CAL_DRVDN

PADCTL_PEX_CTL_PEX_L1_CLKREQ_N_0

Offset: 0x10

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_PEX_L1_CLKREQ_N_0

Reset: 0x00000570 (0bxxxx,xxxx,xxxx,xxxx,xxx0,x1x1,x111,0000)

Bit Reset Description

12 DISABLE E_SCHMT:

= DISABLE0

= ENABLE1

10 SFIO GPIO_SF_SEL:

= GPIO0

= SFIO1

8 ENABLE E_LPDR:

= DISABLE0

= ENABLE1

6 ENABLE E_INPUT:

= DISABLE0

= ENABLE1

5 ENABLE E_IO_HV:

= DISABLE0

= ENABLE1

TRISTATE

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Bit Reset Description

TRISTATE:

= PASSTHROUGH0

= TRISTATE1

3:2 NONE

PUPD:

= NONE0

= PULL_DOWN1

= PULL_UP2

= RSVD3

1:0 PE1 PM:

= PE10

= RSVD11

= RSVD22

= RSVD33

PADCTL_PEX_CTL_CFG2TMC_PEX_L1_CLKREQ_N_0

Offset: 0x14

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_PEX_L1_CLKREQ_N_0

Reset: 0x00000000 (0bxxxx,xxx0,0000,xxx0,0000,xxxx,xxxx,xxxx)

Bit Reset Description

24:20 0x0 CFG_CAL_DRVUP

16:12 0x0 CFG_CAL_DRVDN

PADCTL_PEX_CTL_PEX_L1_RST_N_0

Offset: 0x18

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_PEX_L1_RST_N_0

Reset: 0x00000560 (0bxxxx,xxxx,xxxx,xxxx,xxx0,x1x1,x110,0000)

Bit Reset Description

12 DISABLE E_SCHMT:

= DISABLE0

= ENABLE1

10 SFIO GPIO_SF_SEL:

= GPIO0

= SFIO1

ENABLE

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Bit Reset Description

E_LPDR:

= DISABLE0

= ENABLE1

6 ENABLE E_INPUT:

= DISABLE0

= ENABLE1

5 ENABLE E_IO_HV:

= DISABLE0

= ENABLE1

4 PASSTHROUGH TRISTATE:

= PASSTHROUGH0

= TRISTATE1

3:2 NONE PUPD:

= NONE0

= PULL_DOWN1

= PULL_UP2

= RSVD3

1:0 PE1

PM:

= PE10

= RSVD11

= RSVD22

= ISTCTRL3

PADCTL_PEX_CTL_CFG2TMC_PEX_L1_RST_N_0

Offset: 0x1c

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_PEX_L1_RST_N_0

Reset: 0x00000000 (0bxxxx,xxx0,0000,xxx0,0000,xxxx,xxxx,xxxx)

Bit Reset Description

24:20 0x0 CFG_CAL_DRVUP

16:12 0x0 CFG_CAL_DRVDN

PADCTL_PEX_CTL_PEX_L0_CLKREQ_N_0

Offset: 0x20

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_PEX_L0_CLKREQ_N_0

Reset: 0x00000570 (0bxxxx,xxxx,xxxx,xxxx,xxx0,x1x1,x111,0000)

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Bit Reset Description

12 DISABLE E_SCHMT:

= DISABLE0

= ENABLE1

10 SFIO GPIO_SF_SEL:

= GPIO0

= SFIO1

8 ENABLE E_LPDR:

= DISABLE0

= ENABLE1

6 ENABLE E_INPUT:

= DISABLE0

= ENABLE1

5 ENABLE E_IO_HV:

= DISABLE0

= ENABLE1

4 TRISTATE

TRISTATE:

= PASSTHROUGH0

= TRISTATE1

3:2 NONE

PUPD:

= NONE0

= PULL_DOWN1

= PULL_UP2

= RSVD3

1:0 PE0 PM:

= PE00

= RSVD11

= RSVD22

= RSVD33

PADCTL_PEX_CTL_CFG2TMC_PEX_L0_CLKREQ_N_0

Offset: 0x24

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_PEX_L0_CLKREQ_N_0

Reset: 0x00000000 (0bxxxx,xxx0,0000,xxx0,0000,xxxx,xxxx,xxxx)

Bit Reset Description

24:20 0x0

CFG_CAL_DRVUP

16:12 0x0

CFG_CAL_DRVDN

PADCTL_PEX_CTL_PEX_L0_RST_N_0

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Offset: 0x28

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_PEX_L0_RST_N_0

Reset: 0x00000560 (0bxxxx,xxxx,xxxx,xxxx,xxx0,x1x1,x110,0000)

Bit Reset Description

12 DISABLE

E_SCHMT:

= DISABLE0

= ENABLE1

10 SFIO

GPIO_SF_SEL:

= GPIO0

= SFIO1

8 ENABLE

E_LPDR:

= DISABLE0

= ENABLE1

6 ENABLE E_INPUT:

= DISABLE0

= ENABLE1

5 ENABLE E_IO_HV:

= DISABLE0

= ENABLE1

4 PASSTHROUGH TRISTATE:

= PASSTHROUGH0

= TRISTATE1

3:2 NONE PUPD:

= NONE0

= PULL_DOWN1

= PULL_UP2

= RSVD3

1:0 PE0

PM:

= PE00

= RSVD11

= RSVD22

= ISTCTRL3

PADCTL_PEX_CTL_CFG2TMC_PEX_L0_RST_N_0

Offset: 0x2c

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_PEX_L0_RST_N_0

Reset: 0x00000000 (0bxxxx,xxx0,0000,xxx0,0000,xxxx,xxxx,xxxx)

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Bit Reset Description

24:20 0x0

CFG_CAL_DRVUP

16:12 0x0

CFG_CAL_DRVDN

PADCTL_PEX_CTL_PEX_L2_RST_N_0

Offset: 0x30

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_PEX_L2_RST_N_0

Reset: 0x00000560 (0bxxxx,xxxx,xxxx,xxxx,xxx0,x1x1,x110,0000)

Bit Reset Description

12 DISABLE E_SCHMT:

= DISABLE0

= ENABLE1

10 SFIO GPIO_SF_SEL:

= GPIO0

= SFIO1

8 ENABLE E_LPDR:

= DISABLE0

= ENABLE1

6 ENABLE E_INPUT:

= DISABLE0

= ENABLE1

5 ENABLE E_IO_HV:

= DISABLE0

= ENABLE1

4 PASSTHROUGH

TRISTATE:

= PASSTHROUGH0

= TRISTATE1

3:2 NONE

PUPD:

= NONE0

= PULL_DOWN1

= PULL_UP2

= RSVD3

1:0 PE2 PM:

= PE20

= RSVD11

= RSVD22

= RSVD33

PADCTL_PEX_CTL_CFG2TMC_PEX_L2_RST_N_0

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Offset: 0x34

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_PEX_L2_RST_N_0

Reset: 0x00000000 (0bxxxx,xxx0,0000,xxx0,0000,xxxx,xxxx,xxxx)

Bit Reset Description

24:20 0x0

CFG_CAL_DRVUP

16:12 0x0 CFG_CAL_DRVDN

PADCTL_PEX_CTL_PEX_L3_CLKREQ_N_0

Offset: 0x38

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_PEX_L3_CLKREQ_N_0

Reset: 0x00000570 (0bxxxx,xxxx,xxxx,xxxx,xxx0,x1x1,x111,0000)

Bit Reset Description

12 DISABLE E_SCHMT:

= DISABLE0

= ENABLE1

10 SFIO GPIO_SF_SEL:

= GPIO0

= SFIO1

8 ENABLE

E_LPDR:

= DISABLE0

= ENABLE1

6 ENABLE

E_INPUT:

= DISABLE0

= ENABLE1

5 ENABLE

E_IO_HV:

= DISABLE0

= ENABLE1

4 TRISTATE

TRISTATE:

= PASSTHROUGH0

= TRISTATE1

3:2 NONE PUPD:

= NONE0

= PULL_DOWN1

= PULL_UP2

= RSVD3

1:0

PE3

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Bit Reset Description

PM:

= PE30

= RSVD11

= RSVD22

= RSVD33

PADCTL_PEX_CTL_CFG2TMC_PEX_L3_CLKREQ_N_0

Offset: 0x3c

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_PEX_L3_CLKREQ_N_0

Reset: 0x00000000 (0bxxxx,xxx0,0000,xxx0,0000,xxxx,xxxx,xxxx)

Bit Reset Description

24:20 0x0 CFG_CAL_DRVUP

16:12 0x0

CFG_CAL_DRVDN

PADCTL_PEX_CTL_PEX_L3_RST_N_0

Offset: 0x40

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_PEX_L3_RST_N_0

Reset: 0x00000560 (0bxxxx,xxxx,xxxx,xxxx,xxx0,x1x1,x110,0000)

Bit Reset Description

12 DISABLE

E_SCHMT:

= DISABLE0

= ENABLE1

10 SFIO

GPIO_SF_SEL:

= GPIO0

= SFIO1

8 ENABLE E_LPDR:

= DISABLE0

= ENABLE1

6 ENABLE E_INPUT:

= DISABLE0

= ENABLE1

5 ENABLE E_IO_HV:

= DISABLE0

= ENABLE1

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Bit Reset Description

4 PASSTHROUGH TRISTATE:

= PASSTHROUGH0

= TRISTATE1

3:2 NONE PUPD:

= NONE0

= PULL_DOWN1

= PULL_UP2

= RSVD3

1:0 PE3 PM:

= PE30

= RSVD11

= RSVD22

= RSVD33

PADCTL_PEX_CTL_CFG2TMC_PEX_L3_RST_N_0

Offset: 0x44

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_PEX_L3_RST_N_0

Reset: 0x00000000 (0bxxxx,xxx0,0000,xxx0,0000,xxxx,xxxx,xxxx)

Bit Reset Description

24:20 0x0

CFG_CAL_DRVUP

16:12 0x0

CFG_CAL_DRVDN

PADCTL_PEX_CTL_PEX_L4_CLKREQ_N_0

Offset: 0x48

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_PEX_L4_CLKREQ_N_0

Reset: 0x00000570 (0bxxxx,xxxx,xxxx,xxxx,xxx0,x1x1,x111,0000)

Bit Reset Description

12 DISABLE

E_SCHMT:

= DISABLE0

= ENABLE1

10 SFIO

GPIO_SF_SEL:

= GPIO0

= SFIO1

ENABLE

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Bit Reset Description

E_LPDR:

= DISABLE0

= ENABLE1

6 ENABLE

E_INPUT:

= DISABLE0

= ENABLE1

5 ENABLE

E_IO_HV:

= DISABLE0

= ENABLE1

4 TRISTATE TRISTATE:

= PASSTHROUGH0

= TRISTATE1

3:2 NONE PUPD:

= NONE0

= PULL_DOWN1

= PULL_UP2

= RSVD3

1:0 PE4 PM:

= PE40

= RSVD11

= RSVD22

= RSVD33

PADCTL_PEX_CTL_CFG2TMC_PEX_L4_CLKREQ_N_0

Offset: 0x4c

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_PEX_L4_CLKREQ_N_0

Reset: 0x00000000 (0bxxxx,xxx0,0000,xxx0,0000,xxxx,xxxx,xxxx)

Bit Reset Description

24:20 0x0

CFG_CAL_DRVUP

16:12 0x0

CFG_CAL_DRVDN

PADCTL_PEX_CTL_PEX_L4_RST_N_0

Offset: 0x50

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_PEX_L4_RST_N_0

Reset: 0x00000560 (0bxxxx,xxxx,xxxx,xxxx,xxx0,x1x1,x110,0000)

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Bit Reset Description

12 DISABLE E_SCHMT:

= DISABLE0

= ENABLE1

10 SFIO

GPIO_SF_SEL:

= GPIO0

= SFIO1

8 ENABLE

E_LPDR:

= DISABLE0

= ENABLE1

6 ENABLE E_INPUT:

= DISABLE0

= ENABLE1

5 ENABLE E_IO_HV:

= DISABLE0

= ENABLE1

4 PASSTHROUGH TRISTATE:

= PASSTHROUGH0

= TRISTATE1

3:2 NONE PUPD:

= NONE0

= PULL_DOWN1

= PULL_UP2

= RSVD3

1:0 PE4

PM:

= PE40

= RSVD11

= RSVD22

= RSVD33

PADCTL_PEX_CTL_CFG2TMC_PEX_L4_RST_N_0

Offset: 0x54

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_PEX_L4_RST_N_0

Reset: 0x00000000 (0bxxxx,xxx0,0000,xxx0,0000,xxxx,xxxx,xxxx)

Bit Reset Description

24:20 0x0 CFG_CAL_DRVUP

16:12 0x0 CFG_CAL_DRVDN

PADCTL_PEX_CTL_SATA_DEV_SLP_0

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Offset: 0x58

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_SATA_DEV_SLP_0

Reset: 0x00000430 (0bxxxx,xxxx,xxxx,xxxx,xxx0,x1x0,x011,0000)

Bit Reset Description

12 DISABLE E_SCHMT:

= DISABLE0

= ENABLE1

10 SFIO GPIO_SF_SEL:

= GPIO0

= SFIO1

8 DISABLE E_LPDR:

= DISABLE0

= ENABLE1

6 DISABLE E_INPUT:

= DISABLE0

= ENABLE1

5 ENABLE

E_IO_HV:

= DISABLE0

= ENABLE1

4 TRISTATE

TRISTATE:

= PASSTHROUGH0

= TRISTATE1

3:2 NONE PUPD:

= NONE0

= PULL_DOWN1

= PULL_UP2

= RSVD3

1:0 SATA PM:

= SATA0

= RSVD11

= RSVD22

= RSVD33

PADCTL_PEX_CTL_CFG2TMC_SATA_DEV_SLP_0

Offset: 0x5c

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_SATA_DEV_SLP_0

Reset: 0x00000000 (0bxxxx,xxx0,0000,xxx0,0000,xxxx,xxxx,xxxx)

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Bit Reset Description

24:20 0x0 CFG_CAL_DRVUP

16:12 0x0 CFG_CAL_DRVDN

SDMMC1 High Voltage PAD Control Registers

PADCTL_SDMMC1_HV_SDMMC1_CLK_0

Offset: 0x0

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_SDMMC1_CLK_0

Reset: 0x0000a474 (0b0000,0000,0000,xxx0,1010,x10x,x111,0100)

Bit Reset Description

31:28 0x0

SPARE_VDD

27:24 0x0

SPARE_VAUXC

23:20 0x0 RFU_IN

16:15 0x1 SCHMITT

14:13 COMP_DRIVE_2X DRV_TYPE:

DRV_TYPE[0]:

0 = 1X driver;

1 = 2X driver;

DRV_TYPE[1]:

0 = Driving codes from BDSDMEMCOMP;

1 = Default driving codes;

= COMP_DRIVE_1X0

= COMP_DRIVE_2X1

= DEFAULT_DRIVE_1X2

= DEFAULT_DRIVE_2X3

12 DISABLE E_SCHMT:

= DISABLE0

= ENABLE1

10 SFIO GPIO_SF_SEL:

= GPIO0

= SFIO1

9 DISABLE

E_PBIAS_BUF:

= DISABLE0

= ENABLE1

ENABLE

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Bit Reset Description

E_INPUT:

= DISABLE0

= ENABLE1

5 ENABLE

E_LPBK:

= DISABLE0

= ENABLE1

4 TRISTATE

TRISTATE:

= PASSTHROUGH0

= TRISTATE1

3:2 PULL_DOWN PUPD:

= NONE0

= PULL_DOWN1

= PULL_UP2

= RSVD3

1:0 SDMMC1 PM:

= SDMMC10

= RSVD11

= MIPI2

= RSVD33

PADCTL_SDMMC1_HV_CFG2TMC_SDMMC1_CLK_0

Offset: 0x4

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_SDMMC1_CLK_0

Reset: 0x00000000 (0b0000,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:30 0x0

CFG_CAL_DRVUP_DEF

29:28 0x0 CFG_CAL_DRVDN_DEF

PADCTL_SDMMC1_HV_SDMMC1_CMD_0

Offset: 0x8

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_SDMMC1_CMD_0

Reset: 0x0000a458 (0b0000,0000,0000,xxx0,1010,x10x,x1x1,1000)

Bit Reset Description

31:28 0x0 SPARE_VDD

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Bit Reset Description

27:24 0x0 SPARE_VAUXC

23:20 0x0 RFU_IN

16:15 0x1

SCHMITT

14:13 COMP_DRIVE_2X

DRV_TYPE:

DRV_TYPE[0]:

0 = 1X driver;

1 = 2X driver;

DRV_TYPE[1]:

0 = Driving codes from BDSDMEMCOMP;

1 = Default driving codes;

= COMP_DRIVE_1X0

= COMP_DRIVE_2X1

= DEFAULT_DRIVE_1X2

= DEFAULT_DRIVE_2X3

12 DISABLE

E_SCHMT:

= DISABLE0

= ENABLE1

10 SFIO GPIO_SF_SEL:

= GPIO0

= SFIO1

9 DISABLE E_PBIAS_BUF:

= DISABLE0

= ENABLE1

6 ENABLE E_INPUT:

= DISABLE0

= ENABLE1

4 TRISTATE TRISTATE:

= PASSTHROUGH0

= TRISTATE1

3:2 PULL_UP PUPD:

= NONE0

= PULL_DOWN1

= PULL_UP2

= RSVD3

1:0 SDMMC1

PM:

= SDMMC10

= RSVD11

= MIPI2

= RSVD33

PADCTL_SDMMC1_HV_CFG2TMC_SDMMC1_CMD_0

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Offset: 0xc

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_SDMMC1_CMD_0

Reset: 0x00000000 (0b0000,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:30 0x0

CFG_CAL_DRVUP_DEF

29:28 0x0 CFG_CAL_DRVDN_DEF

PADCTL_SDMMC1_HV_SDMMC1_COMP_0

Offset: 0x10

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_SDMMC1_COMP_0

Reset: 0x00000000 (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxx0,xx00)

Bit Reset Description

4 PASSTHROUGH TRISTATE:

= PASSTHROUGH0

= TRISTATE1

1:0 SDMMC1 PM:

= SDMMC10

= RSVD11

= RSVD22

= RSVD33

reg CFG2TMC_SDMMC1_COMP not used

PADCTL_SDMMC1_HV_SDMMC1_DAT3_0

Offset: 0x18

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_SDMMC1_DAT3_0

Reset: 0x0000a458 (0b0000,0000,0000,xxx0,1010,x10x,x1x1,1000)

Bit Reset Description

31:28 0x0 SPARE_VDD

27:24 0x0 SPARE_VAUXC

23:20 0x0 RFU_IN

16:15 0x1 SCHMITT

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Bit Reset Description

14:13 COMP_DRIVE_2X DRV_TYPE:

DRV_TYPE[0]:

0 = 1X driver;

1 = 2X driver;

DRV_TYPE[1]:

0 = Driving codes from BDSDMEMCOMP;

1 = Default driving codes;

= COMP_DRIVE_1X0

= COMP_DRIVE_2X1

= DEFAULT_DRIVE_1X2

= DEFAULT_DRIVE_2X3

12 DISABLE E_SCHMT:

= DISABLE0

= ENABLE1

10 SFIO GPIO_SF_SEL:

= GPIO0

= SFIO1

9 DISABLE E_PBIAS_BUF:

= DISABLE0

= ENABLE1

6 ENABLE

E_INPUT:

= DISABLE0

= ENABLE1

4 TRISTATE

TRISTATE:

= PASSTHROUGH0

= TRISTATE1

3:2 PULL_UP

PUPD:

= NONE0

= PULL_DOWN1

= PULL_UP2

= RSVD3

1:0 SDMMC1 PM:

= SDMMC10

= RSVD11

= MIPI2

= RSVD33

PADCTL_SDMMC1_HV_CFG2TMC_SDMMC1_DAT3_0

Offset: 0x1c

Read/Write: RW

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Parity Protection: N

SCR Protection: SCR_SDMMC1_DAT3_0

Reset: 0x00000000 (0b0000,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:30 0x0 CFG_CAL_DRVUP_DEF

29:28 0x0 CFG_CAL_DRVDN_DEF

PADCTL_SDMMC1_HV_SDMMC1_DAT2_0

Offset: 0x20

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_SDMMC1_DAT2_0

Reset: 0x0000a458 (0b0000,0000,0000,xxx0,1010,x10x,x1x1,1000)

Bit Reset Description

31:28 0x0 SPARE_VDD

27:24 0x0 SPARE_VAUXC

23:20 0x0

RFU_IN

16:15 0x1

SCHMITT

14:13 COMP_DRIVE_2X

DRV_TYPE:

DRV_TYPE[0]:

0 = 1X driver;

1 = 2X driver;

DRV_TYPE[1]:

0 = Driving codes from BDSDMEMCOMP;

1 = Default driving codes;

= COMP_DRIVE_1X0

= COMP_DRIVE_2X1

= DEFAULT_DRIVE_1X2

= DEFAULT_DRIVE_2X3

12 DISABLE

E_SCHMT:

= DISABLE0

= ENABLE1

10 SFIO

GPIO_SF_SEL:

= GPIO0

= SFIO1

9 DISABLE

E_PBIAS_BUF:

= DISABLE0

= ENABLE1

ENABLE

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Bit Reset Description

E_INPUT:

= DISABLE0

= ENABLE1

4 TRISTATE TRISTATE:

= PASSTHROUGH0

= TRISTATE1

3:2 PULL_UP PUPD:

= NONE0

= PULL_DOWN1

= PULL_UP2

= RSVD3

1:0 SDMMC1

PM:

= SDMMC10

= RSVD11

= MIPI2

= RSVD33

PADCTL_SDMMC1_HV_CFG2TMC_SDMMC1_DAT2_0

Offset: 0x24

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_SDMMC1_DAT2_0

Reset: 0x00000000 (0b0000,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:30 0x0 CFG_CAL_DRVUP_DEF

29:28 0x0

CFG_CAL_DRVDN_DEF

PADCTL_SDMMC1_HV_SDMMC1_DAT1_0

Offset: 0x28

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_SDMMC1_DAT1_0

Reset: 0x0000a458 (0b0000,0000,0000,xxx0,1010,x10x,x1x1,1000)

Bit Reset Description

31:28 0x0

SPARE_VDD

27:24 0x0

SPARE_VAUXC

23:20 0x0 RFU_IN

16:15 0x1 SCHMITT

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Bit Reset Description

14:13 COMP_DRIVE_2X

DRV_TYPE:

DRV_TYPE[0]:

0 = 1X driver;

1 = 2X driver;

DRV_TYPE[1]:

0 = Driving codes from BDSDMEMCOMP;

1 = Default driving codes;

= COMP_DRIVE_1X0

= COMP_DRIVE_2X1

= DEFAULT_DRIVE_1X2

= DEFAULT_DRIVE_2X3

12 DISABLE

E_SCHMT:

= DISABLE0

= ENABLE1

10 SFIO

GPIO_SF_SEL:

= GPIO0

= SFIO1

9 DISABLE

E_PBIAS_BUF:

= DISABLE0

= ENABLE1

6 ENABLE E_INPUT:

= DISABLE0

= ENABLE1

4 TRISTATE TRISTATE:

= PASSTHROUGH0

= TRISTATE1

3:2 PULL_UP PUPD:

= NONE0

= PULL_DOWN1

= PULL_UP2

= RSVD3

1:0 SDMMC1

PM:

= SDMMC10

= RSVD11

= MIPI2

= RSVD33

PADCTL_SDMMC1_HV_CFG2TMC_SDMMC1_DAT1_0

Offset: 0x2c

Read/Write: RW

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Parity Protection: N

SCR Protection: SCR_SDMMC1_DAT1_0

Reset: 0x00000000 (0b0000,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:30 0x0

CFG_CAL_DRVUP_DEF

29:28 0x0

CFG_CAL_DRVDN_DEF

PADCTL_SDMMC1_HV_SDMMC1_DAT0_0

Offset: 0x30

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_SDMMC1_DAT0_0

Reset: 0x0000a458 (0b0000,0000,0000,xxx0,1010,x10x,x1x1,1000)

Bit Reset Description

31:28 0x0 SPARE_VDD

27:24 0x0 SPARE_VAUXC

23:20 0x0 RFU_IN

16:15 0x1 SCHMITT

14:13 COMP_DRIVE_2X DRV_TYPE:

DRV_TYPE[0]:

0 = 1X driver;

1 = 2X driver;

DRV_TYPE[1]:

0 = Driving codes from BDSDMEMCOMP;

1 = Default driving codes;

= COMP_DRIVE_1X0

= COMP_DRIVE_2X1

= DEFAULT_DRIVE_1X2

= DEFAULT_DRIVE_2X3

12 DISABLE E_SCHMT:

= DISABLE0

= ENABLE1

10 SFIO GPIO_SF_SEL:

= GPIO0

= SFIO1

9 DISABLE E_PBIAS_BUF:

= DISABLE0

= ENABLE1

ENABLE

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Bit Reset Description

E_INPUT:

= DISABLE0

= ENABLE1

4 TRISTATE

TRISTATE:

= PASSTHROUGH0

= TRISTATE1

3:2 PULL_UP

PUPD:

= NONE0

= PULL_DOWN1

= PULL_UP2

= RSVD3

1:0 SDMMC1 PM:

= SDMMC10

= RSVD11

= MIPI2

= RSVD33

PADCTL_SDMMC1_HV_CFG2TMC_SDMMC1_DAT0_0

Offset: 0x34

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_SDMMC1_DAT0_0

Reset: 0x00000000 (0b0000,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:30 0x0

CFG_CAL_DRVUP_DEF

29:28 0x0 CFG_CAL_DRVDN_DEF

SDMMC3 High Voltage PAD Control Registers

PADCTL_SDMMC3_HV_SDMMC3_DAT3_0

Offset: 0x0

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_SDMMC3_DAT3_0

Reset: 0x0000a458 (0b0000,0000,0000,xxx0,1010,x10x,x1x1,1000)

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Bit Reset Description

31:28 0x0 SPARE_VDD

27:24 0x0 SPARE_VAUXC

23:20 0x0

RFU_IN

16:15 0x1

SCHMITT

14:13 COMP_DRIVE_2X

DRV_TYPE:

DRV_TYPE[0]:

0 = 1X driver;

1 = 2X driver;

DRV_TYPE[1]:

0 = Driving codes from BDSDMEMCOMP;

1 = Default driving codes;

= COMP_DRIVE_1X0

= COMP_DRIVE_2X1

= DEFAULT_DRIVE_1X2

= DEFAULT_DRIVE_2X3

12 DISABLE

E_SCHMT:

= DISABLE0

= ENABLE1

10 SFIO

GPIO_SF_SEL:

= GPIO0

= SFIO1

9 DISABLE

E_PBIAS_BUF:

= DISABLE0

= ENABLE1

6 ENABLE E_INPUT:

= DISABLE0

= ENABLE1

4 TRISTATE TRISTATE:

= PASSTHROUGH0

= TRISTATE1

3:2 PULL_UP PUPD:

= NONE0

= PULL_DOWN1

= PULL_UP2

= RSVD3

1:0 SDMMC3

PM:

= SDMMC30

= RSVD11

= RSVD22

= RSVD33

PADCTL_SDMMC3_HV_CFG2TMC_SDMMC3_DAT3_0

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Offset: 0x4

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_SDMMC3_DAT3_0

Reset: 0x00000000 (0b0000,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:30 0x0 CFG_CAL_DRVUP_DEF

29:28 0x0 CFG_CAL_DRVDN_DEF

PADCTL_SDMMC3_HV_SDMMC3_DAT2_0

Offset: 0x8

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_SDMMC3_DAT2_0

Reset: 0x0000a458 (0b0000,0000,0000,xxx0,1010,x10x,x1x1,1000)

Bit Reset Description

31:28 0x0 SPARE_VDD

27:24 0x0 SPARE_VAUXC

23:20 0x0 RFU_IN

16:15 0x1

SCHMITT

14:13 COMP_DRIVE_2X

DRV_TYPE:

DRV_TYPE[0]:

0 = 1X driver;

1 = 2X driver;

DRV_TYPE[1]:

0 = Driving codes from BDSDMEMCOMP;

1 = Default driving codes;

= COMP_DRIVE_1X0

= COMP_DRIVE_2X1

= DEFAULT_DRIVE_1X2

= DEFAULT_DRIVE_2X3

12 DISABLE

E_SCHMT:

= DISABLE0

= ENABLE1

10 SFIO GPIO_SF_SEL:

= GPIO0

= SFIO1

DISABLE

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Bit Reset Description

E_PBIAS_BUF:

= DISABLE0

= ENABLE1

6 ENABLE E_INPUT:

= DISABLE0

= ENABLE1

4 TRISTATE TRISTATE:

= PASSTHROUGH0

= TRISTATE1

3:2 PULL_UP PUPD:

= NONE0

= PULL_DOWN1

= PULL_UP2

= RSVD3

1:0 SDMMC3

PM:

= SDMMC30

= RSVD11

= RSVD22

= RSVD33

PADCTL_SDMMC3_HV_CFG2TMC_SDMMC3_DAT2_0

Offset: 0xc

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_SDMMC3_DAT2_0

Reset: 0x00000000 (0b0000,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:30 0x0 CFG_CAL_DRVUP_DEF

29:28 0x0 CFG_CAL_DRVDN_DEF

PADCTL_SDMMC3_HV_SDMMC3_DAT1_0

Offset: 0x10

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_SDMMC3_DAT1_0

Reset: 0x0000a458 (0b0000,0000,0000,xxx0,1010,x10x,x1x1,1000)

Bit Reset Description

31:28 0x0

SPARE_VDD

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Bit Reset Description

27:24 0x0 SPARE_VAUXC

23:20 0x0 RFU_IN

16:15 0x1 SCHMITT

14:13 COMP_DRIVE_2X DRV_TYPE:

DRV_TYPE[0]:

0 = 1X driver;

1 = 2X driver;

DRV_TYPE[1]:

0 = Driving codes from BDSDMEMCOMP;

1 = Default driving codes;

= COMP_DRIVE_1X0

= COMP_DRIVE_2X1

= DEFAULT_DRIVE_1X2

= DEFAULT_DRIVE_2X3

12 DISABLE E_SCHMT:

= DISABLE0

= ENABLE1

10 SFIO GPIO_SF_SEL:

= GPIO0

= SFIO1

9 DISABLE

E_PBIAS_BUF:

= DISABLE0

= ENABLE1

6 ENABLE

E_INPUT:

= DISABLE0

= ENABLE1

4 TRISTATE

TRISTATE:

= PASSTHROUGH0

= TRISTATE1

3:2 PULL_UP

PUPD:

= NONE0

= PULL_DOWN1

= PULL_UP2

= RSVD3

1:0 SDMMC3 PM:

= SDMMC30

= RSVD11

= RSVD22

= RSVD33

PADCTL_SDMMC3_HV_CFG2TMC_SDMMC3_DAT1_0

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Offset: 0x14

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_SDMMC3_DAT1_0

Reset: 0x00000000 (0b0000,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:30 0x0 CFG_CAL_DRVUP_DEF

29:28 0x0 CFG_CAL_DRVDN_DEF

PADCTL_SDMMC3_HV_SDMMC3_DAT0_0

Offset: 0x18

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_SDMMC3_DAT0_0

Reset: 0x0000a458 (0b0000,0000,0000,xxx0,1010,x10x,x1x1,1000)

Bit Reset Description

31:28 0x0

SPARE_VDD

27:24 0x0

SPARE_VAUXC

23:20 0x0

RFU_IN

16:15 0x1 SCHMITT

14:13 COMP_DRIVE_2X DRV_TYPE:

DRV_TYPE[0]:

0 = 1X driver;

1 = 2X driver;

DRV_TYPE[1]:

0 = Driving codes from BDSDMEMCOMP;

1 = Default driving codes;

= COMP_DRIVE_1X0

= COMP_DRIVE_2X1

= DEFAULT_DRIVE_1X2

= DEFAULT_DRIVE_2X3

12 DISABLE E_SCHMT:

= DISABLE0

= ENABLE1

10 SFIO

GPIO_SF_SEL:

= GPIO0

= SFIO1

DISABLE

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Bit Reset Description

E_PBIAS_BUF:

= DISABLE0

= ENABLE1

6 ENABLE

E_INPUT:

= DISABLE0

= ENABLE1

4 TRISTATE

TRISTATE:

= PASSTHROUGH0

= TRISTATE1

3:2 PULL_UP

PUPD:

= NONE0

= PULL_DOWN1

= PULL_UP2

= RSVD3

1:0 SDMMC3 PM:

= SDMMC30

= RSVD11

= RSVD22

= RSVD33

PADCTL_SDMMC3_HV_CFG2TMC_SDMMC3_DAT0_0

Offset: 0x1c

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_SDMMC3_DAT0_0

Reset: 0x00000000 (0b0000,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:30 0x0

CFG_CAL_DRVUP_DEF

29:28 0x0

CFG_CAL_DRVDN_DEF

PADCTL_SDMMC3_HV_SDMMC3_COMP_0

Offset: 0x20

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_SDMMC3_COMP_0

Reset: 0x00000000 (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxx0,xx00)

Bit Reset Description

PASSTHROUGH

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Bit Reset Description

TRISTATE:

= PASSTHROUGH0

= TRISTATE1

1:0 SDMMC3 PM:

= SDMMC30

= RSVD11

= RSVD22

= RSVD33

reg CFG2TMC_SDMMC3_COMP not used

PADCTL_SDMMC3_HV_SDMMC3_CMD_0

Offset: 0x28

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_SDMMC3_CMD_0

Reset: 0x0000a458 (0b0000,0000,0000,xxx0,1010,x10x,x1x1,1000)

Bit Reset Description

31:28 0x0 SPARE_VDD

27:24 0x0 SPARE_VAUXC

23:20 0x0

RFU_IN

16:15 0x1

SCHMITT

14:13 COMP_DRIVE_2X

DRV_TYPE:

DRV_TYPE[0]:

0 = 1X driver;

1 = 2X driver;

DRV_TYPE[1]:

0 = Driving codes from BDSDMEMCOMP;

1 = Default driving codes;

= COMP_DRIVE_1X0

= COMP_DRIVE_2X1

= DEFAULT_DRIVE_1X2

= DEFAULT_DRIVE_2X3

12 DISABLE

E_SCHMT:

= DISABLE0

= ENABLE1

10 SFIO

GPIO_SF_SEL:

= GPIO0

= SFIO1

DISABLE

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Bit Reset Description

E_PBIAS_BUF:

= DISABLE0

= ENABLE1

6 ENABLE

E_INPUT:

= DISABLE0

= ENABLE1

4 TRISTATE

TRISTATE:

= PASSTHROUGH0

= TRISTATE1

3:2 PULL_UP PUPD:

= NONE0

= PULL_DOWN1

= PULL_UP2

= RSVD3

1:0 SDMMC3 PM:

= SDMMC30

= RSVD11

= RSVD22

= RSVD33

PADCTL_SDMMC3_HV_CFG2TMC_SDMMC3_CMD_0

Offset: 0x2c

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_SDMMC3_CMD_0

Reset: 0x00000000 (0b0000,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:30 0x0

CFG_CAL_DRVUP_DEF

29:28 0x0 CFG_CAL_DRVDN_DEF

PADCTL_SDMMC3_HV_SDMMC3_CLK_0

Offset: 0x30

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_SDMMC3_CLK_0

Reset: 0x0000a474 (0b0000,0000,0000,xxx0,1010,x10x,x111,0100)

Bit Reset Description

31:28 0x0 SPARE_VDD

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Bit Reset Description

27:24 0x0 SPARE_VAUXC

23:20 0x0 RFU_IN

16:15 0x1

SCHMITT

14:13 COMP_DRIVE_2X

DRV_TYPE:

DRV_TYPE[0]:

0 = 1X driver;

1 = 2X driver;

DRV_TYPE[1]:

0 = Driving codes from BDSDMEMCOMP;

1 = Default driving codes;

= COMP_DRIVE_1X0

= COMP_DRIVE_2X1

= DEFAULT_DRIVE_1X2

= DEFAULT_DRIVE_2X3

12 DISABLE

E_SCHMT:

= DISABLE0

= ENABLE1

10 SFIO GPIO_SF_SEL:

= GPIO0

= SFIO1

9 DISABLE E_PBIAS_BUF:

= DISABLE0

= ENABLE1

6 ENABLE E_INPUT:

= DISABLE0

= ENABLE1

5 ENABLE E_LPBK:

= DISABLE0

= ENABLE1

4 TRISTATE TRISTATE:

= PASSTHROUGH0

= TRISTATE1

3:2 PULL_DOWN

PUPD:

= NONE0

= PULL_DOWN1

= PULL_UP2

= RSVD3

1:0 SDMMC3 PM:

= SDMMC30

= RSVD11

= RSVD22

= RSVD33

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PADCTL_SDMMC3_HV_CFG2TMC_SDMMC3_CLK_0

Offset: 0x34

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_SDMMC3_CLK_0

Reset: 0x00000000 (0b0000,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:30 0x0 CFG_CAL_DRVUP_DEF

29:28 0x0 CFG_CAL_DRVDN_DEF

QSPI PAD Control Registers

PADCTL_QSPI_QSPI0_IO3_0

Offset: 0x0

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_QSPI0_IO3_0

Reset: 0x00023458 (0bxxxx,xxxx,0000,xx1x,0011,x10x,x1x1,1000)

Bit Reset Description

23:20 0x0 RFU_IN

17 IORESET IO_RESET:

= NORMAL0

= IORESET1

15 DISABLE E_PREEMP:

= DISABLE0

= ENABLE1

14:13 COMP_DRIVE_2X DRV_TYPE:

DRV_TYPE[0]:

0 = 1X driver;

1 = 2X driver;

DRV_TYPE[1]:

0 = Driving codes from BDSDMEMCOMP;

1 = Default driving codes;

= COMP_DRIVE_1X0

= COMP_DRIVE_2X1

= DEFAULT_DRIVE_1X2

= DEFAULT_DRIVE_2X3

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Bit Reset Description

12 ENABLE E_SCHMT:

= DISABLE0

= ENABLE1

10 SFIO GPIO_SF_SEL:

= GPIO0

= SFIO1

9 DISABLE E_HSM:

= DISABLE0

= ENABLE1

6 ENABLE E_INPUT:

= DISABLE0

= ENABLE1

4 TRISTATE

TRISTATE:

= PASSTHROUGH0

= TRISTATE1

3:2 PULL_UP

PUPD:

= NONE0

= PULL_DOWN1

= PULL_UP2

= RSVD3

1:0 QSPI0 PM:

= QSPI00

= RSVD11

= RSVD22

= RSVD33

PADCTL_QSPI_QSPI0_IO2_0

Offset: 0x8

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_QSPI0_IO2_0

Reset: 0x00023458 (0bxxxx,xxxx,0000,xx1x,0011,x10x,x1x1,1000)

Bit Reset Description

23:20 0x0 RFU_IN

17 IORESET IO_RESET:

= NORMAL0

= IORESET1

DISABLE

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Bit Reset Description

E_PREEMP:

= DISABLE0

= ENABLE1

14:13 COMP_DRIVE_2X

DRV_TYPE:

DRV_TYPE[0]:

0 = 1X driver;

1 = 2X driver;

DRV_TYPE[1]:

0 = Driving codes from BDSDMEMCOMP;

1 = Default driving codes;

= COMP_DRIVE_1X0

= COMP_DRIVE_2X1

= DEFAULT_DRIVE_1X2

= DEFAULT_DRIVE_2X3

12 ENABLE

E_SCHMT:

= DISABLE0

= ENABLE1

10 SFIO GPIO_SF_SEL:

= GPIO0

= SFIO1

9 DISABLE E_HSM:

= DISABLE0

= ENABLE1

6 ENABLE E_INPUT:

= DISABLE0

= ENABLE1

4 TRISTATE TRISTATE:

= PASSTHROUGH0

= TRISTATE1

3:2 PULL_UP PUPD:

= NONE0

= PULL_DOWN1

= PULL_UP2

= RSVD3

1:0 QSPI0

PM:

= QSPI00

= RSVD11

= RSVD22

= RSVD33

PADCTL_QSPI_QSPI0_IO1_0

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Offset: 0x10

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_QSPI0_IO1_0

Reset: 0x00023458 (0bxxxx,xxxx,0000,xx1x,0011,x10x,x1x1,1000)

Bit Reset Description

23:20 0x0 RFU_IN

17 IORESET IO_RESET:

= NORMAL0

= IORESET1

15 DISABLE E_PREEMP:

= DISABLE0

= ENABLE1

14:13 COMP_DRIVE_2X DRV_TYPE:

DRV_TYPE[0]:

0 = 1X driver;

1 = 2X driver;

DRV_TYPE[1]:

0 = Driving codes from BDSDMEMCOMP;

1 = Default driving codes;

= COMP_DRIVE_1X0

= COMP_DRIVE_2X1

= DEFAULT_DRIVE_1X2

= DEFAULT_DRIVE_2X3

12 ENABLE E_SCHMT:

= DISABLE0

= ENABLE1

10 SFIO GPIO_SF_SEL:

= GPIO0

= SFIO1

9 DISABLE

E_HSM:

= DISABLE0

= ENABLE1

6 ENABLE

E_INPUT:

= DISABLE0

= ENABLE1

4 TRISTATE

TRISTATE:

= PASSTHROUGH0

= TRISTATE1

3:2

PULL_UP

PUPD:

= NONE0

= PULL_DOWN1

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Bit Reset Description

= PULL_UP2

= RSVD3

1:0 QSPI0 PM:

= QSPI00

= RSVD11

= RSVD22

= RSVD33

PADCTL_QSPI_QSPI0_IO0_0

Offset: 0x18

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_QSPI0_IO0_0

Reset: 0x00023458 (0bxxxx,xxxx,0000,xx1x,0011,x10x,x1x1,1000)

Bit Reset Description

23:20 0x0 RFU_IN

17 IORESET IO_RESET:

= NORMAL0

= IORESET1

15 DISABLE E_PREEMP:

= DISABLE0

= ENABLE1

14:13 COMP_DRIVE_2X DRV_TYPE:

DRV_TYPE[0]:

0 = 1X driver;

1 = 2X driver;

DRV_TYPE[1]:

0 = Driving codes from BDSDMEMCOMP;

1 = Default driving codes;

= COMP_DRIVE_1X0

= COMP_DRIVE_2X1

= DEFAULT_DRIVE_1X2

= DEFAULT_DRIVE_2X3

12 ENABLE E_SCHMT:

= DISABLE0

= ENABLE1

10 SFIO GPIO_SF_SEL:

= GPIO0

= SFIO1

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Bit Reset Description

9 DISABLE E_HSM:

= DISABLE0

= ENABLE1

6 ENABLE E_INPUT:

= DISABLE0

= ENABLE1

4 TRISTATE TRISTATE:

= PASSTHROUGH0

= TRISTATE1

3:2 PULL_UP PUPD:

= NONE0

= PULL_DOWN1

= PULL_UP2

= RSVD3

1:0 QSPI0

PM:

= QSPI00

= RSVD11

= RSVD22

= RSVD33

PADCTL_QSPI_QSPI0_SCK_0

Offset: 0x20

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_QSPI0_SCK_0

Reset: 0x00023474 (0bxxxx,xxxx,0000,xx1x,0011,x10x,x111,0100)

Bit Reset Description

23:20 0x0

RFU_IN

17 IORESET

IO_RESET:

= NORMAL0

= IORESET1

15 DISABLE

E_PREEMP:

= DISABLE0

= ENABLE1

14:13

COMP_DRIVE_2X

DRV_TYPE:

DRV_TYPE[0]:

0 = 1X driver;

1 = 2X driver;

DRV_TYPE[1]:

0 = Driving codes from BDSDMEMCOMP;

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Bit Reset Description

1 = Default driving codes;

= COMP_DRIVE_1X0

= COMP_DRIVE_2X1

= DEFAULT_DRIVE_1X2

= DEFAULT_DRIVE_2X3

12 ENABLE

E_SCHMT:

= DISABLE0

= ENABLE1

10 SFIO

GPIO_SF_SEL:

= GPIO0

= SFIO1

9 DISABLE E_HSM:

= DISABLE0

= ENABLE1

6 ENABLE E_INPUT:

= DISABLE0

= ENABLE1

5 ENABLE E_LPBK:

= DISABLE0

= ENABLE1

4 TRISTATE TRISTATE:

= PASSTHROUGH0

= TRISTATE1

3:2 PULL_DOWN PUPD:

= NONE0

= PULL_DOWN1

= PULL_UP2

= RSVD3

1:0 QSPI0

PM:

= QSPI00

= RSVD11

= RSVD22

= RSVD33

PADCTL_QSPI_QSPI0_CS_N_0

Offset: 0x28

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_QSPI0_CS_N_0

Reset: 0x00023418 (0bxxxx,xxxx,0000,xx1x,0011,x10x,x0x1,1000)

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Bit Reset Description

23:20 0x0 RFU_IN

17 IORESET

IO_RESET:

= NORMAL0

= IORESET1

15 DISABLE

E_PREEMP:

= DISABLE0

= ENABLE1

14:13 COMP_DRIVE_2X DRV_TYPE:

DRV_TYPE[0]:

0 = 1X driver;

1 = 2X driver;

DRV_TYPE[1]:

0 = Driving codes from BDSDMEMCOMP;

1 = Default driving codes;

= COMP_DRIVE_1X0

= COMP_DRIVE_2X1

= DEFAULT_DRIVE_1X2

= DEFAULT_DRIVE_2X3

12 ENABLE E_SCHMT:

= DISABLE0

= ENABLE1

10 SFIO GPIO_SF_SEL:

= GPIO0

= SFIO1

9 DISABLE E_HSM:

= DISABLE0

= ENABLE1

6 DISABLE E_INPUT:

= DISABLE0

= ENABLE1

4 TRISTATE

TRISTATE:

= PASSTHROUGH0

= TRISTATE1

3:2 PULL_UP

PUPD:

= NONE0

= PULL_DOWN1

= PULL_UP2

= RSVD3

1:0 QSPI0 PM:

= QSPI00

= RSVD11

= RSVD22

= RSVD33

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PADCTL_QSPI_QSPI1_IO3_0

Offset: 0x30

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_QSPI1_IO3_0

Reset: 0x00023458 (0bxxxx,xxxx,0000,xx1x,0011,x10x,x1x1,1000)

Bit Reset Description

23:20 0x0 RFU_IN

17 IORESET IO_RESET:

= NORMAL0

= IORESET1

15 DISABLE E_PREEMP:

= DISABLE0

= ENABLE1

14:13 COMP_DRIVE_2X DRV_TYPE:

DRV_TYPE[0]:

0 = 1X driver;

1 = 2X driver;

DRV_TYPE[1]:

0 = Driving codes from BDSDMEMCOMP;

1 = Default driving codes;

= COMP_DRIVE_1X0

= COMP_DRIVE_2X1

= DEFAULT_DRIVE_1X2

= DEFAULT_DRIVE_2X3

12 ENABLE E_SCHMT:

= DISABLE0

= ENABLE1

10 SFIO GPIO_SF_SEL:

= GPIO0

= SFIO1

9 DISABLE

E_HSM:

= DISABLE0

= ENABLE1

6 ENABLE

E_INPUT:

= DISABLE0

= ENABLE1

TRISTATE

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Bit Reset Description

TRISTATE:

= PASSTHROUGH0

= TRISTATE1

3:2 PULL_UP PUPD:

= NONE0

= PULL_DOWN1

= PULL_UP2

= RSVD3

1:0 QSPI1 PM:

= QSPI10

= RSVD11

= RSVD22

= RSVD33

PADCTL_QSPI_QSPI1_IO2_0

Offset: 0x38

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_QSPI1_IO2_0

Reset: 0x00023458 (0bxxxx,xxxx,0000,xx1x,0011,x10x,x1x1,1000)

Bit Reset Description

23:20 0x0

RFU_IN

17 IORESET IO_RESET:

= NORMAL0

= IORESET1

15 DISABLE E_PREEMP:

= DISABLE0

= ENABLE1

14:13 COMP_DRIVE_2X

DRV_TYPE:

DRV_TYPE[0]:

0 = 1X driver;

1 = 2X driver;

DRV_TYPE[1]:

0 = Driving codes from BDSDMEMCOMP;

1 = Default driving codes;

= COMP_DRIVE_1X0

= COMP_DRIVE_2X1

= DEFAULT_DRIVE_1X2

= DEFAULT_DRIVE_2X3

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Bit Reset Description

12 ENABLE E_SCHMT:

= DISABLE0

= ENABLE1

10 SFIO

GPIO_SF_SEL:

= GPIO0

= SFIO1

9 DISABLE

E_HSM:

= DISABLE0

= ENABLE1

6 ENABLE E_INPUT:

= DISABLE0

= ENABLE1

4 TRISTATE TRISTATE:

= PASSTHROUGH0

= TRISTATE1

3:2 PULL_UP PUPD:

= NONE0

= PULL_DOWN1

= PULL_UP2

= RSVD3

1:0 QSPI1 PM:

= QSPI10

= RSVD11

= RSVD22

= RSVD33

PADCTL_QSPI_QSPI1_IO1_0

Offset: 0x40

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_QSPI1_IO1_0

Reset: 0x00023458 (0bxxxx,xxxx,0000,xx1x,0011,x10x,x1x1,1000)

Bit Reset Description

23:20 0x0

RFU_IN

17 IORESET IO_RESET:

= NORMAL0

= IORESET1

DISABLE

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Bit Reset Description

E_PREEMP:

= DISABLE0

= ENABLE1

14:13 COMP_DRIVE_2X DRV_TYPE:

DRV_TYPE[0]:

0 = 1X driver;

1 = 2X driver;

DRV_TYPE[1]:

0 = Driving codes from BDSDMEMCOMP;

1 = Default driving codes;

= COMP_DRIVE_1X0

= COMP_DRIVE_2X1

= DEFAULT_DRIVE_1X2

= DEFAULT_DRIVE_2X3

12 ENABLE E_SCHMT:

= DISABLE0

= ENABLE1

10 SFIO GPIO_SF_SEL:

= GPIO0

= SFIO1

9 DISABLE E_HSM:

= DISABLE0

= ENABLE1

6 ENABLE

E_INPUT:

= DISABLE0

= ENABLE1

4 TRISTATE

TRISTATE:

= PASSTHROUGH0

= TRISTATE1

3:2 PULL_UP PUPD:

= NONE0

= PULL_DOWN1

= PULL_UP2

= RSVD3

1:0 QSPI1 PM:

= QSPI10

= RSVD11

= RSVD22

= RSVD33

PADCTL_QSPI_QSPI1_IO0_0

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Offset: 0x48

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_QSPI1_IO0_0

Reset: 0x00023458 (0bxxxx,xxxx,0000,xx1x,0011,x10x,x1x1,1000)

Bit Reset Description

23:20 0x0

RFU_IN

17 IORESET IO_RESET:

= NORMAL0

= IORESET1

15 DISABLE E_PREEMP:

= DISABLE0

= ENABLE1

14:13 COMP_DRIVE_2X

DRV_TYPE:

DRV_TYPE[0]:

0 = 1X driver;

1 = 2X driver;

DRV_TYPE[1]:

0 = Driving codes from BDSDMEMCOMP;

1 = Default driving codes;

= COMP_DRIVE_1X0

= COMP_DRIVE_2X1

= DEFAULT_DRIVE_1X2

= DEFAULT_DRIVE_2X3

12 ENABLE

E_SCHMT:

= DISABLE0

= ENABLE1

10 SFIO GPIO_SF_SEL:

= GPIO0

= SFIO1

9 DISABLE E_HSM:

= DISABLE0

= ENABLE1

6 ENABLE E_INPUT:

= DISABLE0

= ENABLE1

4 TRISTATE TRISTATE:

= PASSTHROUGH0

= TRISTATE1

3:2

PULL_UP

PUPD:

= NONE0

= PULL_DOWN1

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Bit Reset Description

= PULL_UP2

= RSVD3

1:0 QSPI1 PM:

= QSPI10

= RSVD11

= RSVD22

= RSVD33

PADCTL_QSPI_QSPI1_SCK_0

Offset: 0x50

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_QSPI1_SCK_0

Reset: 0x00023474 (0bxxxx,xxxx,0000,xx1x,0011,x10x,x111,0100)

Bit Reset Description

23:20 0x0

RFU_IN

17 IORESET IO_RESET:

= NORMAL0

= IORESET1

15 DISABLE E_PREEMP:

= DISABLE0

= ENABLE1

14:13 COMP_DRIVE_2X

DRV_TYPE:

DRV_TYPE[0]:

0 = 1X driver;

1 = 2X driver;

DRV_TYPE[1]:

0 = Driving codes from BDSDMEMCOMP;

1 = Default driving codes;

= COMP_DRIVE_1X0

= COMP_DRIVE_2X1

= DEFAULT_DRIVE_1X2

= DEFAULT_DRIVE_2X3

12 ENABLE

E_SCHMT:

= DISABLE0

= ENABLE1

10 SFIO GPIO_SF_SEL:

= GPIO0

= SFIO1

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Bit Reset Description

9 DISABLE E_HSM:

= DISABLE0

= ENABLE1

6 ENABLE

E_INPUT:

= DISABLE0

= ENABLE1

5 ENABLE

E_LPBK:

= DISABLE0

= ENABLE1

4 TRISTATE TRISTATE:

= PASSTHROUGH0

= TRISTATE1

3:2 PULL_DOWN PUPD:

= NONE0

= PULL_DOWN1

= PULL_UP2

= RSVD3

1:0 QSPI1 PM:

= QSPI10

= RSVD11

= RSVD22

= RSVD33

PADCTL_QSPI_QSPI1_CS_N_0

Offset: 0x58

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_QSPI1_CS_N_0

Reset: 0x00023418 (0bxxxx,xxxx,0000,xx1x,0011,x10x,x0x1,1000)

Bit Reset Description

23:20 0x0 RFU_IN

17 IORESET IO_RESET:

= NORMAL0

= IORESET1

15 DISABLE E_PREEMP:

= DISABLE0

= ENABLE1

14:13

COMP_DRIVE_2X

DRV_TYPE:

DRV_TYPE[0]:

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Bit Reset Description

0 = 1X driver;

1 = 2X driver;

DRV_TYPE[1]:

0 = Driving codes from BDSDMEMCOMP;

1 = Default driving codes;

= COMP_DRIVE_1X0

= COMP_DRIVE_2X1

= DEFAULT_DRIVE_1X2

= DEFAULT_DRIVE_2X3

12 ENABLE E_SCHMT:

= DISABLE0

= ENABLE1

10 SFIO GPIO_SF_SEL:

= GPIO0

= SFIO1

9 DISABLE E_HSM:

= DISABLE0

= ENABLE1

6 DISABLE

E_INPUT:

= DISABLE0

= ENABLE1

4 TRISTATE

TRISTATE:

= PASSTHROUGH0

= TRISTATE1

3:2 PULL_UP PUPD:

= NONE0

= PULL_DOWN1

= PULL_UP2

= RSVD3

1:0 QSPI1 PM:

= QSPI10

= RSVD11

= RSVD22

= RSVD33

PADCTL_QSPI_QSPI_COMP_0

Offset: 0x60

Read/Write: RW

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Parity Protection: N

SCR Protection: SCR_QSPI_COMP_0

Reset: 0x00002000 (0bxxxx,xxxx,0000,xxxx,x01x,xxxx,xxx0,xx00)

Bit Reset Description

23:20 0x0 RFU_IN

14:13 COMP_DRIVE_2X DRV_TYPE:

DRV_TYPE[0]:

0 = 1X driver;

1 = 2X driver;

DRV_TYPE[1]:

0 = Driving codes from BDSDMEMCOMP;

1 = Default driving codes;

= COMP_DRIVE_1X0

= COMP_DRIVE_2X1

= DEFAULT_DRIVE_1X2

= DEFAULT_DRIVE_2X3

4 PASSTHROUGH TRISTATE:

= PASSTHROUGH0

= TRISTATE1

1:0 QSPI PM:

= QSPI0

= RSVD11

= RSVD22

= RSVD33

SYS PAD Control Registers

PADCTL_SYS_SHUTDOWN_N_0

Offset: 0x0

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_SHUTDOWN_N_0

Reset: 0x00000020 (0bxxxx,xxxx,xxxx,xxxx,xxx0,xxx0,x010,0000)

Bit Reset Description

12 DISABLE

E_SCHMT:

= DISABLE0

= ENABLE1

DISABLE

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Bit Reset Description

E_LPDR:

= DISABLE0

= ENABLE1

6 DISABLE E_INPUT:

= DISABLE0

= ENABLE1

5 ENABLE E_IO_HV:

= DISABLE0

= ENABLE1

4 PASSTHROUGH TRISTATE:

= PASSTHROUGH0

= TRISTATE1

3:2 NONE

PUPD:

= NONE0

= PULL_DOWN1

= PULL_UP2

= RSVD3

1:0 SHUTDOWN PM:

= SHUTDOWN0

= RSVD11

= RSVD22

= ISTCTRL3

PADCTL_SYS_CFG2TMC_SHUTDOWN_N_0

Offset: 0x4

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_SHUTDOWN_N_0

Reset: 0x00000000 (0bxxxx,xxx0,0000,xxx0,0000,xxxx,xxxx,xxxx)

Bit Reset Description

24:20 0x0 CFG_CAL_DRVUP

16:12 0x0 CFG_CAL_DRVDN

PADCTL_SYS_PMU_INT_N_0

Offset: 0x8

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_PMU_INT_N_0

Reset: 0x00000040 (0bxxxx,xxxx,xxxx,xxxx,xxx0,xxx0,x1xx,00xx)

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Bit Reset Description

12 DISABLE E_SCHMT:

= DISABLE0

= ENABLE1

8 DISABLE E_LPDR:

= DISABLE0

= ENABLE1

6 ENABLE E_INPUT:

= DISABLE0

= ENABLE1

3:2 NONE PUPD:

= NONE0

= PULL_DOWN1

= PULL_UP2

= RSVD3

PADCTL_SYS_CFG2TMC_PMU_INT_N_0

Offset: 0xc

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_PMU_INT_N_0

Reset: 0x00000000 (0bxxxx,xxx0,0000,xxx0,0000,xxxx,xxxx,xxxx)

Bit Reset Description

24:20 0x0 CFG_CAL_DRVUP

16:12 0x0 CFG_CAL_DRVDN

PADCTL_SYS_SAFE_STATE_0

Offset: 0x10

Read/Write: RW

Parity Protection: Y

SCR Protection: SCR_SAFE_STATE_0

Reset: 0x00000470 (0bxxxx,xxxx,xxxx,xxxx,xxx0,x1x0,x111,0000)

Bit Reset Description

12 DISABLE E_SCHMT:

= DISABLE0

= ENABLE1

SFIO

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Bit Reset Description

GPIO_SF_SEL:

= GPIO0

= SFIO1

8 DISABLE E_LPDR:

= DISABLE0

= ENABLE1

6 ENABLE E_INPUT:

= DISABLE0

= ENABLE1

5 ENABLE E_IO_HV:

= DISABLE0

= ENABLE1

4 TRISTATE TRISTATE:

= PASSTHROUGH0

= TRISTATE1

3:2 NONE

PUPD:

= NONE0

= PULL_DOWN1

= PULL_UP2

= RSVD3

1:0 SCE PM:

= SCE0

= RSVD11

= RSVD22

= RSVD33

PADCTL_SYS_CFG2TMC_SAFE_STATE_0

Offset: 0x14

Read/Write: RW

Parity Protection: Y

SCR Protection: SCR_SAFE_STATE_0

Reset: 0x00000000 (0bxxxx,xxx0,0000,xxx0,0000,xxxx,xxxx,xxxx)

Bit Reset Description

24:20 0x0 CFG_CAL_DRVUP

16:12 0x0 CFG_CAL_DRVDN

PADCTL_SYS_VCOMP_ALERT_0

Offset: 0x18

Read/Write: RW

Parity Protection: N

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SCR Protection: SCR_VCOMP_ALERT_0

Reset: 0x00000454 (0bxxxx,xxxx,xxxx,xxxx,xxx0,x1x0,x1x1,0100)

Bit Reset Description

12 DISABLE E_SCHMT:

= DISABLE0

= ENABLE1

10 SFIO GPIO_SF_SEL:

= GPIO0

= SFIO1

8 DISABLE E_LPDR:

= DISABLE0

= ENABLE1

6 ENABLE E_INPUT:

= DISABLE0

= ENABLE1

4 TRISTATE

TRISTATE:

= PASSTHROUGH0

= TRISTATE1

3:2 PULL_DOWN

PUPD:

= NONE0

= PULL_DOWN1

= PULL_UP2

= RSVD3

1:0 SOC PM:

= SOC0

= RSVD11

= RSVD22

= RSVD33

PADCTL_SYS_CFG2TMC_VCOMP_ALERT_0

Offset: 0x1c

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_VCOMP_ALERT_0

Reset: 0x00000000 (0bxxxx,xxx0,0000,xxx0,0000,xxxx,xxxx,xxxx)

Bit Reset Description

24:20 0x0

CFG_CAL_DRVUP

16:12 0x0 CFG_CAL_DRVDN

PADCTL_SYS_SOC_PWR_REQ_0

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Offset: 0x20

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_SOC_PWR_REQ_0

Reset: 0x00000000 (0bxxxx,xxxx,xxxx,xxxx,xxx0,xxx0,x0xx,00xx)

Bit Reset Description

12 DISABLE E_SCHMT:

= DISABLE0

= ENABLE1

8 DISABLE E_LPDR:

= DISABLE0

= ENABLE1

6 DISABLE E_INPUT:

= DISABLE0

= ENABLE1

3:2 NONE PUPD:

= NONE0

= PULL_DOWN1

= PULL_UP2

= RSVD3

PADCTL_SYS_CFG2TMC_SOC_PWR_REQ_0

Offset: 0x24

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_SOC_PWR_REQ_0

Reset: 0x00000000 (0bxxxx,xxx0,0000,xxx0,0000,xxxx,xxxx,xxxx)

Bit Reset Description

24:20 0x0

CFG_CAL_DRVUP

16:12 0x0

CFG_CAL_DRVDN

PADCTL_SYS_BATT_OC_0

Offset: 0x28

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_BATT_OC_0

Reset: 0x00001454 (0bxxxx,xxxx,xxxx,xxxx,xxx1,x1x0,x1x1,0100)

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Bit Reset Description

12 ENABLE E_SCHMT:

= DISABLE0

= ENABLE1

10 SFIO

GPIO_SF_SEL:

= GPIO0

= SFIO1

8 DISABLE

E_LPDR:

= DISABLE0

= ENABLE1

6 ENABLE E_INPUT:

= DISABLE0

= ENABLE1

4 TRISTATE TRISTATE:

= PASSTHROUGH0

= TRISTATE1

3:2 PULL_DOWN PUPD:

= NONE0

= PULL_DOWN1

= PULL_UP2

= RSVD3

1:0 SOC PM:

= SOC0

= RSVD11

= RSVD22

= RSVD33

PADCTL_SYS_CFG2TMC_BATT_OC_0

Offset: 0x2c

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_BATT_OC_0

Reset: 0x00000000 (0bxxxx,xxx0,0000,xxx0,0000,xxxx,xxxx,xxxx)

Bit Reset Description

24:20 0x0 CFG_CAL_DRVUP

16:12 0x0 CFG_CAL_DRVDN

PADCTL_SYS_CLK_32K_IN_0

Offset: 0x30

Read/Write: RW

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Parity Protection: N

SCR Protection: SCR_CLK_32K_IN_0

Reset: 0x00001000 (0bxxxx,xxxx,xxxx,xxxx,xxx1,xxx0,xxxx,00xx)

Bit Reset Description

12 ENABLE

E_SCHMT:

= DISABLE0

= ENABLE1

8 DISABLE

E_LPDR:

= DISABLE0

= ENABLE1

3:2 NONE PUPD:

= NONE0

= PULL_DOWN1

= PULL_UP2

= RSVD3

PADCTL_SYS_CFG2TMC_CLK_32K_IN_0

Offset: 0x34

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_CLK_32K_IN_0

Reset: 0x00000000 (0bxxxx,xxx0,0000,xxx0,0000,xxxx,xxxx,xxxx)

Bit Reset Description

24:20 0x0 CFG_CAL_DRVUP

16:12 0x0 CFG_CAL_DRVDN

PADCTL_SYS_POWER_ON_0

Offset: 0x38

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_POWER_ON_0

Reset: 0x00000454 (0bxxxx,xxxx,xxxx,xxxx,xxx0,x1x0,x1x1,0100)

Bit Reset Description

12 DISABLE E_SCHMT:

= DISABLE0

= ENABLE1

10 SFIO GPIO_SF_SEL:

= GPIO0

= SFIO1

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Bit Reset Description

8 DISABLE

E_LPDR:

= DISABLE0

= ENABLE1

6 ENABLE

E_INPUT:

= DISABLE0

= ENABLE1

4 TRISTATE

TRISTATE:

= PASSTHROUGH0

= TRISTATE1

3:2 PULL_DOWN

PUPD:

= NONE0

= PULL_DOWN1

= PULL_UP2

= RSVD3

1:0 RSVD0 PM:

= RSVD00

= RSVD11

= RSVD22

= RSVD33

PADCTL_SYS_CFG2TMC_POWER_ON_0

Offset: 0x3c

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_POWER_ON_0

Reset: 0x00000000 (0bxxxx,xxx0,0000,xxx0,0000,xxxx,xxxx,xxxx)

Bit Reset Description

24:20 0x0

CFG_CAL_DRVUP

16:12 0x0

CFG_CAL_DRVDN

PADCTL_SYS_PWR_I2C_SCL_0

Offset: 0x40

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_PWR_I2C_SCL_0

Reset: 0x00001550 (0bxxxx,xxxx,xxxx,xxxx,xxx1,x1x1,x101,0000)

Bit Reset Description

ENABLE

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Bit Reset Description

E_SCHMT:

= DISABLE0

= ENABLE1

10 SFIO GPIO_SF_SEL:

= GPIO0

= SFIO1

8 ENABLE E_LPDR:

= DISABLE0

= ENABLE1

6 ENABLE E_INPUT:

= DISABLE0

= ENABLE1

5 DISABLE

E_IO_HV:

= DISABLE0

= ENABLE1

4 TRISTATE

TRISTATE:

= PASSTHROUGH0

= TRISTATE1

3:2 NONE

PUPD:

= NONE0

= PULL_DOWN1

= PULL_UP2

= RSVD3

1:0 I2C5 PM:

= I2C50

= RSVD11

= RSVD22

= RSVD33

PADCTL_SYS_CFG2TMC_PWR_I2C_SCL_0

Offset: 0x44

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_PWR_I2C_SCL_0

Reset: 0x00000000 (0bxxxx,xxx0,0000,xxx0,0000,xxxx,xxxx,xxxx)

Bit Reset Description

24:20 0x0 CFG_CAL_DRVUP

16:12 0x0 CFG_CAL_DRVDN

PADCTL_SYS_PWR_I2C_SDA_0

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Offset: 0x48

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_PWR_I2C_SDA_0

Reset: 0x00001550 (0bxxxx,xxxx,xxxx,xxxx,xxx1,x1x1,x101,0000)

Bit Reset Description

12 ENABLE E_SCHMT:

= DISABLE0

= ENABLE1

10 SFIO

GPIO_SF_SEL:

= GPIO0

= SFIO1

8 ENABLE

E_LPDR:

= DISABLE0

= ENABLE1

6 ENABLE E_INPUT:

= DISABLE0

= ENABLE1

5 DISABLE E_IO_HV:

= DISABLE0

= ENABLE1

4 TRISTATE TRISTATE:

= PASSTHROUGH0

= TRISTATE1

3:2 NONE PUPD:

= NONE0

= PULL_DOWN1

= PULL_UP2

= RSVD3

1:0 I2C5

PM:

= I2C50

= RSVD11

= RSVD22

= RSVD33

PADCTL_SYS_CFG2TMC_PWR_I2C_SDA_0

Offset: 0x4c

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_PWR_I2C_SDA_0

Reset: 0x00000000 (0bxxxx,xxx0,0000,xxx0,0000,xxxx,xxxx,xxxx)

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Bit Reset Description

24:20 0x0 CFG_CAL_DRVUP

16:12 0x0 CFG_CAL_DRVDN

reg GEN1_I2C_SCL not used

reg CFG2TMC_GEN1_I2C_SCL not used

reg GEN1_I2C_SDA not used

reg CFG2TMC_GEN1_I2C_SDA not used

PADCTL_SYS_AO_RETENTION_N_0

Offset: 0x60

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_AO_RETENTION_N_0

Reset: 0x00000470 (0bxxxx,xxxx,xxxx,xxxx,xxx0,x1x0,x111,0000)

Bit Reset Description

12 DISABLE

E_SCHMT:

= DISABLE0

= ENABLE1

10 SFIO

GPIO_SF_SEL:

= GPIO0

= SFIO1

8 DISABLE E_LPDR:

= DISABLE0

= ENABLE1

6 ENABLE E_INPUT:

= DISABLE0

= ENABLE1

5 ENABLE E_IO_HV:

= DISABLE0

= ENABLE1

4 TRISTATE TRISTATE:

= PASSTHROUGH0

= TRISTATE1

3:2 NONE PUPD:

= NONE0

= PULL_DOWN1

= PULL_UP2

= RSVD3

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Bit Reset Description

1:0 GPIO

PM:

= GPIO0

= RSVD11

= RSVD22

= RSVD33

PADCTL_SYS_CFG2TMC_AO_RETENTION_N_0

Offset: 0x64

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_AO_RETENTION_N_0

Reset: 0x00000000 (0bxxxx,xxx0,0000,xxx0,0000,xxxx,xxxx,xxxx)

Bit Reset Description

24:20 0x0 CFG_CAL_DRVUP

16:12 0x0

CFG_CAL_DRVDN

PADCTL_SYS_EC_FEATURE_0

==================================

GLOBAL SLICE

==================================

Offset: 0x400

Read/Write: RO

Parity Protection: N

SCR Protection: EC_SCR_0

Reset: 0x00020001 (0b0000,0000,0000,0010,xxxx,xxxx,xx00,0001)

Bit Reset Description

31:16 0x2 NUM_ERR:

Number of errors connected to this collator. This is passed as a build time option to the plugin

5:0 0x1 NUM_ERR_SLICES:

Number of error slices supported by this error collator, does not include the GlobalSpace and is

derived by ceil (NUM_ERR/32). SW shall first read this register to determine the number of slices

and read the required number of Error_Status registers .

PADCTL_SYS_EC_SWRESET_0

Offset: 0x404

Read/Write: WO

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Parity Protection: N

SCR Protection: EC_SCR_0

Reset: 0x00000000 (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxx0)

Bit Reset Description

0 0x0

SWRST:

1'b1 : Issue a SW reset to the Error Collator. This will reset all the registers(Except SCR), counters

and logic of the Error Collator. SW can use this bit to flush errors logged into the error collator

for ex, after Boot, SC7/8 exit.

1'b0 : Do nothing, reset value.

This bit is auto-cleared.

PADCTL_SYS_EC_MISSIONERR_TYPE_0

Offset: 0x408

Read/Write: RO

Parity Protection: N

SCR Protection: EC_SCR_0

Reset: 0x00000005 (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xx00,0101)

Bit Reset Description

5:0 0x5

CODE:

This register indicates the fault code of the error line based on the value of MISSIONERR_INDEX Register.

This can be used by a fault handling agent to triage an error without requiring device-specific code.The

possible values of this field are:

6'd0 : None

6'd1 : Parity Error on internal data path

6'd2 : ECC SEC Error on internal data path

6'd3 : ECC DED Error on internal data path

6'd4 : Comparator Error

6'd5 : Register Parity Error

6'd6 : Parity Error from on-chip SRAM/Fifo

6'd7 : ECC SEC Error from on-chip SRAM/Fifo

6'd8 : ECC DED Error from on-chip SRAM/Fifo

6'd9 : Clock Monitor Error

6'd10 : Voltage Error

6'd11 : Temperature Error

6'd16 : SW Correctable Error

6'd17 : SW Un-Correctable Error

6'd32 : Other HW Correctable Error

6'd33 : Other HW Uncorrectable Error

All other values : Reserved for future use.

PADCTL_SYS_EC_CURRENT_COUNTER_VALUE_0

Offset: 0x40c

Read/Write: RO

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Parity Protection: N

SCR Protection: EC_SCR_0

Reset: 0x00000000 (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxx0,0000,0000)

Bit Reset Description

8:0 0x0 VALUE:

Provides the current value of the counter corresponding to the error in MissionErr_Index Register.

Default provides the value of error 0 counter.

Bit[8] is the ovrerflow bit post which the counter saturates and does not counter further.

PADCTL_SYS_EC_MISSIONERR_INDEX_0

Offset: 0x414

Read/Write: RW

Parity Protection: Y

SCR Protection: EC_SCR_0

Reset: 0x00000000 (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xx00)

Bit Reset Description

1:0 0x0 IDX:

BINARY Encoded. For error number 32, register should be programmed with value 0x20.

Write to this register with Error number will update:

- MISSIONERR_TYPE Register with the Error-Code for the Error.

- CURRENT_COUNTER_VALUE Register with the error's SEC/DED Counter.

- MISSIONERR_USERVALUE with value of the first error_<i>_user signal.

SW can use this to trage the error.

number shall update the MISSIONERR_TYPE register with the error code and the Current_Counter_Value

with the value of the errors SEC/DED counter. SW can use this register to triage the error.

PADCTL_SYS_EC_CORRECTABLE_THRESHOLD_0

Offset: 0x418

Read/Write: RW

Parity Protection: Y

SCR Protection: EC_SCR_0

Reset: 0x000000ff (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,1111,1111)

Bit Reset Description

7:0

0xff

COUNT:

Threshold value for all SEC Fault Reporting Units connected to this error collator.

SEC Errors are logged once the threshold is reached and the overflow bit is set.

7'b0 : Log SEC error after receiving 1 Error.

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Bit Reset Description

7'b1 : Log SEC error after receiving 2 Errors.

...

7'bFF : Log SEC error after receiving 256 Errors.

PADCTL_SYS_EC_MISSIONERR_INJECT_UNLOCK_0

Offset: 0x41c

Read/Write: RW

Parity Protection: N

SCR Protection: EC_SCR_0

Reset: 0x00000000 (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,0000,0000)

Bit Reset Description

7:0 0x0 VALUE:

Writes to ERRSLICE_XXX_MISSIONERR_INJECT registers are disabled until this register is written with a

value of 0xE1.

This is to prevent an inadvertent safety error injection in the safety plugin due to:

1. A fault on ERRSLICE_XXX_MISSIONERR_INJECT register itself.

2. Erroneous SW.

The register shall be written with a value of 0x0 to reestablish the lock after user has completed the error

injection testing.

0xE1 : Unlock the MISSIONERR_INJECT Register

0x0 : Lock the MISSIONERR_INJECT Register

= LOCK0

= UNLOCK225

PADCTL_SYS_EC_ERRSLICE0_MISSIONERR_ENABLE_0

==================================

ERROR SLICE - 0

==================================

Offset: 0x430

Read/Write: RW

Parity Protection: Y

SCR Protection: EC_SCR_0

Reset: 0x00000007 (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,x111)

Bit Reset Description

0x1

ERR2:

1'b1 -> Enable Mission Error Reporting for Register Parity Error from PADCTL.SYS.SCR.SAFE_STATE

1'b0 -> Disable Mission Error Reporting for Register Parity Error from PADCTL.SYS.SCR.SAFE_STATE

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Bit Reset Description

= DISABLE0

= ENABLE1

1 0x1 ERR1:

1'b1 -> Enable Mission Error Reporting for Register Parity Error from PADCTL.SYS.SAFE_STATE

1'b0 -> Disable Mission Error Reporting for Register Parity Error from PADCTL.SYS.SAFE_STATE

= DISABLE0

= ENABLE1

0 0x1 ERR0:

1'b1 -> Enable Mission Error Reporting for Register Parity Error from PADCTL_SYS_err_collator

1'b0 -> Disable Mission Error Reporting for Register Parity Error from PADCTL_SYS_err_collator

= DISABLE0

= ENABLE1

PADCTL_SYS_EC_ERRSLICE0_MISSIONERR_FORCE_0

Offset: 0x434

Read/Write: WO

Parity Protection: N

SCR Protection: EC_SCR_0

Reset: 0x00000000 (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,x000)

Bit Reset Description

2 0x0

ERR2:

1'b1 -> Force Assertion of Mission Error Reporting for Register Parity Error from PADCTL.SYS.SCR.

SAFE_STATE

1'b0 -> Do Nothing

= NOFORCE0

= FORCE1

1 0x0

ERR1:

1'b1 -> Force Assertion of Mission Error Reporting for Register Parity Error from PADCTL.SYS.SAFE_STATE

1'b0 -> Do Nothing

= NOFORCE0

= FORCE1

0 0x0

ERR0:

1'b1 -> Force Assertion of Mission Error Reporting for Register Parity Error from PADCTL_SYS_err_collator

1'b0 -> Do Nothing

= NOFORCE0

= FORCE1

PADCTL_SYS_EC_ERRSLICE0_MISSIONERR_STATUS_0

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SW must write 1 to clear the fields of this register.

Bits in this register continue to be logged independent of the value of MissionError_Enable register, to avoid

silent dropping of errors.

Offset: 0x438

Read/Write: RW

Parity Protection: Y

SCR Protection: EC_SCR_0

Reset: 0x00000000 (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,x000)

Bit Reset Description

2 0x0 ERR2:

1'b1 -> Error_2_pulse[1:0] for Register Parity Error from PADCTL.SYS.SCR.SAFE_STATE was equal to

2'b10.

1'b0 -> Error_2_pulse[1:0] for Register Parity Error from PADCTL.SYS.SCR.SAFE_STATE was equal to

2'b01.

1 0x0 ERR1:

1'b1 -> Error_1_pulse[1:0] for Register Parity Error from PADCTL.SYS.SAFE_STATE was equal to 2'b10.

1'b0 -> Error_1_pulse[1:0] for Register Parity Error from PADCTL.SYS.SAFE_STATE was equal to 2'b01.

0 0x0

ERR0:

1'b1 -> Error_0_pulse[1:0] for Register Parity Error from PADCTL_SYS_err_collator was equal to 2'b10.

1'b0 -> Error_0_pulse[1:0] for Register Parity Error from PADCTL_SYS_err_collator was equal to 2'b01.

PADCTL_SYS_EC_ERRSLICE0_MISSIONERR_INJECT_0

Offset: 0x43c

Read/Write: RW

Parity Protection: N

SCR Protection: EC_SCR_0

Reset: 0x00000000 (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,x000)

Bit Reset Description

2 0x0 ERR2:

1'b1 -> Assert the inject_error_2 output for Register Parity Error to PADCTL.SYS.SCR.SAFE_STATE to

allow for error injection.

1'b0 -> De-Asseert inject_error_2 output.

= DISABLE0

= ENABLE1

0x0

ERR1:

1'b1 -> Assert the inject_error_1 output for Register Parity Error to PADCTL.SYS.SAFE_STATE to allow for

error injection.

1'b0 -> De-Asseert inject_error_1 output.

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Bit Reset Description

= DISABLE0

= ENABLE1

0 0x0 ERR0:

1'b1 -> Assert the inject_error_0 output for Register Parity Error to PADCTL_SYS_err_collator to allow for

error injection.

1'b0 -> De-Asseert inject_error_0 output.

= DISABLE0

= ENABLE1

PADCTL_SYS_EC_ERRSLICE0_LATENTERR_ENABLE_0

Offset: 0x440

Read/Write: RW

Parity Protection: Y

SCR Protection: EC_SCR_0

Reset: 0x00000007 (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,x111)

Bit Reset Description

2 0x1 ERR2:

1'b1 -> Enable Latent Error Reporting for Register Parity Error from PADCTL.SYS.SCR.SAFE_STATE

1'b0 -> Disable Latent Error Reporting for Register Parity Error from PADCTL.SYS.SCR.SAFE_STATE

= DISABLE0

= ENABLE1

1 0x1 ERR1:

1'b1 -> Enable Latent Error Reporting for Register Parity Error from PADCTL.SYS.SAFE_STATE

1'b0 -> Disable Latent Error Reporting for Register Parity Error from PADCTL.SYS.SAFE_STATE

= DISABLE0

= ENABLE1

0 0x1 ERR0:

1'b1 -> Enable Latent Error Reporting for Register Parity Error from PADCTL_SYS_err_collator

1'b0 -> Disable Latent Error Reporting for Register Parity Error from PADCTL_SYS_err_collator

= DISABLE0

= ENABLE1

PADCTL_SYS_EC_ERRSLICE0_LATENTERR_FORCE_0

Offset: 0x444

Read/Write: WO

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Parity Protection: N

SCR Protection: EC_SCR_0

Reset: 0x00000000 (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,x000)

Bit Reset Description

2 0x0

ERR2:

1'b1 -> Force Assertion of Latent Error Reporting for Register Parity Error from PADCTL.SYS.SCR.

SAFE_STATE

1'b0 -> Do Nothing

= NOFORCE0

= FORCE1

1 0x0 ERR1:

1'b1 -> Force Assertion of Latent Error Reporting for Register Parity Error from PADCTL.SYS.SAFE_STATE

1'b0 -> Do Nothing

= NOFORCE0

= FORCE1

0 0x0

ERR0:

1'b1 -> Force Assertion of Latent Error Reporting for Register Parity Error from PADCTL_SYS_err_collator

1'b0 -> Do Nothing

= NOFORCE0

= FORCE1

PADCTL_SYS_EC_ERRSLICE0_LATENTERR_STATUS_0

SW must write 1 to clear the fields of this register.

Bits in this register continue to be logged independent of the value of LatentError_Enable register, to avoid

silent dropping of errors.

Offset: 0x448

Read/Write: RW

Parity Protection: Y

SCR Protection: EC_SCR_0

Reset: 0x00000000 (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,x000)

Bit Reset Description

2 0x0 ERR2:

1'b1 -> Error_2_pulse[1:0] for Register Parity Error from PADCTL.SYS.SCR.SAFE_STATE was equal to

2'b00 or 2'b11.

1'b0 -> Error_2_pulse[1:0] for Register Parity Error from PADCTL.SYS.SCR.SAFE_STATE was equal to

2'b01 or 2'b10, but no latent error.

0x0

ERR1:

1'b1 -> Error_1_pulse[1:0] for Register Parity Error from PADCTL.SYS.SAFE_STATE was equal to 2'b00 or

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Bit Reset Description

2'b11.

1'b0 -> Error_1_pulse[1:0] for Register Parity Error from PADCTL.SYS.SAFE_STATE was equal to 2'b01 or

2'b10, but no latent error.

0 0x0

ERR0:

1'b1 -> Error_0_pulse[1:0] for Register Parity Error from PADCTL_SYS_err_collator was equal to 2'b00 or

2'b11.

1'b0 -> Error_0_pulse[1:0] for Register Parity Error from PADCTL_SYS_err_collator was equal to 2'b01 or

2'b10, but no latent error.

PADCTL_SYS_EC_ERRSLICE0_COUNTER_RELOAD_0

Offset: 0x450

Read/Write: WO

Parity Protection: N

SCR Protection: EC_SCR_0

Reset: 0x00000000 (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,x000)

Bit Reset Description

2 0x0 ERR2:

1'b1 -> Reload Error Counter for Register Parity Error from PADCTL.SYS.SCR.SAFE_STATE

1'b0 -> Do Nothing

= NORELOAD0

= RELOAD1

1 0x0 ERR1:

1'b1 -> Reload Error Counter for Register Parity Error from PADCTL.SYS.SAFE_STATE

1'b0 -> Do Nothing

= NORELOAD0

= RELOAD1

0 0x0 ERR0:

1'b1 -> Reload Error Counter for Register Parity Error from PADCTL_SYS_err_collator

1'b0 -> Do Nothing

= NORELOAD0

= RELOAD1

UART PAD Control Registers

PADCTL_UART_GPU_PWR_REQ_0

Offset: 0x0

Read/Write: RW

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Parity Protection: N

SCR Protection: SCR_GPU_PWR_REQ_0

Reset: 0x00000400 (0bxxxx,xxxx,xxxx,xxxx,xxx0,x1x0,x0x0,0000)

Bit Reset Description

12 DISABLE

E_SCHMT:

= DISABLE0

= ENABLE1

10 SFIO GPIO_SF_SEL:

= GPIO0

= SFIO1

8 DISABLE E_LPDR:

= DISABLE0

= ENABLE1

6 DISABLE E_INPUT:

= DISABLE0

= ENABLE1

4 PASSTHROUGH TRISTATE:

= PASSTHROUGH0

= TRISTATE1

3:2 NONE PUPD:

= NONE0

= PULL_DOWN1

= PULL_UP2

= RSVD3

1:0 RSVD0

PM:

= RSVD00

= RSVD11

= RSVD22

= RSVD33

PADCTL_UART_CFG2TMC_GPU_PWR_REQ_0

Offset: 0x4

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_GPU_PWR_REQ_0

Reset: 0x00000000 (0bxxxx,xxx0,0000,xxx0,0000,xxxx,xxxx,xxxx)

Bit Reset Description

24:20 0x0 CFG_CAL_DRVUP

16:12 0x0 CFG_CAL_DRVDN

PADCTL_UART_SPI3_MISO_0

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Offset: 0x8

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_SPI3_MISO_0

Reset: 0x00000474 (0bxxxx,xxxx,xxxx,xxxx,xxx0,x1x0,x111,0100)

Bit Reset Description

12 DISABLE

E_SCHMT:

= DISABLE0

= ENABLE1

10 SFIO GPIO_SF_SEL:

= GPIO0

= SFIO1

8 DISABLE E_LPDR:

= DISABLE0

= ENABLE1

6 ENABLE E_INPUT:

= DISABLE0

= ENABLE1

5 ENABLE E_IO_HV:

= DISABLE0

= ENABLE1

4 TRISTATE TRISTATE:

= PASSTHROUGH0

= TRISTATE1

3:2 PULL_DOWN

PUPD:

= NONE0

= PULL_DOWN1

= PULL_UP2

= RSVD3

1:0 SPI3 PM:

= SPI30

= RSVD11

= RSVD22

= RSVD33

PADCTL_UART_CFG2TMC_SPI3_MISO_0

Offset: 0xc

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_SPI3_MISO_0

Reset: 0x00000000 (0bxxxx,xxx0,0000,xxx0,0000,xxxx,xxxx,xxxx)

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Bit Reset Description

24:20 0x0

CFG_CAL_DRVUP

16:12 0x0

CFG_CAL_DRVDN

PADCTL_UART_SPI1_CS0_0

Offset: 0x10

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_SPI1_CS0_0

Reset: 0x00000458 (0bxxxx,xxxx,xxxx,xxxx,xxx0,x1x0,x1x1,1000)

Bit Reset Description

12 DISABLE

E_SCHMT:

= DISABLE0

= ENABLE1

10 SFIO GPIO_SF_SEL:

= GPIO0

= SFIO1

8 DISABLE E_LPDR:

= DISABLE0

= ENABLE1

6 ENABLE E_INPUT:

= DISABLE0

= ENABLE1

4 TRISTATE TRISTATE:

= PASSTHROUGH0

= TRISTATE1

3:2 PULL_UP PUPD:

= NONE0

= PULL_DOWN1

= PULL_UP2

= RSVD3

1:0 SPI1

PM:

= SPI10

= RSVD11

= RSVD22

= RSVD33

PADCTL_UART_CFG2TMC_SPI1_CS0_0

Offset: 0x14

Read/Write: RW

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Parity Protection: N

SCR Protection: SCR_SPI1_CS0_0

Reset: 0x00000000 (0bxxxx,xxx0,0000,xxx0,0000,xxxx,xxxx,xxxx)

Bit Reset Description

24:20 0x0 CFG_CAL_DRVUP

16:12 0x0 CFG_CAL_DRVDN

PADCTL_UART_SPI3_CS0_0

Offset: 0x18

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_SPI3_CS0_0

Reset: 0x00000470 (0bxxxx,xxxx,xxxx,xxxx,xxx0,x1x0,x111,0000)

Bit Reset Description

12 DISABLE E_SCHMT:

= DISABLE0

= ENABLE1

10 SFIO GPIO_SF_SEL:

= GPIO0

= SFIO1

8 DISABLE E_LPDR:

= DISABLE0

= ENABLE1

6 ENABLE E_INPUT:

= DISABLE0

= ENABLE1

5 ENABLE

E_IO_HV:

= DISABLE0

= ENABLE1

4 TRISTATE

TRISTATE:

= PASSTHROUGH0

= TRISTATE1

3:2 NONE

PUPD:

= NONE0

= PULL_DOWN1

= PULL_UP2

= RSVD3

1:0

SPI3

PM:

= SPI30

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Bit Reset Description

= RSVD11

= RSVD22

= RSVD33

PADCTL_UART_CFG2TMC_SPI3_CS0_0

Offset: 0x1c

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_SPI3_CS0_0

Reset: 0x00000000 (0bxxxx,xxx0,0000,xxx0,0000,xxxx,xxxx,xxxx)

Bit Reset Description

24:20 0x0 CFG_CAL_DRVUP

16:12 0x0 CFG_CAL_DRVDN

PADCTL_UART_SPI1_MISO_0

Offset: 0x20

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_SPI1_MISO_0

Reset: 0x00000458 (0bxxxx,xxxx,xxxx,xxxx,xxx0,x1x0,x1x1,1000)

Bit Reset Description

12 DISABLE E_SCHMT:

= DISABLE0

= ENABLE1

10 SFIO GPIO_SF_SEL:

= GPIO0

= SFIO1

8 DISABLE E_LPDR:

= DISABLE0

= ENABLE1

6 ENABLE E_INPUT:

= DISABLE0

= ENABLE1

4 TRISTATE TRISTATE:

= PASSTHROUGH0

= TRISTATE1

3:2

PULL_UP

PUPD:

= NONE0

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Bit Reset Description

= PULL_DOWN1

= PULL_UP2

= RSVD3

1:0 SPI1

PM:

= SPI10

= RSVD11

= RSVD22

= RSVD33

PADCTL_UART_CFG2TMC_SPI1_MISO_0

Offset: 0x24

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_SPI1_MISO_0

Reset: 0x00000000 (0bxxxx,xxx0,0000,xxx0,0000,xxxx,xxxx,xxxx)

Bit Reset Description

24:20 0x0 CFG_CAL_DRVUP

16:12 0x0 CFG_CAL_DRVDN

PADCTL_UART_SPI3_CS1_0

Offset: 0x28

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_SPI3_CS1_0

Reset: 0x00000470 (0bxxxx,xxxx,xxxx,xxxx,xxx0,x1x0,x111,0000)

Bit Reset Description

12 DISABLE

E_SCHMT:

= DISABLE0

= ENABLE1

10 SFIO

GPIO_SF_SEL:

= GPIO0

= SFIO1

8 DISABLE E_LPDR:

= DISABLE0

= ENABLE1

6 ENABLE E_INPUT:

= DISABLE0

= ENABLE1

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Bit Reset Description

5 ENABLE E_IO_HV:

= DISABLE0

= ENABLE1

4 TRISTATE TRISTATE:

= PASSTHROUGH0

= TRISTATE1

3:2 NONE PUPD:

= NONE0

= PULL_DOWN1

= PULL_UP2

= RSVD3

1:0 SPI3

PM:

= SPI30

= RSVD11

= RSVD22

= RSVD33

PADCTL_UART_CFG2TMC_SPI3_CS1_0

Offset: 0x2c

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_SPI3_CS1_0

Reset: 0x00000000 (0bxxxx,xxx0,0000,xxx0,0000,xxxx,xxxx,xxxx)

Bit Reset Description

24:20 0x0 CFG_CAL_DRVUP

16:12 0x0

CFG_CAL_DRVDN

PADCTL_UART_GP_PWM3_0

Offset: 0x30

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_GP_PWM3_0

Reset: 0x00000410 (0bxxxx,xxxx,xxxx,xxxx,xxx0,x1x0,x0x1,0000)

Bit Reset Description

12 DISABLE

E_SCHMT:

= DISABLE0

= ENABLE1

SFIO

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Bit Reset Description

GPIO_SF_SEL:

= GPIO0

= SFIO1

8 DISABLE

E_LPDR:

= DISABLE0

= ENABLE1

6 DISABLE

E_INPUT:

= DISABLE0

= ENABLE1

4 TRISTATE

TRISTATE:

= PASSTHROUGH0

= TRISTATE1

3:2 NONE PUPD:

= NONE0

= PULL_DOWN1

= PULL_UP2

= RSVD3

1:0 GP PM:

= GP0

= RSVD11

= RSVD22

= RSVD33

PADCTL_UART_CFG2TMC_GP_PWM3_0

Offset: 0x34

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_GP_PWM3_0

Reset: 0x00000000 (0bxxxx,xxx0,0000,xxx0,0000,xxxx,xxxx,xxxx)

Bit Reset Description

24:20 0x0

CFG_CAL_DRVUP

16:12 0x0

CFG_CAL_DRVDN

PADCTL_UART_GP_PWM2_0

Offset: 0x38

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_GP_PWM2_0

Reset: 0x00000410 (0bxxxx,xxxx,xxxx,xxxx,xxx0,x1x0,x0x1,0000)

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Bit Reset Description

12 DISABLE

E_SCHMT:

= DISABLE0

= ENABLE1

10 SFIO

GPIO_SF_SEL:

= GPIO0

= SFIO1

8 DISABLE

E_LPDR:

= DISABLE0

= ENABLE1

6 DISABLE

E_INPUT:

= DISABLE0

= ENABLE1

4 TRISTATE TRISTATE:

= PASSTHROUGH0

= TRISTATE1

3:2 NONE PUPD:

= NONE0

= PULL_DOWN1

= PULL_UP2

= RSVD3

1:0 GP

PM:

= GP0

= RSVD11

= RSVD22

= RSVD33

PADCTL_UART_CFG2TMC_GP_PWM2_0

Offset: 0x3c

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_GP_PWM2_0

Reset: 0x00000000 (0bxxxx,xxx0,0000,xxx0,0000,xxxx,xxxx,xxxx)

Bit Reset Description

24:20 0x0 CFG_CAL_DRVUP

16:12 0x0 CFG_CAL_DRVDN

PADCTL_UART_SPI1_SCK_0

Offset: 0x40

Read/Write: RW

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Parity Protection: N

SCR Protection: SCR_SPI1_SCK_0

Reset: 0x00000454 (0bxxxx,xxxx,xxxx,xxxx,xxx0,x1x0,x1x1,0100)

Bit Reset Description

12 DISABLE E_SCHMT:

= DISABLE0

= ENABLE1

10 SFIO GPIO_SF_SEL:

= GPIO0

= SFIO1

8 DISABLE E_LPDR:

= DISABLE0

= ENABLE1

6 ENABLE

E_INPUT:

= DISABLE0

= ENABLE1

4 TRISTATE

TRISTATE:

= PASSTHROUGH0

= TRISTATE1

3:2 PULL_DOWN PUPD:

= NONE0

= PULL_DOWN1

= PULL_UP2

= RSVD3

1:0 SPI1 PM:

= SPI10

= RSVD11

= RSVD22

= RSVD33

PADCTL_UART_CFG2TMC_SPI1_SCK_0

Offset: 0x44

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_SPI1_SCK_0

Reset: 0x00000000 (0bxxxx,xxx0,0000,xxx0,0000,xxxx,xxxx,xxxx)

Bit Reset Description

24:20 0x0

CFG_CAL_DRVUP

16:12 0x0 CFG_CAL_DRVDN

PADCTL_UART_SPI3_SCK_0

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Offset: 0x48

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_SPI3_SCK_0

Reset: 0x00000474 (0bxxxx,xxxx,xxxx,xxxx,xxx0,x1x0,x111,0100)

Bit Reset Description

12 DISABLE E_SCHMT:

= DISABLE0

= ENABLE1

10 SFIO

GPIO_SF_SEL:

= GPIO0

= SFIO1

8 DISABLE

E_LPDR:

= DISABLE0

= ENABLE1

6 ENABLE

E_INPUT:

= DISABLE0

= ENABLE1

5 ENABLE

E_IO_HV:

= DISABLE0

= ENABLE1

4 TRISTATE TRISTATE:

= PASSTHROUGH0

= TRISTATE1

3:2 PULL_DOWN PUPD:

= NONE0

= PULL_DOWN1

= PULL_UP2

= RSVD3

1:0 SPI3

PM:

= SPI30

= RSVD11

= RSVD22

= RSVD33

PADCTL_UART_CFG2TMC_SPI3_SCK_0

Offset: 0x4c

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_SPI3_SCK_0

Reset: 0x00000000 (0bxxxx,xxx0,0000,xxx0,0000,xxxx,xxxx,xxxx)

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Bit Reset Description

24:20 0x0 CFG_CAL_DRVUP

16:12 0x0 CFG_CAL_DRVDN

PADCTL_UART_SPI1_CS1_0

Offset: 0x50

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_SPI1_CS1_0

Reset: 0x00000458 (0bxxxx,xxxx,xxxx,xxxx,xxx0,x1x0,x1x1,1000)

Bit Reset Description

12 DISABLE E_SCHMT:

= DISABLE0

= ENABLE1

10 SFIO GPIO_SF_SEL:

= GPIO0

= SFIO1

8 DISABLE E_LPDR:

= DISABLE0

= ENABLE1

6 ENABLE

E_INPUT:

= DISABLE0

= ENABLE1

4 TRISTATE

TRISTATE:

= PASSTHROUGH0

= TRISTATE1

3:2 PULL_UP PUPD:

= NONE0

= PULL_DOWN1

= PULL_UP2

= RSVD3

1:0 SPI1 PM:

= SPI10

= RSVD11

= RSVD22

= RSVD33

PADCTL_UART_CFG2TMC_SPI1_CS1_0

Offset: 0x54

Read/Write: RW

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Parity Protection: N

SCR Protection: SCR_SPI1_CS1_0

Reset: 0x00000000 (0bxxxx,xxx0,0000,xxx0,0000,xxxx,xxxx,xxxx)

Bit Reset Description

24:20 0x0

CFG_CAL_DRVUP

16:12 0x0

CFG_CAL_DRVDN

PADCTL_UART_SPI1_MOSI_0

Offset: 0x58

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_SPI1_MOSI_0

Reset: 0x00000458 (0bxxxx,xxxx,xxxx,xxxx,xxx0,x1x0,x1x1,1000)

Bit Reset Description

12 DISABLE E_SCHMT:

= DISABLE0

= ENABLE1

10 SFIO

GPIO_SF_SEL:

= GPIO0

= SFIO1

8 DISABLE

E_LPDR:

= DISABLE0

= ENABLE1

6 ENABLE E_INPUT:

= DISABLE0

= ENABLE1

4 TRISTATE TRISTATE:

= PASSTHROUGH0

= TRISTATE1

3:2 PULL_UP PUPD:

= NONE0

= PULL_DOWN1

= PULL_UP2

= RSVD3

1:0 SPI1 PM:

= SPI10

= RSVD11

= RSVD22

= RSVD33

PADCTL_UART_CFG2TMC_SPI1_MOSI_0

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Offset: 0x5c

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_SPI1_MOSI_0

Reset: 0x00000000 (0bxxxx,xxx0,0000,xxx0,0000,xxxx,xxxx,xxxx)

Bit Reset Description

24:20 0x0

CFG_CAL_DRVUP

16:12 0x0

CFG_CAL_DRVDN

PADCTL_UART_SPI3_MOSI_0

Offset: 0x60

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_SPI3_MOSI_0

Reset: 0x00000474 (0bxxxx,xxxx,xxxx,xxxx,xxx0,x1x0,x111,0100)

Bit Reset Description

12 DISABLE

E_SCHMT:

= DISABLE0

= ENABLE1

10 SFIO

GPIO_SF_SEL:

= GPIO0

= SFIO1

8 DISABLE

E_LPDR:

= DISABLE0

= ENABLE1

6 ENABLE E_INPUT:

= DISABLE0

= ENABLE1

5 ENABLE E_IO_HV:

= DISABLE0

= ENABLE1

4 TRISTATE TRISTATE:

= PASSTHROUGH0

= TRISTATE1

3:2 PULL_DOWN PUPD:

= NONE0

= PULL_DOWN1

= PULL_UP2

= RSVD3

1:0

SPI3

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Bit Reset Description

PM:

= SPI30

= RSVD11

= RSVD22

= RSVD33

PADCTL_UART_CFG2TMC_SPI3_MOSI_0

Offset: 0x64

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_SPI3_MOSI_0

Reset: 0x00000000 (0bxxxx,xxx0,0000,xxx0,0000,xxxx,xxxx,xxxx)

Bit Reset Description

24:20 0x0 CFG_CAL_DRVUP

16:12 0x0 CFG_CAL_DRVDN

PADCTL_UART_CV_PWR_REQ_0

Offset: 0x68

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_CV_PWR_REQ_0

Reset: 0x00000400 (0bxxxx,xxxx,xxxx,xxxx,xxx0,x1x0,x0x0,0000)

Bit Reset Description

12 DISABLE E_SCHMT:

= DISABLE0

= ENABLE1

10 SFIO GPIO_SF_SEL:

= GPIO0

= SFIO1

8 DISABLE E_LPDR:

= DISABLE0

= ENABLE1

6 DISABLE

E_INPUT:

= DISABLE0

= ENABLE1

4 PASSTHROUGH

TRISTATE:

= PASSTHROUGH0

= TRISTATE1

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Bit Reset Description

3:2 NONE

PUPD:

= NONE0

= PULL_DOWN1

= PULL_UP2

= RSVD3

1:0 RSVD0 PM:

= RSVD00

= RSVD11

= RSVD22

= RSVD33

PADCTL_UART_CFG2TMC_CV_PWR_REQ_0

Offset: 0x6c

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_CV_PWR_REQ_0

Reset: 0x00000000 (0bxxxx,xxx0,0000,xxx0,0000,xxxx,xxxx,xxxx)

Bit Reset Description

24:20 0x0 CFG_CAL_DRVUP

16:12 0x0 CFG_CAL_DRVDN

PADCTL_UART_UART2_TX_0

Offset: 0x70

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_UART2_TX_0

Reset: 0x00000434 (0bxxxx,xxxx,xxxx,xxxx,xxx0,x1x0,x011,0100)

Bit Reset Description

12 DISABLE E_SCHMT:

= DISABLE0

= ENABLE1

10 SFIO GPIO_SF_SEL:

= GPIO0

= SFIO1

8 DISABLE E_LPDR:

= DISABLE0

= ENABLE1

DISABLE

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Bit Reset Description

E_INPUT:

= DISABLE0

= ENABLE1

5 ENABLE E_IO_HV:

= DISABLE0

= ENABLE1

4 TRISTATE TRISTATE:

= PASSTHROUGH0

= TRISTATE1

3:2 PULL_DOWN PUPD:

= NONE0

= PULL_DOWN1

= PULL_UP2

= RSVD3

1:0 UARTB

PM:

= UARTB0

= RSVD11

= RSVD22

= RSVD33

PADCTL_UART_CFG2TMC_UART2_TX_0

Offset: 0x74

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_UART2_TX_0

Reset: 0x00000000 (0bxxxx,xxx0,0000,xxx0,0000,xxxx,xxxx,xxxx)

Bit Reset Description

24:20 0x0 CFG_CAL_DRVUP

16:12 0x0 CFG_CAL_DRVDN

PADCTL_UART_UART2_RX_0

Offset: 0x78

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_UART2_RX_0

Reset: 0x00000474 (0bxxxx,xxxx,xxxx,xxxx,xxx0,x1x0,x111,0100)

Bit Reset Description

DISABLE

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Bit Reset Description

E_SCHMT:

= DISABLE0

= ENABLE1

10 SFIO

GPIO_SF_SEL:

= GPIO0

= SFIO1

8 DISABLE

E_LPDR:

= DISABLE0

= ENABLE1

6 ENABLE E_INPUT:

= DISABLE0

= ENABLE1

5 ENABLE E_IO_HV:

= DISABLE0

= ENABLE1

4 TRISTATE TRISTATE:

= PASSTHROUGH0

= TRISTATE1

3:2 PULL_DOWN PUPD:

= NONE0

= PULL_DOWN1

= PULL_UP2

= RSVD3

1:0 UARTB

PM:

= UARTB0

= RSVD11

= RSVD22

= RSVD33

PADCTL_UART_CFG2TMC_UART2_RX_0

Offset: 0x7c

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_UART2_RX_0

Reset: 0x00000000 (0bxxxx,xxx0,0000,xxx0,0000,xxxx,xxxx,xxxx)

Bit Reset Description

24:20 0x0 CFG_CAL_DRVUP

16:12 0x0 CFG_CAL_DRVDN

PADCTL_UART_UART2_RTS_0

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Offset: 0x80

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_UART2_RTS_0

Reset: 0x00000414 (0bxxxx,xxxx,xxxx,xxxx,xxx0,x1x0,x0x1,0100)

Bit Reset Description

12 DISABLE E_SCHMT:

= DISABLE0

= ENABLE1

10 SFIO GPIO_SF_SEL:

= GPIO0

= SFIO1

8 DISABLE E_LPDR:

= DISABLE0

= ENABLE1

6 DISABLE E_INPUT:

= DISABLE0

= ENABLE1

4 TRISTATE TRISTATE:

= PASSTHROUGH0

= TRISTATE1

3:2 PULL_DOWN

PUPD:

= NONE0

= PULL_DOWN1

= PULL_UP2

= RSVD3

1:0 UARTB PM:

= UARTB0

= RSVD11

= RSVD22

= RSVD33

PADCTL_UART_CFG2TMC_UART2_RTS_0

Offset: 0x84

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_UART2_RTS_0

Reset: 0x00000000 (0bxxxx,xxx0,0000,xxx0,0000,xxxx,xxxx,xxxx)

Bit Reset Description

24:20 0x0 CFG_CAL_DRVUP

16:12 0x0 CFG_CAL_DRVDN

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PADCTL_UART_UART2_CTS_0

Offset: 0x88

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_UART2_CTS_0

Reset: 0x00000458 (0bxxxx,xxxx,xxxx,xxxx,xxx0,x1x0,x1x1,1000)

Bit Reset Description

12 DISABLE E_SCHMT:

= DISABLE0

= ENABLE1

10 SFIO GPIO_SF_SEL:

= GPIO0

= SFIO1

8 DISABLE E_LPDR:

= DISABLE0

= ENABLE1

6 ENABLE

E_INPUT:

= DISABLE0

= ENABLE1

4 TRISTATE

TRISTATE:

= PASSTHROUGH0

= TRISTATE1

3:2 PULL_UP

PUPD:

= NONE0

= PULL_DOWN1

= PULL_UP2

= RSVD3

1:0 UARTB PM:

= UARTB0

= RSVD11

= RSVD22

= RSVD33

PADCTL_UART_CFG2TMC_UART2_CTS_0

Offset: 0x8c

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_UART2_CTS_0

Reset: 0x00000000 (0bxxxx,xxx0,0000,xxx0,0000,xxxx,xxxx,xxxx)

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Bit Reset Description

24:20 0x0 CFG_CAL_DRVUP

16:12 0x0

CFG_CAL_DRVDN

PADCTL_UART_UART5_RX_0

Offset: 0x90

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_UART5_RX_0

Reset: 0x00000454 (0bxxxx,xxxx,xxxx,xxxx,xxx0,x1x0,x1x1,0100)

Bit Reset Description

12 DISABLE E_SCHMT:

= DISABLE0

= ENABLE1

10 SFIO GPIO_SF_SEL:

= GPIO0

= SFIO1

8 DISABLE E_LPDR:

= DISABLE0

= ENABLE1

6 ENABLE

E_INPUT:

= DISABLE0

= ENABLE1

4 TRISTATE

TRISTATE:

= PASSTHROUGH0

= TRISTATE1

3:2 PULL_DOWN

PUPD:

= NONE0

= PULL_DOWN1

= PULL_UP2

= RSVD3

1:0 UARTE PM:

= UARTE0

= RSVD11

= RSVD22

= RSVD33

PADCTL_UART_CFG2TMC_UART5_RX_0

Offset: 0x94

Read/Write: RW

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Parity Protection: N

SCR Protection: SCR_UART5_RX_0

Reset: 0x00000000 (0bxxxx,xxx0,0000,xxx0,0000,xxxx,xxxx,xxxx)

Bit Reset Description

24:20 0x0 CFG_CAL_DRVUP

16:12 0x0 CFG_CAL_DRVDN

PADCTL_UART_UART5_TX_0

Offset: 0x98

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_UART5_TX_0

Reset: 0x00000414 (0bxxxx,xxxx,xxxx,xxxx,xxx0,x1x0,x0x1,0100)

Bit Reset Description

12 DISABLE E_SCHMT:

= DISABLE0

= ENABLE1

10 SFIO GPIO_SF_SEL:

= GPIO0

= SFIO1

8 DISABLE E_LPDR:

= DISABLE0

= ENABLE1

6 DISABLE E_INPUT:

= DISABLE0

= ENABLE1

4 TRISTATE TRISTATE:

= PASSTHROUGH0

= TRISTATE1

3:2 PULL_DOWN

PUPD:

= NONE0

= PULL_DOWN1

= PULL_UP2

= RSVD3

1:0 UARTE PM:

= UARTE0

= RSVD11

= RSVD22

= RSVD33

PADCTL_UART_CFG2TMC_UART5_TX_0

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Offset: 0x9c

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_UART5_TX_0

Reset: 0x00000000 (0bxxxx,xxx0,0000,xxx0,0000,xxxx,xxxx,xxxx)

Bit Reset Description

24:20 0x0 CFG_CAL_DRVUP

16:12 0x0 CFG_CAL_DRVDN

PADCTL_UART_UART5_RTS_0

Offset: 0xa0

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_UART5_RTS_0

Reset: 0x00000414 (0bxxxx,xxxx,xxxx,xxxx,xxx0,x1x0,x0x1,0100)

Bit Reset Description

12 DISABLE E_SCHMT:

= DISABLE0

= ENABLE1

10 SFIO GPIO_SF_SEL:

= GPIO0

= SFIO1

8 DISABLE E_LPDR:

= DISABLE0

= ENABLE1

6 DISABLE

E_INPUT:

= DISABLE0

= ENABLE1

4 TRISTATE

TRISTATE:

= PASSTHROUGH0

= TRISTATE1

3:2 PULL_DOWN

PUPD:

= NONE0

= PULL_DOWN1

= PULL_UP2

= RSVD3

1:0

UARTE

PM:

= UARTE0

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Bit Reset Description

= RSVD11

= RSVD22

= RSVD33

PADCTL_UART_CFG2TMC_UART5_RTS_0

Offset: 0xa4

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_UART5_RTS_0

Reset: 0x00000000 (0bxxxx,xxx0,0000,xxx0,0000,xxxx,xxxx,xxxx)

Bit Reset Description

24:20 0x0

CFG_CAL_DRVUP

16:12 0x0 CFG_CAL_DRVDN

PADCTL_UART_UART5_CTS_0

Offset: 0xa8

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_UART5_CTS_0

Reset: 0x00000458 (0bxxxx,xxxx,xxxx,xxxx,xxx0,x1x0,x1x1,1000)

Bit Reset Description

12 DISABLE E_SCHMT:

= DISABLE0

= ENABLE1

10 SFIO

GPIO_SF_SEL:

= GPIO0

= SFIO1

8 DISABLE

E_LPDR:

= DISABLE0

= ENABLE1

6 ENABLE

E_INPUT:

= DISABLE0

= ENABLE1

4 TRISTATE

TRISTATE:

= PASSTHROUGH0

= TRISTATE1

3:2

PULL_UP

PUPD:

= NONE0

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Bit Reset Description

= PULL_DOWN1

= PULL_UP2

= RSVD3

1:0 UARTE PM:

= UARTE0

= RSVD11

= RSVD22

= RSVD33

PADCTL_UART_CFG2TMC_UART5_CTS_0

Offset: 0xac

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_UART5_CTS_0

Reset: 0x00000000 (0bxxxx,xxx0,0000,xxx0,0000,xxxx,xxxx,xxxx)

Bit Reset Description

24:20 0x0 CFG_CAL_DRVUP

16:12 0x0 CFG_CAL_DRVDN

PADCTL_UART_USB_VBUS_EN0_0

Offset: 0xb0

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_USB_VBUS_EN0_0

Reset: 0x00000560 (0bxxxx,xxxx,xxxx,xxxx,xxx0,x1x1,x110,0000)

Bit Reset Description

12 DISABLE E_SCHMT:

= DISABLE0

= ENABLE1

10 SFIO GPIO_SF_SEL:

= GPIO0

= SFIO1

8 ENABLE E_LPDR:

= DISABLE0

= ENABLE1

6 ENABLE

E_INPUT:

= DISABLE0

= ENABLE1

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Bit Reset Description

5 ENABLE E_IO_HV:

= DISABLE0

= ENABLE1

4 PASSTHROUGH

TRISTATE:

= PASSTHROUGH0

= TRISTATE1

3:2 NONE

PUPD:

= NONE0

= PULL_DOWN1

= PULL_UP2

= RSVD3

1:0 USB PM:

= USB0

= RSVD11

= RSVD22

= RSVD33

PADCTL_UART_CFG2TMC_USB_VBUS_EN0_0

Offset: 0xb4

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_USB_VBUS_EN0_0

Reset: 0x00000000 (0bxxxx,xxx0,0000,xxx0,0000,xxxx,xxxx,xxxx)

Bit Reset Description

24:20 0x0

CFG_CAL_DRVUP

16:12 0x0 CFG_CAL_DRVDN

PADCTL_UART_USB_VBUS_EN1_0

Offset: 0xb8

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_USB_VBUS_EN1_0

Reset: 0x00000560 (0bxxxx,xxxx,xxxx,xxxx,xxx0,x1x1,x110,0000)

Bit Reset Description

12 DISABLE E_SCHMT:

= DISABLE0

= ENABLE1

SFIO

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Bit Reset Description

GPIO_SF_SEL:

= GPIO0

= SFIO1

8 ENABLE E_LPDR:

= DISABLE0

= ENABLE1

6 ENABLE E_INPUT:

= DISABLE0

= ENABLE1

5 ENABLE E_IO_HV:

= DISABLE0

= ENABLE1

4 PASSTHROUGH TRISTATE:

= PASSTHROUGH0

= TRISTATE1

3:2 NONE

PUPD:

= NONE0

= PULL_DOWN1

= PULL_UP2

= RSVD3

1:0 USB PM:

= USB0

= RSVD11

= RSVD22

= RSVD33

PADCTL_UART_CFG2TMC_USB_VBUS_EN1_0

Offset: 0xbc

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_USB_VBUS_EN1_0

Reset: 0x00000000 (0bxxxx,xxx0,0000,xxx0,0000,xxxx,xxxx,xxxx)

Bit Reset Description

24:20 0x0 CFG_CAL_DRVUP

16:12 0x0 CFG_CAL_DRVDN

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AO PAD Control Registers

PADCTL_AO_TOUCH_CLK_0

Offset: 0x0

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_TOUCH_CLK_0

Reset: 0x00000414 (0bxxxx,xxxx,xxxx,xxxx,xxx0,x1x0,x0x1,0100)

Bit Reset Description

12 DISABLE

E_SCHMT:

= DISABLE0

= ENABLE1

10 SFIO

GPIO_SF_SEL:

= GPIO0

= SFIO1

8 DISABLE E_LPDR:

= DISABLE0

= ENABLE1

6 DISABLE E_INPUT:

= DISABLE0

= ENABLE1

4 TRISTATE TRISTATE:

= PASSTHROUGH0

= TRISTATE1

3:2 PULL_DOWN PUPD:

= NONE0

= PULL_DOWN1

= PULL_UP2

= RSVD3

1:0 GP

PM:

= GP0

= TOUCH1

= RSVD22

= RSVD33

PADCTL_AO_CFG2TMC_TOUCH_CLK_0

Offset: 0x4

Read/Write: RW

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Parity Protection: N

SCR Protection: SCR_TOUCH_CLK_0

Reset: 0x00000000 (0bxxxx,xxx0,0000,xxx0,0000,xxxx,xxxx,xxxx)

Bit Reset Description

24:20 0x0

CFG_CAL_DRVUP

16:12 0x0

CFG_CAL_DRVDN

PADCTL_AO_UART3_RX_0

Offset: 0x8

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_UART3_RX_0

Reset: 0x00000474 (0bxxxx,xxxx,xxxx,xxxx,xxx0,x1x0,x111,0100)

Bit Reset Description

12 DISABLE E_SCHMT:

= DISABLE0

= ENABLE1

10 SFIO

GPIO_SF_SEL:

= GPIO0

= SFIO1

8 DISABLE

E_LPDR:

= DISABLE0

= ENABLE1

6 ENABLE E_INPUT:

= DISABLE0

= ENABLE1

5 ENABLE E_IO_HV:

= DISABLE0

= ENABLE1

4 TRISTATE TRISTATE:

= PASSTHROUGH0

= TRISTATE1

3:2 PULL_DOWN PUPD:

= NONE0

= PULL_DOWN1

= PULL_UP2

= RSVD3

1:0

UARTC

PM:

= UARTC0

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Bit Reset Description

= RSVD11

= RSVD22

= RSVD33

PADCTL_AO_CFG2TMC_UART3_RX_0

Offset: 0xc

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_UART3_RX_0

Reset: 0x00000000 (0bxxxx,xxx0,0000,xxx0,0000,xxxx,xxxx,xxxx)

Bit Reset Description

24:20 0x0

CFG_CAL_DRVUP

16:12 0x0

CFG_CAL_DRVDN

PADCTL_AO_UART3_TX_0

Offset: 0x10

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_UART3_TX_0

Reset: 0x00000434 (0bxxxx,xxxx,xxxx,xxxx,xxx0,x1x0,x011,0100)

Bit Reset Description

12 DISABLE E_SCHMT:

= DISABLE0

= ENABLE1

10 SFIO GPIO_SF_SEL:

= GPIO0

= SFIO1

8 DISABLE

E_LPDR:

= DISABLE0

= ENABLE1

6 DISABLE

E_INPUT:

= DISABLE0

= ENABLE1

5 ENABLE E_IO_HV:

= DISABLE0

= ENABLE1

TRISTATE

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Bit Reset Description

TRISTATE:

= PASSTHROUGH0

= TRISTATE1

3:2 PULL_DOWN PUPD:

= NONE0

= PULL_DOWN1

= PULL_UP2

= RSVD3

1:0 UARTC

PM:

= UARTC0

= RSVD11

= RSVD22

= RSVD33

PADCTL_AO_CFG2TMC_UART3_TX_0

Offset: 0x14

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_UART3_TX_0

Reset: 0x00000000 (0bxxxx,xxx0,0000,xxx0,0000,xxxx,xxxx,xxxx)

Bit Reset Description

24:20 0x0 CFG_CAL_DRVUP

16:12 0x0

CFG_CAL_DRVDN

PADCTL_AO_GEN8_I2C_SDA_0

Offset: 0x18

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_GEN8_I2C_SDA_0

Reset: 0x00001570 (0bxxxx,xxxx,xxxx,xxxx,xxx1,x1x1,x111,0000)

Bit Reset Description

12 ENABLE

E_SCHMT:

= DISABLE0

= ENABLE1

10 SFIO

GPIO_SF_SEL:

= GPIO0

= SFIO1

ENABLE

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Bit Reset Description

E_LPDR:

= DISABLE0

= ENABLE1

6 ENABLE

E_INPUT:

= DISABLE0

= ENABLE1

5 ENABLE

E_IO_HV:

= DISABLE0

= ENABLE1

4 TRISTATE

TRISTATE:

= PASSTHROUGH0

= TRISTATE1

3:2 NONE PUPD:

= NONE0

= PULL_DOWN1

= PULL_UP2

= RSVD3

1:0 I2C8 PM:

= I2C80

= RSVD11

= RSVD22

= RSVD33

PADCTL_AO_CFG2TMC_GEN8_I2C_SDA_0

Offset: 0x1c

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_GEN8_I2C_SDA_0

Reset: 0x00000000 (0bxxxx,xxx0,0000,xxx0,0000,xxxx,xxxx,xxxx)

Bit Reset Description

24:20 0x0

CFG_CAL_DRVUP

16:12 0x0

CFG_CAL_DRVDN

PADCTL_AO_GEN8_I2C_SCL_0

Offset: 0x20

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_GEN8_I2C_SCL_0

Reset: 0x00001570 (0bxxxx,xxxx,xxxx,xxxx,xxx1,x1x1,x111,0000)

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Bit Reset Description

12 ENABLE

E_SCHMT:

= DISABLE0

= ENABLE1

10 SFIO

GPIO_SF_SEL:

= GPIO0

= SFIO1

8 ENABLE

E_LPDR:

= DISABLE0

= ENABLE1

6 ENABLE

E_INPUT:

= DISABLE0

= ENABLE1

5 ENABLE E_IO_HV:

= DISABLE0

= ENABLE1

4 TRISTATE TRISTATE:

= PASSTHROUGH0

= TRISTATE1

3:2 NONE PUPD:

= NONE0

= PULL_DOWN1

= PULL_UP2

= RSVD3

1:0 I2C8

PM:

= I2C80

= RSVD11

= RSVD22

= RSVD33

PADCTL_AO_CFG2TMC_GEN8_I2C_SCL_0

Offset: 0x24

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_GEN8_I2C_SCL_0

Reset: 0x00000000 (0bxxxx,xxx0,0000,xxx0,0000,xxxx,xxxx,xxxx)

Bit Reset Description

24:20 0x0 CFG_CAL_DRVUP

16:12 0x0 CFG_CAL_DRVDN

PADCTL_AO_SPI2_MOSI_0

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Offset: 0x28

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_SPI2_MOSI_0

Reset: 0x00000574 (0bxxxx,xxxx,xxxx,xxxx,xxx0,x1x1,x111,0100)

Bit Reset Description

12 DISABLE E_SCHMT:

= DISABLE0

= ENABLE1

10 SFIO GPIO_SF_SEL:

= GPIO0

= SFIO1

8 ENABLE E_LPDR:

= DISABLE0

= ENABLE1

6 ENABLE

E_INPUT:

= DISABLE0

= ENABLE1

5 ENABLE

E_IO_HV:

= DISABLE0

= ENABLE1

4 TRISTATE

TRISTATE:

= PASSTHROUGH0

= TRISTATE1

3:2 PULL_DOWN

PUPD:

= NONE0

= PULL_DOWN1

= PULL_UP2

= RSVD3

1:0 SPI2 PM:

= SPI20

= UARTG1

= RSVD22

= RSVD33

PADCTL_AO_CFG2TMC_SPI2_MOSI_0

Offset: 0x2c

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_SPI2_MOSI_0

Reset: 0x00000000 (0bxxxx,xxx0,0000,xxx0,0000,xxxx,xxxx,xxxx)

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Bit Reset Description

24:20 0x0 CFG_CAL_DRVUP

16:12 0x0 CFG_CAL_DRVDN

PADCTL_AO_GEN2_I2C_SCL_0

Offset: 0x30

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_GEN2_I2C_SCL_0

Reset: 0x00001570 (0bxxxx,xxxx,xxxx,xxxx,xxx1,x1x1,x111,0000)

Bit Reset Description

12 ENABLE

E_SCHMT:

= DISABLE0

= ENABLE1

10 SFIO

GPIO_SF_SEL:

= GPIO0

= SFIO1

8 ENABLE

E_LPDR:

= DISABLE0

= ENABLE1

6 ENABLE

E_INPUT:

= DISABLE0

= ENABLE1

5 ENABLE E_IO_HV:

= DISABLE0

= ENABLE1

4 TRISTATE TRISTATE:

= PASSTHROUGH0

= TRISTATE1

3:2 NONE PUPD:

= NONE0

= PULL_DOWN1

= PULL_UP2

= RSVD3

1:0 I2C2

PM:

= I2C20

= RSVD11

= RSVD22

= RSVD33

PADCTL_AO_CFG2TMC_GEN2_I2C_SCL_0

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Offset: 0x34

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_GEN2_I2C_SCL_0

Reset: 0x00000000 (0bxxxx,xxx0,0000,xxx0,0000,xxxx,xxxx,xxxx)

Bit Reset Description

24:20 0x0 CFG_CAL_DRVUP

16:12 0x0

CFG_CAL_DRVDN

PADCTL_AO_SPI2_CS0_0

Offset: 0x38

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_SPI2_CS0_0

Reset: 0x00000570 (0bxxxx,xxxx,xxxx,xxxx,xxx0,x1x1,x111,0000)

Bit Reset Description

12 DISABLE

E_SCHMT:

= DISABLE0

= ENABLE1

10 SFIO GPIO_SF_SEL:

= GPIO0

= SFIO1

8 ENABLE E_LPDR:

= DISABLE0

= ENABLE1

6 ENABLE E_INPUT:

= DISABLE0

= ENABLE1

5 ENABLE E_IO_HV:

= DISABLE0

= ENABLE1

4 TRISTATE TRISTATE:

= PASSTHROUGH0

= TRISTATE1

3:2 NONE

PUPD:

= NONE0

= PULL_DOWN1

= PULL_UP2

= RSVD3

1:0

SPI2

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Bit Reset Description

PM:

= SPI20

= UARTG1

= RSVD22

= RSVD33

PADCTL_AO_CFG2TMC_SPI2_CS0_0

Offset: 0x3c

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_SPI2_CS0_0

Reset: 0x00000000 (0bxxxx,xxx0,0000,xxx0,0000,xxxx,xxxx,xxxx)

Bit Reset Description

24:20 0x0 CFG_CAL_DRVUP

16:12 0x0 CFG_CAL_DRVDN

PADCTL_AO_GEN2_I2C_SDA_0

Offset: 0x40

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_GEN2_I2C_SDA_0

Reset: 0x00001570 (0bxxxx,xxxx,xxxx,xxxx,xxx1,x1x1,x111,0000)

Bit Reset Description

12 ENABLE E_SCHMT:

= DISABLE0

= ENABLE1

10 SFIO GPIO_SF_SEL:

= GPIO0

= SFIO1

8 ENABLE E_LPDR:

= DISABLE0

= ENABLE1

6 ENABLE E_INPUT:

= DISABLE0

= ENABLE1

5 ENABLE

E_IO_HV:

= DISABLE0

= ENABLE1

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Bit Reset Description

4 TRISTATE TRISTATE:

= PASSTHROUGH0

= TRISTATE1

3:2 NONE

PUPD:

= NONE0

= PULL_DOWN1

= PULL_UP2

= RSVD3

1:0 I2C2 PM:

= I2C20

= RSVD11

= RSVD22

= RSVD33

PADCTL_AO_CFG2TMC_GEN2_I2C_SDA_0

Offset: 0x44

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_GEN2_I2C_SDA_0

Reset: 0x00000000 (0bxxxx,xxx0,0000,xxx0,0000,xxxx,xxxx,xxxx)

Bit Reset Description

24:20 0x0 CFG_CAL_DRVUP

16:12 0x0 CFG_CAL_DRVDN

PADCTL_AO_SPI2_SCK_0

Offset: 0x48

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_SPI2_SCK_0

Reset: 0x00000574 (0bxxxx,xxxx,xxxx,xxxx,xxx0,x1x1,x111,0100)

Bit Reset Description

12 DISABLE E_SCHMT:

= DISABLE0

= ENABLE1

10 SFIO GPIO_SF_SEL:

= GPIO0

= SFIO1

ENABLE

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Bit Reset Description

E_LPDR:

= DISABLE0

= ENABLE1

6 ENABLE E_INPUT:

= DISABLE0

= ENABLE1

5 ENABLE E_IO_HV:

= DISABLE0

= ENABLE1

4 TRISTATE TRISTATE:

= PASSTHROUGH0

= TRISTATE1

3:2 PULL_DOWN PUPD:

= NONE0

= PULL_DOWN1

= PULL_UP2

= RSVD3

1:0 SPI2

PM:

= SPI20

= UARTG1

= RSVD22

= RSVD33

PADCTL_AO_CFG2TMC_SPI2_SCK_0

Offset: 0x4c

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_SPI2_SCK_0

Reset: 0x00000000 (0bxxxx,xxx0,0000,xxx0,0000,xxxx,xxxx,xxxx)

Bit Reset Description

24:20 0x0 CFG_CAL_DRVUP

16:12 0x0 CFG_CAL_DRVDN

PADCTL_AO_SPI2_MISO_0

Offset: 0x50

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_SPI2_MISO_0

Reset: 0x00000574 (0bxxxx,xxxx,xxxx,xxxx,xxx0,x1x1,x111,0100)

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Bit Reset Description

12 DISABLE E_SCHMT:

= DISABLE0

= ENABLE1

10 SFIO GPIO_SF_SEL:

= GPIO0

= SFIO1

8 ENABLE E_LPDR:

= DISABLE0

= ENABLE1

6 ENABLE E_INPUT:

= DISABLE0

= ENABLE1

5 ENABLE E_IO_HV:

= DISABLE0

= ENABLE1

4 TRISTATE

TRISTATE:

= PASSTHROUGH0

= TRISTATE1

3:2 PULL_DOWN

PUPD:

= NONE0

= PULL_DOWN1

= PULL_UP2

= RSVD3

1:0 SPI2 PM:

= SPI20

= UARTG1

= RSVD22

= RSVD33

PADCTL_AO_CFG2TMC_SPI2_MISO_0

Offset: 0x54

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_SPI2_MISO_0

Reset: 0x00000000 (0bxxxx,xxx0,0000,xxx0,0000,xxxx,xxxx,xxxx)

Bit Reset Description

24:20 0x0

CFG_CAL_DRVUP

16:12 0x0

CFG_CAL_DRVDN

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Always On High Voltage PAD Control Registers

PADCTL_AO_HV_CAN1_DOUT_0

Offset: 0x0

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_CAN1_DOUT_0

Reset: 0x0000c418 (0b0000,0000,0000,xxx0,1100,x10x,x0x1,1000)

Bit Reset Description

31:28 0x0

SPARE_VDD

27:24 0x0 SPARE_VAUXC

23:20 0x0 RFU_IN

16:15 0x1 SCHMITT

14:13 DEFAULT_DRIVE_1X DRV_TYPE:

DRV_TYPE[0]:

0 = 1X driver;

1 = 2X driver;

DRV_TYPE[1]:

0 = Driving codes from BDSDMEMCOMP;

1 = Default driving codes;

= COMP_DRIVE_1X0

= COMP_DRIVE_2X1

= DEFAULT_DRIVE_1X2

= DEFAULT_DRIVE_2X3

12 DISABLE E_SCHMT:

= DISABLE0

= ENABLE1

10 SFIO GPIO_SF_SEL:

= GPIO0

= SFIO1

9 DISABLE E_PBIAS_BUF:

= DISABLE0

= ENABLE1

6 DISABLE

E_INPUT:

= DISABLE0

= ENABLE1

4 TRISTATE

TRISTATE:

= PASSTHROUGH0

= TRISTATE1

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Bit Reset Description

3:2 PULL_UP PUPD:

= NONE0

= PULL_DOWN1

= PULL_UP2

= RSVD3

1:0 CAN1

PM:

= CAN10

= RSVD11

= RSVD22

= RSVD33

PADCTL_AO_HV_CFG2TMC_CAN1_DOUT_0

Offset: 0x4

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_CAN1_DOUT_0

Reset: 0x00000000 (0b0000,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:30 0x0 CFG_CAL_DRVUP_DEF

29:28 0x0 CFG_CAL_DRVDN_DEF

PADCTL_AO_HV_CAN1_DIN_0

Offset: 0x8

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_CAN1_DIN_0

Reset: 0x0000c458 (0b0000,0000,0000,xxx0,1100,x10x,x1x1,1000)

Bit Reset Description

31:28 0x0 SPARE_VDD

27:24 0x0

SPARE_VAUXC

23:20 0x0

RFU_IN

16:15 0x1

SCHMITT

14:13

DEFAULT_DRIVE_1X

DRV_TYPE:

DRV_TYPE[0]:

0 = 1X driver;

1 = 2X driver;

DRV_TYPE[1]:

0 = Driving codes from BDSDMEMCOMP;

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Bit Reset Description

1 = Default driving codes;

= COMP_DRIVE_1X0

= COMP_DRIVE_2X1

= DEFAULT_DRIVE_1X2

= DEFAULT_DRIVE_2X3

12 DISABLE E_SCHMT:

= DISABLE0

= ENABLE1

10 SFIO GPIO_SF_SEL:

= GPIO0

= SFIO1

9 DISABLE

E_PBIAS_BUF:

= DISABLE0

= ENABLE1

6 ENABLE

E_INPUT:

= DISABLE0

= ENABLE1

4 TRISTATE

TRISTATE:

= PASSTHROUGH0

= TRISTATE1

3:2 PULL_UP

PUPD:

= NONE0

= PULL_DOWN1

= PULL_UP2

= RSVD3

1:0 CAN1 PM:

= CAN10

= RSVD11

= RSVD22

= RSVD33

PADCTL_AO_HV_CFG2TMC_CAN1_DIN_0

Offset: 0xc

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_CAN1_DIN_0

Reset: 0x00000000 (0b0000,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:30 0x0

CFG_CAL_DRVUP_DEF

29:28 0x0

CFG_CAL_DRVDN_DEF

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PADCTL_AO_HV_CAN0_DOUT_0

Offset: 0x10

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_CAN0_DOUT_0

Reset: 0x0000c418 (0b0000,0000,0000,xxx0,1100,x10x,x0x1,1000)

Bit Reset Description

31:28 0x0 SPARE_VDD

27:24 0x0 SPARE_VAUXC

23:20 0x0 RFU_IN

16:15 0x1 SCHMITT

14:13 DEFAULT_DRIVE_1X

DRV_TYPE:

DRV_TYPE[0]:

0 = 1X driver;

1 = 2X driver;

DRV_TYPE[1]:

0 = Driving codes from BDSDMEMCOMP;

1 = Default driving codes;

= COMP_DRIVE_1X0

= COMP_DRIVE_2X1

= DEFAULT_DRIVE_1X2

= DEFAULT_DRIVE_2X3

12 DISABLE E_SCHMT:

= DISABLE0

= ENABLE1

10 SFIO GPIO_SF_SEL:

= GPIO0

= SFIO1

9 DISABLE E_PBIAS_BUF:

= DISABLE0

= ENABLE1

6 DISABLE E_INPUT:

= DISABLE0

= ENABLE1

4 TRISTATE TRISTATE:

= PASSTHROUGH0

= TRISTATE1

3:2

PULL_UP

PUPD:

= NONE0

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Bit Reset Description

= PULL_DOWN1

= PULL_UP2

= RSVD3

1:0 CAN0 PM:

= CAN00

= RSVD11

= RSVD22

= RSVD33

PADCTL_AO_HV_CFG2TMC_CAN0_DOUT_0

Offset: 0x14

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_CAN0_DOUT_0

Reset: 0x00000000 (0b0000,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:30 0x0 CFG_CAL_DRVUP_DEF

29:28 0x0 CFG_CAL_DRVDN_DEF

PADCTL_AO_HV_CAN0_DIN_0

Offset: 0x18

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_CAN0_DIN_0

Reset: 0x0000c458 (0b0000,0000,0000,xxx0,1100,x10x,x1x1,1000)

Bit Reset Description

31:28 0x0 SPARE_VDD

27:24 0x0 SPARE_VAUXC

23:20 0x0 RFU_IN

16:15 0x1 SCHMITT

14:13

DEFAULT_DRIVE_1X

DRV_TYPE:

DRV_TYPE[0]:

0 = 1X driver;

1 = 2X driver;

DRV_TYPE[1]:

0 = Driving codes from BDSDMEMCOMP;

1 = Default driving codes;

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Bit Reset Description

= COMP_DRIVE_1X0

= COMP_DRIVE_2X1

= DEFAULT_DRIVE_1X2

= DEFAULT_DRIVE_2X3

12 DISABLE E_SCHMT:

= DISABLE0

= ENABLE1

10 SFIO GPIO_SF_SEL:

= GPIO0

= SFIO1

9 DISABLE

E_PBIAS_BUF:

= DISABLE0

= ENABLE1

6 ENABLE

E_INPUT:

= DISABLE0

= ENABLE1

4 TRISTATE

TRISTATE:

= PASSTHROUGH0

= TRISTATE1

3:2 PULL_UP

PUPD:

= NONE0

= PULL_DOWN1

= PULL_UP2

= RSVD3

1:0 CAN0 PM:

= CAN00

= RSVD11

= RSVD22

= RSVD33

PADCTL_AO_HV_CFG2TMC_CAN0_DIN_0

Offset: 0x1c

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_CAN0_DIN_0

Reset: 0x00000000 (0b0000,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:30 0x0

CFG_CAL_DRVUP_DEF

29:28 0x0

CFG_CAL_DRVDN_DEF

PADCTL_AO_HV_CAN0_STB_0

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Offset: 0x20

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_CAN0_STB_0

Reset: 0x0000c440 (0b0000,0000,0000,xxx0,1100,x10x,x1x0,0000)

Bit Reset Description

31:28 0x0 SPARE_VDD

27:24 0x0 SPARE_VAUXC

23:20 0x0 RFU_IN

16:15 0x1 SCHMITT

14:13 DEFAULT_DRIVE_1X

DRV_TYPE:

DRV_TYPE[0]:

0 = 1X driver;

1 = 2X driver;

DRV_TYPE[1]:

0 = Driving codes from BDSDMEMCOMP;

1 = Default driving codes;

= COMP_DRIVE_1X0

= COMP_DRIVE_2X1

= DEFAULT_DRIVE_1X2

= DEFAULT_DRIVE_2X3

12 DISABLE E_SCHMT:

= DISABLE0

= ENABLE1

10 SFIO GPIO_SF_SEL:

= GPIO0

= SFIO1

9 DISABLE E_PBIAS_BUF:

= DISABLE0

= ENABLE1

6 ENABLE E_INPUT:

= DISABLE0

= ENABLE1

4 PASSTHROUGH TRISTATE:

= PASSTHROUGH0

= TRISTATE1

3:2 NONE

PUPD:

= NONE0

= PULL_DOWN1

= PULL_UP2

= RSVD3

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Bit Reset Description

1:0 RSVD0

PM:

= RSVD00

= WDT1

= RSVD22

= RSVD33

PADCTL_AO_HV_CFG2TMC_CAN0_STB_0

Offset: 0x24

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_CAN0_STB_0

Reset: 0x00000000 (0b0000,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:30 0x0 CFG_CAL_DRVUP_DEF

29:28 0x0

CFG_CAL_DRVDN_DEF

PADCTL_AO_HV_CAN0_EN_0

Offset: 0x28

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_CAN0_EN_0

Reset: 0x0000c450 (0b0000,0000,0000,xxx0,1100,x10x,x1x1,0000)

Bit Reset Description

31:28 0x0

SPARE_VDD

27:24 0x0

SPARE_VAUXC

23:20 0x0 RFU_IN

16:15 0x1 SCHMITT

14:13 DEFAULT_DRIVE_1X DRV_TYPE:

DRV_TYPE[0]:

0 = 1X driver;

1 = 2X driver;

DRV_TYPE[1]:

0 = Driving codes from BDSDMEMCOMP;

1 = Default driving codes;

= COMP_DRIVE_1X0

= COMP_DRIVE_2X1

= DEFAULT_DRIVE_1X2

= DEFAULT_DRIVE_2X3

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Bit Reset Description

12 DISABLE E_SCHMT:

= DISABLE0

= ENABLE1

10 SFIO GPIO_SF_SEL:

= GPIO0

= SFIO1

9 DISABLE E_PBIAS_BUF:

= DISABLE0

= ENABLE1

6 ENABLE E_INPUT:

= DISABLE0

= ENABLE1

4 TRISTATE

TRISTATE:

= PASSTHROUGH0

= TRISTATE1

3:2 NONE

PUPD:

= NONE0

= PULL_DOWN1

= PULL_UP2

= RSVD3

1:0 RSVD0 PM:

= RSVD00

= RSVD11

= RSVD22

= RSVD33

PADCTL_AO_HV_CFG2TMC_CAN0_EN_0

Offset: 0x2c

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_CAN0_EN_0

Reset: 0x00000000 (0b0000,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:30 0x0 CFG_CAL_DRVUP_DEF

29:28 0x0 CFG_CAL_DRVDN_DEF

PADCTL_AO_HV_CAN0_WAKE_0

Offset: 0x30

Read/Write: RW

Parity Protection: N

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SCR Protection: SCR_CAN0_WAKE_0

Reset: 0x0000c450 (0b0000,0000,0000,xxx0,1100,x10x,x1x1,0000)

Bit Reset Description

31:28 0x0 SPARE_VDD

27:24 0x0 SPARE_VAUXC

23:20 0x0 RFU_IN

16:15 0x1

SCHMITT

14:13 DEFAULT_DRIVE_1X

DRV_TYPE:

DRV_TYPE[0]:

0 = 1X driver;

1 = 2X driver;

DRV_TYPE[1]:

0 = Driving codes from BDSDMEMCOMP;

1 = Default driving codes;

= COMP_DRIVE_1X0

= COMP_DRIVE_2X1

= DEFAULT_DRIVE_1X2

= DEFAULT_DRIVE_2X3

12 DISABLE

E_SCHMT:

= DISABLE0

= ENABLE1

10 SFIO GPIO_SF_SEL:

= GPIO0

= SFIO1

9 DISABLE E_PBIAS_BUF:

= DISABLE0

= ENABLE1

6 ENABLE E_INPUT:

= DISABLE0

= ENABLE1

4 TRISTATE TRISTATE:

= PASSTHROUGH0

= TRISTATE1

3:2 NONE PUPD:

= NONE0

= PULL_DOWN1

= PULL_UP2

= RSVD3

1:0

RSVD0

PM:

= RSVD00

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Bit Reset Description

= RSVD11

= RSVD22

= RSVD33

PADCTL_AO_HV_CFG2TMC_CAN0_WAKE_0

Offset: 0x34

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_CAN0_WAKE_0

Reset: 0x00000000 (0b0000,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:30 0x0 CFG_CAL_DRVUP_DEF

29:28 0x0 CFG_CAL_DRVDN_DEF

PADCTL_AO_HV_CAN0_ERR_0

Offset: 0x38

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_CAN0_ERR_0

Reset: 0x0000c458 (0b0000,0000,0000,xxx0,1100,x10x,x1x1,1000)

Bit Reset Description

31:28 0x0

SPARE_VDD

27:24 0x0

SPARE_VAUXC

23:20 0x0

RFU_IN

16:15 0x1 SCHMITT

14:13 DEFAULT_DRIVE_1X DRV_TYPE:

DRV_TYPE[0]:

0 = 1X driver;

1 = 2X driver;

DRV_TYPE[1]:

0 = Driving codes from BDSDMEMCOMP;

1 = Default driving codes;

= COMP_DRIVE_1X0

= COMP_DRIVE_2X1

= DEFAULT_DRIVE_1X2

= DEFAULT_DRIVE_2X3

DISABLE

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Bit Reset Description

E_SCHMT:

= DISABLE0

= ENABLE1

10 SFIO

GPIO_SF_SEL:

= GPIO0

= SFIO1

9 DISABLE

E_PBIAS_BUF:

= DISABLE0

= ENABLE1

6 ENABLE

E_INPUT:

= DISABLE0

= ENABLE1

4 TRISTATE TRISTATE:

= PASSTHROUGH0

= TRISTATE1

3:2 PULL_UP PUPD:

= NONE0

= PULL_DOWN1

= PULL_UP2

= RSVD3

1:0 RSVD0

PM:

= RSVD00

= RSVD11

= RSVD22

= RSVD33

PADCTL_AO_HV_CFG2TMC_CAN0_ERR_0

Offset: 0x3c

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_CAN0_ERR_0

Reset: 0x00000000 (0b0000,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:30 0x0 CFG_CAL_DRVUP_DEF

29:28 0x0

CFG_CAL_DRVDN_DEF

PADCTL_AO_HV_CAN1_STB_0

Offset: 0x40

Read/Write: RW

Parity Protection: N

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SCR Protection: SCR_CAN1_STB_0

Reset: 0x0000c454 (0b0000,0000,0000,xxx0,1100,x10x,x1x1,0100)

Bit Reset Description

31:28 0x0

SPARE_VDD

27:24 0x0 SPARE_VAUXC

23:20 0x0 RFU_IN

16:15 0x1 SCHMITT

14:13 DEFAULT_DRIVE_1X DRV_TYPE:

DRV_TYPE[0]:

0 = 1X driver;

1 = 2X driver;

DRV_TYPE[1]:

0 = Driving codes from BDSDMEMCOMP;

1 = Default driving codes;

= COMP_DRIVE_1X0

= COMP_DRIVE_2X1

= DEFAULT_DRIVE_1X2

= DEFAULT_DRIVE_2X3

12 DISABLE E_SCHMT:

= DISABLE0

= ENABLE1

10 SFIO GPIO_SF_SEL:

= GPIO0

= SFIO1

9 DISABLE

E_PBIAS_BUF:

= DISABLE0

= ENABLE1

6 ENABLE

E_INPUT:

= DISABLE0

= ENABLE1

4 TRISTATE

TRISTATE:

= PASSTHROUGH0

= TRISTATE1

3:2 PULL_DOWN

PUPD:

= NONE0

= PULL_DOWN1

= PULL_UP2

= RSVD3

1:0

RSVD0

PM:

= RSVD00

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Bit Reset Description

= DMIC31

= DMIC52

= RSVD33

PADCTL_AO_HV_CFG2TMC_CAN1_STB_0

Offset: 0x44

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_CAN1_STB_0

Reset: 0x00000000 (0b0000,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:30 0x0

CFG_CAL_DRVUP_DEF

29:28 0x0

CFG_CAL_DRVDN_DEF

PADCTL_AO_HV_CAN1_EN_0

Offset: 0x48

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_CAN1_EN_0

Reset: 0x0000c450 (0b0000,0000,0000,xxx0,1100,x10x,x1x1,0000)

Bit Reset Description

31:28 0x0 SPARE_VDD

27:24 0x0 SPARE_VAUXC

23:20 0x0 RFU_IN

16:15 0x1 SCHMITT

14:13 DEFAULT_DRIVE_1X

DRV_TYPE:

DRV_TYPE[0]:

0 = 1X driver;

1 = 2X driver;

DRV_TYPE[1]:

0 = Driving codes from BDSDMEMCOMP;

1 = Default driving codes;

= COMP_DRIVE_1X0

= COMP_DRIVE_2X1

= DEFAULT_DRIVE_1X2

= DEFAULT_DRIVE_2X3

DISABLE

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Bit Reset Description

E_SCHMT:

= DISABLE0

= ENABLE1

10 SFIO GPIO_SF_SEL:

= GPIO0

= SFIO1

9 DISABLE E_PBIAS_BUF:

= DISABLE0

= ENABLE1

6 ENABLE E_INPUT:

= DISABLE0

= ENABLE1

4 TRISTATE TRISTATE:

= PASSTHROUGH0

= TRISTATE1

3:2 NONE

PUPD:

= NONE0

= PULL_DOWN1

= PULL_UP2

= RSVD3

1:0 RSVD0 PM:

= RSVD00

= DMIC31

= DMIC52

= RSVD33

PADCTL_AO_HV_CFG2TMC_CAN1_EN_0

Offset: 0x4c

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_CAN1_EN_0

Reset: 0x00000000 (0b0000,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:30 0x0 CFG_CAL_DRVUP_DEF

29:28 0x0 CFG_CAL_DRVDN_DEF

PADCTL_AO_HV_CAN1_WAKE_0

Offset: 0x50

Read/Write: RW

Parity Protection: N

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SCR Protection: SCR_CAN1_WAKE_0

Reset: 0x0000c450 (0b0000,0000,0000,xxx0,1100,x10x,x1x1,0000)

Bit Reset Description

31:28 0x0 SPARE_VDD

27:24 0x0 SPARE_VAUXC

23:20 0x0

RFU_IN

16:15 0x1

SCHMITT

14:13 DEFAULT_DRIVE_1X

DRV_TYPE:

DRV_TYPE[0]:

0 = 1X driver;

1 = 2X driver;

DRV_TYPE[1]:

0 = Driving codes from BDSDMEMCOMP;

1 = Default driving codes;

= COMP_DRIVE_1X0

= COMP_DRIVE_2X1

= DEFAULT_DRIVE_1X2

= DEFAULT_DRIVE_2X3

12 DISABLE

E_SCHMT:

= DISABLE0

= ENABLE1

10 SFIO

GPIO_SF_SEL:

= GPIO0

= SFIO1

9 DISABLE E_PBIAS_BUF:

= DISABLE0

= ENABLE1

6 ENABLE E_INPUT:

= DISABLE0

= ENABLE1

4 TRISTATE TRISTATE:

= PASSTHROUGH0

= TRISTATE1

3:2 NONE PUPD:

= NONE0

= PULL_DOWN1

= PULL_UP2

= RSVD3

1:0

RSVD0

PM:

= RSVD00

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Bit Reset Description

= RSVD11

= RSVD22

= RSVD33

PADCTL_AO_HV_CFG2TMC_CAN1_WAKE_0

Offset: 0x54

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_CAN1_WAKE_0

Reset: 0x00000000 (0b0000,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:30 0x0 CFG_CAL_DRVUP_DEF

29:28 0x0 CFG_CAL_DRVDN_DEF

PADCTL_AO_HV_CAN1_ERR_0

Offset: 0x58

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_CAN1_ERR_0

Reset: 0x0000c458 (0b0000,0000,0000,xxx0,1100,x10x,x1x1,1000)

Bit Reset Description

31:28 0x0 SPARE_VDD

27:24 0x0

SPARE_VAUXC

23:20 0x0

RFU_IN

16:15 0x1

SCHMITT

14:13 DEFAULT_DRIVE_1X DRV_TYPE:

DRV_TYPE[0]:

0 = 1X driver;

1 = 2X driver;

DRV_TYPE[1]:

0 = Driving codes from BDSDMEMCOMP;

1 = Default driving codes;

= COMP_DRIVE_1X0

= COMP_DRIVE_2X1

= DEFAULT_DRIVE_1X2

= DEFAULT_DRIVE_2X3

DISABLE

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Bit Reset Description

E_SCHMT:

= DISABLE0

= ENABLE1

10 SFIO

GPIO_SF_SEL:

= GPIO0

= SFIO1

9 DISABLE

E_PBIAS_BUF:

= DISABLE0

= ENABLE1

6 ENABLE E_INPUT:

= DISABLE0

= ENABLE1

4 TRISTATE TRISTATE:

= PASSTHROUGH0

= TRISTATE1

3:2 PULL_UP PUPD:

= NONE0

= PULL_DOWN1

= PULL_UP2

= RSVD3

1:0 RSVD0 PM:

= RSVD00

= RSVD11

= RSVD22

= RSVD33

PADCTL_AO_HV_CFG2TMC_CAN1_ERR_0

Offset: 0x5c

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_CAN1_ERR_0

Reset: 0x00000000 (0b0000,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

31:30 0x0

CFG_CAL_DRVUP_DEF

29:28 0x0

CFG_CAL_DRVDN_DEF

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EDP PAD Control Registers

PADCTL_EDP_SOC_GPIO50_0

Offset: 0x0

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_SOC_GPIO50_0

Reset: 0x00000454 (0bxxxx,xxxx,xxxx,xxxx,xxx0,x1x0,x1x1,0100)

Bit Reset Description

12 DISABLE E_SCHMT:

= DISABLE0

= ENABLE1

10 SFIO GPIO_SF_SEL:

= GPIO0

= SFIO1

8 DISABLE E_LPDR:

= DISABLE0

= ENABLE1

6 ENABLE

E_INPUT:

= DISABLE0

= ENABLE1

4 TRISTATE

TRISTATE:

= PASSTHROUGH0

= TRISTATE1

3:2 PULL_DOWN

PUPD:

= NONE0

= PULL_DOWN1

= PULL_UP2

= RSVD3

1:0 RSVD0 PM:

= RSVD00

= DCA1

= RSVD22

= RSVD33

PADCTL_EDP_CFG2TMC_SOC_GPIO50_0

Offset: 0x4

Read/Write: RW

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Parity Protection: N

SCR Protection: SCR_SOC_GPIO50_0

Reset: 0x00000000 (0bxxxx,xxx0,0000,xxx0,0000,xxxx,xxxx,xxxx)

Bit Reset Description

24:20 0x0 CFG_CAL_DRVUP

16:12 0x0 CFG_CAL_DRVDN

PADCTL_EDP_SOC_GPIO51_0

Offset: 0x8

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_SOC_GPIO51_0

Reset: 0x00000454 (0bxxxx,xxxx,xxxx,xxxx,xxx0,x1x0,x1x1,0100)

Bit Reset Description

12 DISABLE E_SCHMT:

= DISABLE0

= ENABLE1

10 SFIO GPIO_SF_SEL:

= GPIO0

= SFIO1

8 DISABLE E_LPDR:

= DISABLE0

= ENABLE1

6 ENABLE E_INPUT:

= DISABLE0

= ENABLE1

4 TRISTATE

TRISTATE:

= PASSTHROUGH0

= TRISTATE1

3:2 PULL_DOWN

PUPD:

= NONE0

= PULL_DOWN1

= PULL_UP2

= RSVD3

1:0 RSVD0 PM:

= RSVD00

= DCA1

= RSVD22

= RSVD33

PADCTL_EDP_CFG2TMC_SOC_GPIO51_0

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Offset: 0xc

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_SOC_GPIO51_0

Reset: 0x00000000 (0bxxxx,xxx0,0000,xxx0,0000,xxxx,xxxx,xxxx)

Bit Reset Description

24:20 0x0 CFG_CAL_DRVUP

16:12 0x0 CFG_CAL_DRVDN

PADCTL_EDP_SOC_GPIO52_0

Offset: 0x10

Read/Write: RW

Parity Protection: Y

SCR Protection: SCR_SOC_GPIO52_0

Reset: 0x00000454 (0bxxxx,xxxx,xxxx,xxxx,xxx0,x1x0,x1x1,0100)

Bit Reset Description

12 DISABLE E_SCHMT:

= DISABLE0

= ENABLE1

10 SFIO GPIO_SF_SEL:

= GPIO0

= SFIO1

8 DISABLE E_LPDR:

= DISABLE0

= ENABLE1

6 ENABLE E_INPUT:

= DISABLE0

= ENABLE1

4 TRISTATE

TRISTATE:

= PASSTHROUGH0

= TRISTATE1

3:2 PULL_DOWN

PUPD:

= NONE0

= PULL_DOWN1

= PULL_UP2

= RSVD3

1:0

RSVD0

PM:

= RSVD00

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Bit Reset Description

= DCB1

= DGPU2

= RSVD33

PADCTL_EDP_CFG2TMC_SOC_GPIO52_0

Offset: 0x14

Read/Write: RW

Parity Protection: Y

SCR Protection: SCR_SOC_GPIO52_0

Reset: 0x00000000 (0bxxxx,xxx0,0000,xxx0,0000,xxxx,xxxx,xxxx)

Bit Reset Description

24:20 0x0

CFG_CAL_DRVUP

16:12 0x0

CFG_CAL_DRVDN

PADCTL_EDP_SOC_GPIO53_0

Offset: 0x18

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_SOC_GPIO53_0

Reset: 0x00000454 (0bxxxx,xxxx,xxxx,xxxx,xxx0,x1x0,x1x1,0100)

Bit Reset Description

12 DISABLE E_SCHMT:

= DISABLE0

= ENABLE1

10 SFIO GPIO_SF_SEL:

= GPIO0

= SFIO1

8 DISABLE

E_LPDR:

= DISABLE0

= ENABLE1

6 ENABLE

E_INPUT:

= DISABLE0

= ENABLE1

4 TRISTATE TRISTATE:

= PASSTHROUGH0

= TRISTATE1

3:2

PULL_DOWN

PUPD:

= NONE0

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Bit Reset Description

= PULL_DOWN1

= PULL_UP2

= RSVD3

1:0 RSVD0 PM:

= RSVD00

= DCB1

= RSVD22

= ISTCTRL3

PADCTL_EDP_CFG2TMC_SOC_GPIO53_0

Offset: 0x1c

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_SOC_GPIO53_0

Reset: 0x00000000 (0bxxxx,xxx0,0000,xxx0,0000,xxxx,xxxx,xxxx)

Bit Reset Description

24:20 0x0

CFG_CAL_DRVUP

16:12 0x0 CFG_CAL_DRVDN

PADCTL_EDP_SOC_GPIO54_0

Offset: 0x20

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_SOC_GPIO54_0

Reset: 0x00000454 (0bxxxx,xxxx,xxxx,xxxx,xxx0,x1x0,x1x1,0100)

Bit Reset Description

12 DISABLE E_SCHMT:

= DISABLE0

= ENABLE1

10 SFIO GPIO_SF_SEL:

= GPIO0

= SFIO1

8 DISABLE

E_LPDR:

= DISABLE0

= ENABLE1

6 ENABLE

E_INPUT:

= DISABLE0

= ENABLE1

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Bit Reset Description

4 TRISTATE

TRISTATE:

= PASSTHROUGH0

= TRISTATE1

3:2 PULL_DOWN

PUPD:

= NONE0

= PULL_DOWN1

= PULL_UP2

= RSVD3

1:0 RSVD0 PM:

= RSVD00

= SDMMC31

= GP2

= RSVD33

PADCTL_EDP_CFG2TMC_SOC_GPIO54_0

Offset: 0x24

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_SOC_GPIO54_0

Reset: 0x00000000 (0bxxxx,xxx0,0000,xxx0,0000,xxxx,xxxx,xxxx)

Bit Reset Description

24:20 0x0 CFG_CAL_DRVUP

16:12 0x0 CFG_CAL_DRVDN

PADCTL_EDP_SOC_GPIO55_0

Offset: 0x28

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_SOC_GPIO55_0

Reset: 0x00000454 (0bxxxx,xxxx,xxxx,xxxx,xxx0,x1x0,x1x1,0100)

Bit Reset Description

12 DISABLE E_SCHMT:

= DISABLE0

= ENABLE1

10 SFIO GPIO_SF_SEL:

= GPIO0

= SFIO1

DISABLE

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Bit Reset Description

E_LPDR:

= DISABLE0

= ENABLE1

6 ENABLE E_INPUT:

= DISABLE0

= ENABLE1

4 TRISTATE TRISTATE:

= PASSTHROUGH0

= TRISTATE1

3:2 PULL_DOWN PUPD:

= NONE0

= PULL_DOWN1

= PULL_UP2

= RSVD3

1:0 RSVD0

PM:

= RSVD00

= SDMMC31

= RSVD22

= RSVD33

PADCTL_EDP_CFG2TMC_SOC_GPIO55_0

Offset: 0x2c

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_SOC_GPIO55_0

Reset: 0x00000000 (0bxxxx,xxx0,0000,xxx0,0000,xxxx,xxxx,xxxx)

Bit Reset Description

24:20 0x0 CFG_CAL_DRVUP

16:12 0x0 CFG_CAL_DRVDN

PADCTL_EDP_DP_AUX_CH0_HPD_0

Offset: 0x30

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_DP_AUX_CH0_HPD_0

Reset: 0x00000474 (0bxxxx,xxxx,xxxx,xxxx,xxx0,x1x0,x111,0100)

Bit Reset Description

DISABLE

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Bit Reset Description

E_SCHMT:

= DISABLE0

= ENABLE1

10 SFIO

GPIO_SF_SEL:

= GPIO0

= SFIO1

8 DISABLE

E_LPDR:

= DISABLE0

= ENABLE1

6 ENABLE E_INPUT:

= DISABLE0

= ENABLE1

5 ENABLE E_IO_HV:

= DISABLE0

= ENABLE1

4 TRISTATE TRISTATE:

= PASSTHROUGH0

= TRISTATE1

3:2 PULL_DOWN PUPD:

= NONE0

= PULL_DOWN1

= PULL_UP2

= RSVD3

1:0 DP

PM:

= DP0

= RSVD11

= RSVD22

= RSVD33

PADCTL_EDP_CFG2TMC_DP_AUX_CH0_HPD_0

Offset: 0x34

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_DP_AUX_CH0_HPD_0

Reset: 0x00000000 (0bxxxx,xxx0,0000,xxx0,0000,xxxx,xxxx,xxxx)

Bit Reset Description

24:20 0x0 CFG_CAL_DRVUP

16:12 0x0 CFG_CAL_DRVDN

PADCTL_EDP_DP_AUX_CH1_HPD_0

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Offset: 0x38

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_DP_AUX_CH1_HPD_0

Reset: 0x00000474 (0bxxxx,xxxx,xxxx,xxxx,xxx0,x1x0,x111,0100)

Bit Reset Description

12 DISABLE E_SCHMT:

= DISABLE0

= ENABLE1

10 SFIO GPIO_SF_SEL:

= GPIO0

= SFIO1

8 DISABLE E_LPDR:

= DISABLE0

= ENABLE1

6 ENABLE E_INPUT:

= DISABLE0

= ENABLE1

5 ENABLE E_IO_HV:

= DISABLE0

= ENABLE1

4 TRISTATE

TRISTATE:

= PASSTHROUGH0

= TRISTATE1

3:2 PULL_DOWN

PUPD:

= NONE0

= PULL_DOWN1

= PULL_UP2

= RSVD3

1:0 DP PM:

= DP0

= RSVD11

= RSVD22

= RSVD33

PADCTL_EDP_CFG2TMC_DP_AUX_CH1_HPD_0

Offset: 0x3c

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_DP_AUX_CH1_HPD_0

Reset: 0x00000000 (0bxxxx,xxx0,0000,xxx0,0000,xxxx,xxxx,xxxx)

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Bit Reset Description

24:20 0x0

CFG_CAL_DRVUP

16:12 0x0 CFG_CAL_DRVDN

PADCTL_EDP_DP_AUX_CH2_HPD_0

Offset: 0x40

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_DP_AUX_CH2_HPD_0

Reset: 0x00000474 (0bxxxx,xxxx,xxxx,xxxx,xxx0,x1x0,x111,0100)

Bit Reset Description

12 DISABLE

E_SCHMT:

= DISABLE0

= ENABLE1

10 SFIO

GPIO_SF_SEL:

= GPIO0

= SFIO1

8 DISABLE

E_LPDR:

= DISABLE0

= ENABLE1

6 ENABLE E_INPUT:

= DISABLE0

= ENABLE1

5 ENABLE E_IO_HV:

= DISABLE0

= ENABLE1

4 TRISTATE TRISTATE:

= PASSTHROUGH0

= TRISTATE1

3:2 PULL_DOWN PUPD:

= NONE0

= PULL_DOWN1

= PULL_UP2

= RSVD3

1:0 DP

PM:

= DP0

= DISPLAYA1

= RSVD22

= RSVD33

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PADCTL_EDP_CFG2TMC_DP_AUX_CH2_HPD_0

Offset: 0x44

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_DP_AUX_CH2_HPD_0

Reset: 0x00000000 (0bxxxx,xxx0,0000,xxx0,0000,xxxx,xxxx,xxxx)

Bit Reset Description

24:20 0x0

CFG_CAL_DRVUP

16:12 0x0

CFG_CAL_DRVDN

PADCTL_EDP_DP_AUX_CH3_HPD_0

Offset: 0x48

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_DP_AUX_CH3_HPD_0

Reset: 0x00000474 (0bxxxx,xxxx,xxxx,xxxx,xxx0,x1x0,x111,0100)

Bit Reset Description

12 DISABLE

E_SCHMT:

= DISABLE0

= ENABLE1

10 SFIO

GPIO_SF_SEL:

= GPIO0

= SFIO1

8 DISABLE

E_LPDR:

= DISABLE0

= ENABLE1

6 ENABLE E_INPUT:

= DISABLE0

= ENABLE1

5 ENABLE E_IO_HV:

= DISABLE0

= ENABLE1

4 TRISTATE TRISTATE:

= PASSTHROUGH0

= TRISTATE1

3:2 PULL_DOWN PUPD:

= NONE0

= PULL_DOWN1

= PULL_UP2

= RSVD3

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Bit Reset Description

1:0 DP PM:

= DP0

= DISPLAYB1

= RSVD22

= RSVD33

PADCTL_EDP_CFG2TMC_DP_AUX_CH3_HPD_0

Offset: 0x4c

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_DP_AUX_CH3_HPD_0

Reset: 0x00000000 (0bxxxx,xxx0,0000,xxx0,0000,xxxx,xxxx,xxxx)

Bit Reset Description

24:20 0x0

CFG_CAL_DRVUP

16:12 0x0

CFG_CAL_DRVDN

PADCTL_EDP_HDMI_CEC_0

Offset: 0x50

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_HDMI_CEC_0

Reset: 0x00000470 (0bxxxx,xxxx,xxxx,xxxx,xxx0,x1x0,x111,0000)

Bit Reset Description

12 DISABLE

E_SCHMT:

= DISABLE0

= ENABLE1

10 SFIO

GPIO_SF_SEL:

= GPIO0

= SFIO1

8 DISABLE

E_LPDR:

= DISABLE0

= ENABLE1

6 ENABLE E_INPUT:

= DISABLE0

= ENABLE1

5 ENABLE E_IO_HV:

= DISABLE0

= ENABLE1

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Bit Reset Description

4 TRISTATE TRISTATE:

= PASSTHROUGH0

= TRISTATE1

3:2 NONE PUPD:

= NONE0

= PULL_DOWN1

= PULL_UP2

= RSVD3

1:0 HDMI

PM:

= HDMI0

= RSVD11

= RSVD22

= RSVD33

PADCTL_EDP_CFG2TMC_HDMI_CEC_0

Offset: 0x54

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_HDMI_CEC_0

Reset: 0x00000000 (0bxxxx,xxx0,0000,xxx0,0000,xxxx,xxxx,xxxx)

Bit Reset Description

24:20 0x0 CFG_CAL_DRVUP

16:12 0x0

CFG_CAL_DRVDN

PADCTL_EDP_EC_FEATURE_0

==================================

GLOBAL SLICE

==================================

Offset: 0x400

Read/Write: RO

Parity Protection: N

SCR Protection: EC_SCR_0

Reset: 0x00020001 (0b0000,0000,0000,0010,xxxx,xxxx,xx00,0001)

Bit Reset Description

31:16 0x2 NUM_ERR:

Number of errors connected to this collator. This is passed as a build time option to the plugin

5:0

0x1

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Bit Reset Description

NUM_ERR_SLICES:

Number of error slices supported by this error collator, does not include the GlobalSpace and is

derived by ceil (NUM_ERR/32). SW shall first read this register to determine the number of slices

and read the required number of Error_Status registers .

PADCTL_EDP_EC_SWRESET_0

Offset: 0x404

Read/Write: WO

Parity Protection: N

SCR Protection: EC_SCR_0

Reset: 0x00000000 (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxx0)

Bit Reset Description

0 0x0 SWRST:

1'b1 : Issue a SW reset to the Error Collator. This will reset all the registers(Except SCR), counters

and logic of the Error Collator. SW can use this bit to flush errors logged into the error collator

for ex, after Boot, SC7/8 exit.

1'b0 : Do nothing, reset value.

This bit is auto-cleared.

PADCTL_EDP_EC_MISSIONERR_TYPE_0

Offset: 0x408

Read/Write: RO

Parity Protection: N

SCR Protection: EC_SCR_0

Reset: 0x00000005 (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xx00,0101)

Bit Reset Description

5:0

0x5

CODE:

This register indicates the fault code of the error line based on the value of MISSIONERR_INDEX Register.

This can be used by a fault handling agent to triage an error without requiring device-specific code.The

possible values of this field are:

6'd0 : None

6'd1 : Parity Error on internal data path

6'd2 : ECC SEC Error on internal data path

6'd3 : ECC DED Error on internal data path

6'd4 : Comparator Error

6'd5 : Register Parity Error

6'd6 : Parity Error from on-chip SRAM/Fifo

6'd7 : ECC SEC Error from on-chip SRAM/Fifo

6'd8 : ECC DED Error from on-chip SRAM/Fifo

6'd9 : Clock Monitor Error

6'd10 : Voltage Error

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Bit Reset Description

6'd11 : Temperature Error

6'd16 : SW Correctable Error

6'd17 : SW Un-Correctable Error

6'd32 : Other HW Correctable Error

6'd33 : Other HW Uncorrectable Error

All other values : Reserved for future use.

PADCTL_EDP_EC_CURRENT_COUNTER_VALUE_0

Offset: 0x40c

Read/Write: RO

Parity Protection: N

SCR Protection: EC_SCR_0

Reset: 0x00000000 (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxx0,0000,0000)

Bit Reset Description

8:0 0x0

VALUE:

Provides the current value of the counter corresponding to the error in MissionErr_Index Register.

Default provides the value of error 0 counter.

Bit[8] is the ovrerflow bit post which the counter saturates and does not counter further.

PADCTL_EDP_EC_MISSIONERR_INDEX_0

Offset: 0x414

Read/Write: RW

Parity Protection: Y

SCR Protection: EC_SCR_0

Reset: 0x00000000 (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xx00)

Bit Reset Description

1:0 0x0 IDX:

BINARY Encoded. For error number 32, register should be programmed with value 0x20.

Write to this register with Error number will update:

- MISSIONERR_TYPE Register with the Error-Code for the Error.

- CURRENT_COUNTER_VALUE Register with the error's SEC/DED Counter.

- MISSIONERR_USERVALUE with value of the first error_<i>_user signal.

SW can use this to trage the error.

number shall update the MISSIONERR_TYPE register with the error code and the Current_Counter_Value

with the value of the errors SEC/DED counter. SW can use this register to triage the error.

PADCTL_EDP_EC_CORRECTABLE_THRESHOLD_0

Offset: 0x418

Read/Write: RW

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Parity Protection: Y

SCR Protection: EC_SCR_0

Reset: 0x000000ff (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,1111,1111)

Bit Reset Description

7:0 0xff COUNT:

Threshold value for all SEC Fault Reporting Units connected to this error collator.

SEC Errors are logged once the threshold is reached and the overflow bit is set.

7'b0 : Log SEC error after receiving 1 Error.

7'b1 : Log SEC error after receiving 2 Errors.

...

7'bFF : Log SEC error after receiving 256 Errors.

PADCTL_EDP_EC_MISSIONERR_INJECT_UNLOCK_0

Offset: 0x41c

Read/Write: RW

Parity Protection: N

SCR Protection: EC_SCR_0

Reset: 0x00000000 (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,0000,0000)

Bit Reset Description

7:0 0x0

VALUE:

Writes to ERRSLICE_XXX_MISSIONERR_INJECT registers are disabled until this register is written with a

value of 0xE1.

This is to prevent an inadvertent safety error injection in the safety plugin due to:

1. A fault on ERRSLICE_XXX_MISSIONERR_INJECT register itself.

2. Erroneous SW.

The register shall be written with a value of 0x0 to reestablish the lock after user has completed the error

injection testing.

0xE1 : Unlock the MISSIONERR_INJECT Register

0x0 : Lock the MISSIONERR_INJECT Register

= LOCK0

= UNLOCK225

0x20 to 0x2C = Reserved for future use.

PADCTL_EDP_EC_ERRSLICE0_MISSIONERR_ENABLE_0

==================================

ERROR SLICE - 0

==================================

Offset: 0x430

Read/Write: RW

Parity Protection: Y

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SCR Protection: EC_SCR_0

Reset: 0x00000007 (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,x111)

Bit Reset Description

2 0x1

ERR2:

1'b1 -> Enable Mission Error Reporting for Register Parity Error from PADCTL.EDP.SCR.SOC_GPIO52

1'b0 -> Disable Mission Error Reporting for Register Parity Error from PADCTL.EDP.SCR.SOC_GPIO52

= DISABLE0

= ENABLE1

1 0x1 ERR1:

1'b1 -> Enable Mission Error Reporting for Register Parity Error from PADCTL.EDP.SOC_GPIO52

1'b0 -> Disable Mission Error Reporting for Register Parity Error from PADCTL.EDP.SOC_GPIO52

= DISABLE0

= ENABLE1

0 0x1 ERR0:

1'b1 -> Enable Mission Error Reporting for Register Parity Error from PADCTL_EDP_err_collator

1'b0 -> Disable Mission Error Reporting for Register Parity Error from PADCTL_EDP_err_collator

= DISABLE0

= ENABLE1

PADCTL_EDP_EC_ERRSLICE0_MISSIONERR_FORCE_0

Offset: 0x434

Read/Write: WO

Parity Protection: N

SCR Protection: EC_SCR_0

Reset: 0x00000000 (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,x000)

Bit Reset Description

2 0x0 ERR2:

1'b1 -> Force Assertion of Mission Error Reporting for Register Parity Error from PADCTL.EDP.SCR.

SOC_GPIO52

1'b0 -> Do Nothing

= NOFORCE0

= FORCE1

1 0x0 ERR1:

1'b1 -> Force Assertion of Mission Error Reporting for Register Parity Error from PADCTL.EDP.SOC_GPIO52

1'b0 -> Do Nothing

= NOFORCE0

= FORCE1

0x0

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Bit Reset Description

ERR0:

1'b1 -> Force Assertion of Mission Error Reporting for Register Parity Error from PADCTL_EDP_err_collator

1'b0 -> Do Nothing

= NOFORCE0

= FORCE1

PADCTL_EDP_EC_ERRSLICE0_MISSIONERR_STATUS_0

SW must write 1 to clear the fields of this register.

Bits in this register continue to be logged independent of the value of MissionError_Enable register, to avoid

silent dropping of errors.

Offset: 0x438

Read/Write: RW

Parity Protection: Y

SCR Protection: EC_SCR_0

Reset: 0x00000000 (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,x000)

Bit Reset Description

2 0x0 ERR2:

1'b1 -> Error_2_pulse[1:0] for Register Parity Error from PADCTL.EDP.SCR.SOC_GPIO52 was equal to

2'b10.

1'b0 -> Error_2_pulse[1:0] for Register Parity Error from PADCTL.EDP.SCR.SOC_GPIO52 was equal to

2'b01.

1 0x0 ERR1:

1'b1 -> Error_1_pulse[1:0] for Register Parity Error from PADCTL.EDP.SOC_GPIO52 was equal to 2'b10.

1'b0 -> Error_1_pulse[1:0] for Register Parity Error from PADCTL.EDP.SOC_GPIO52 was equal to 2'b01.

0 0x0 ERR0:

1'b1 -> Error_0_pulse[1:0] for Register Parity Error from PADCTL_EDP_err_collator was equal to 2'b10.

1'b0 -> Error_0_pulse[1:0] for Register Parity Error from PADCTL_EDP_err_collator was equal to 2'b01.

PADCTL_EDP_EC_ERRSLICE0_MISSIONERR_INJECT_0

Offset: 0x43c

Read/Write: RW

Parity Protection: N

SCR Protection: EC_SCR_0

Reset: 0x00000000 (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,x000)

Bit Reset Description

0x0

ERR2:

1'b1 -> Assert the inject_error_2 output for Register Parity Error to PADCTL.EDP.SCR.SOC_GPIO52 to

allow for error injection.

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Bit Reset Description

1'b0 -> De-Asseert inject_error_2 output.

= DISABLE0

= ENABLE1

1 0x0 ERR1:

1'b1 -> Assert the inject_error_1 output for Register Parity Error to PADCTL.EDP.SOC_GPIO52 to allow for

error injection.

1'b0 -> De-Asseert inject_error_1 output.

= DISABLE0

= ENABLE1

0 0x0 ERR0:

1'b1 -> Assert the inject_error_0 output for Register Parity Error to PADCTL_EDP_err_collator to allow for

error injection.

1'b0 -> De-Asseert inject_error_0 output.

= DISABLE0

= ENABLE1

PADCTL_EDP_EC_ERRSLICE0_LATENTERR_ENABLE_0

Offset: 0x440

Read/Write: RW

Parity Protection: Y

SCR Protection: EC_SCR_0

Reset: 0x00000007 (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,x111)

Bit Reset Description

2 0x1 ERR2:

1'b1 -> Enable Latent Error Reporting for Register Parity Error from PADCTL.EDP.SCR.SOC_GPIO52

1'b0 -> Disable Latent Error Reporting for Register Parity Error from PADCTL.EDP.SCR.SOC_GPIO52

= DISABLE0

= ENABLE1

1 0x1 ERR1:

1'b1 -> Enable Latent Error Reporting for Register Parity Error from PADCTL.EDP.SOC_GPIO52

1'b0 -> Disable Latent Error Reporting for Register Parity Error from PADCTL.EDP.SOC_GPIO52

= DISABLE0

= ENABLE1

0x1

ERR0:

1'b1 -> Enable Latent Error Reporting for Register Parity Error from PADCTL_EDP_err_collator

1'b0 -> Disable Latent Error Reporting for Register Parity Error from PADCTL_EDP_err_collator

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Bit Reset Description

= DISABLE0

= ENABLE1

PADCTL_EDP_EC_ERRSLICE0_LATENTERR_FORCE_0

Offset: 0x444

Read/Write: WO

Parity Protection: N

SCR Protection: EC_SCR_0

Reset: 0x00000000 (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,x000)

Bit Reset Description

2 0x0 ERR2:

1'b1 -> Force Assertion of Latent Error Reporting for Register Parity Error from PADCTL.EDP.SCR.

SOC_GPIO52

1'b0 -> Do Nothing

= NOFORCE0

= FORCE1

1 0x0 ERR1:

1'b1 -> Force Assertion of Latent Error Reporting for Register Parity Error from PADCTL.EDP.SOC_GPIO52

1'b0 -> Do Nothing

= NOFORCE0

= FORCE1

0 0x0 ERR0:

1'b1 -> Force Assertion of Latent Error Reporting for Register Parity Error from PADCTL_EDP_err_collator

1'b0 -> Do Nothing

= NOFORCE0

= FORCE1

PADCTL_EDP_EC_ERRSLICE0_LATENTERR_STATUS_0

SW must write 1 to clear the fields of this register.

Bits in this register continue to be logged independent of the value of LatentError_Enable register, to avoid

silent dropping of errors.

Offset: 0x448

Read/Write: RW

Parity Protection: Y

SCR Protection: EC_SCR_0

Reset: 0x00000000 (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,x000)

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Bit Reset Description

2 0x0

ERR2:

1'b1 -> Error_2_pulse[1:0] for Register Parity Error from PADCTL.EDP.SCR.SOC_GPIO52 was equal to

2'b00 or 2'b11.

1'b0 -> Error_2_pulse[1:0] for Register Parity Error from PADCTL.EDP.SCR.SOC_GPIO52 was equal to

2'b01 or 2'b10, but no latent error.

1 0x0

ERR1:

1'b1 -> Error_1_pulse[1:0] for Register Parity Error from PADCTL.EDP.SOC_GPIO52 was equal to 2'b00 or

2'b11.

1'b0 -> Error_1_pulse[1:0] for Register Parity Error from PADCTL.EDP.SOC_GPIO52 was equal to 2'b01 or

2'b10, but no latent error.

0 0x0

ERR0:

1'b1 -> Error_0_pulse[1:0] for Register Parity Error from PADCTL_EDP_err_collator was equal to 2'b00 or

2'b11.

1'b0 -> Error_0_pulse[1:0] for Register Parity Error from PADCTL_EDP_err_collator was equal to 2'b01 or

2'b10, but no latent error.

PADCTL_EDP_EC_ERRSLICE0_COUNTER_RELOAD_0

Offset: 0x450

Read/Write: WO

Parity Protection: N

SCR Protection: EC_SCR_0

Reset: 0x00000000 (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,x000)

Bit Reset Description

2 0x0

ERR2:

1'b1 -> Reload Error Counter for Register Parity Error from PADCTL.EDP.SCR.SOC_GPIO52

1'b0 -> Do Nothing

= NORELOAD0

= RELOAD1

1 0x0 ERR1:

1'b1 -> Reload Error Counter for Register Parity Error from PADCTL.EDP.SOC_GPIO52

1'b0 -> Do Nothing

= NORELOAD0

= RELOAD1

0 0x0 ERR0:

1'b1 -> Reload Error Counter for Register Parity Error from PADCTL_EDP_err_collator

1'b0 -> Do Nothing

= NORELOAD0

= RELOAD1

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UFS PAD Control Registers

PADCTL_UFS_UFS0_RST_0

Offset: 0x0

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_UFS0_RST_0

Reset: 0x00022400 (0bxxxx,xxxx,0000,xx1x,0010,x10x,x0x0,0000)

Bit Reset Description

23:20 0x0 RFU_IN

17 IORESET

IO_RESET:

= NORMAL0

= IORESET1

15 DISABLE E_PREEMP:

= DISABLE0

= ENABLE1

14:13 COMP_DRIVE_2X DRV_TYPE:

DRV_TYPE[0]:

0 = 1X driver;

1 = 2X driver;

DRV_TYPE[1]:

0 = Driving codes from BDSDMEMCOMP;

1 = Default driving codes;

= COMP_DRIVE_1X0

= COMP_DRIVE_2X1

= DEFAULT_DRIVE_1X2

= DEFAULT_DRIVE_2X3

12 DISABLE E_SCHMT:

= DISABLE0

= ENABLE1

10 SFIO GPIO_SF_SEL:

= GPIO0

= SFIO1

9 DISABLE E_HSM:

= DISABLE0

= ENABLE1

6 DISABLE E_INPUT:

= DISABLE0

= ENABLE1

PASSTHROUGH

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Bit Reset Description

TRISTATE:

= PASSTHROUGH0

= TRISTATE1

3:2 NONE PUPD:

= NONE0

= PULL_DOWN1

= PULL_UP2

= RSVD3

1:0 UFS0 PM:

= UFS00

= RSVD11

= RSVD22

= RSVD33

PADCTL_UFS_CFG2TMC_UFS0_RST_0

Offset: 0x4

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_UFS0_RST_0

Reset: 0x00000000 (0b0000,0000,xxx0,0000,0000,xxxx,xxxx,xxxx)

Bit Reset Description

31:24 0x0

CFG_CAL_DRVUP

20:12 0x0

CFG_CAL_DRVDN

PADCTL_UFS_UFS0_REF_CLK_0

Offset: 0x8

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_UFS0_REF_CLK_0

Reset: 0x00022400 (0bxxxx,xxxx,0000,xx1x,0010,x10x,x0x0,0000)

Bit Reset Description

23:20 0x0

RFU_IN

17 IORESET IO_RESET:

= NORMAL0

= IORESET1

15 DISABLE

E_PREEMP:

= DISABLE0

= ENABLE1

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Bit Reset Description

14:13 COMP_DRIVE_2X DRV_TYPE:

DRV_TYPE[0]:

0 = 1X driver;

1 = 2X driver;

DRV_TYPE[1]:

0 = Driving codes from BDSDMEMCOMP;

1 = Default driving codes;

= COMP_DRIVE_1X0

= COMP_DRIVE_2X1

= DEFAULT_DRIVE_1X2

= DEFAULT_DRIVE_2X3

12 DISABLE E_SCHMT:

= DISABLE0

= ENABLE1

10 SFIO

GPIO_SF_SEL:

= GPIO0

= SFIO1

9 DISABLE

E_HSM:

= DISABLE0

= ENABLE1

6 DISABLE

E_INPUT:

= DISABLE0

= ENABLE1

4 PASSTHROUGH

TRISTATE:

= PASSTHROUGH0

= TRISTATE1

3:2 NONE PUPD:

= NONE0

= PULL_DOWN1

= PULL_UP2

= RSVD3

1:0 UFS0 PM:

= UFS00

= RSVD11

= RSVD22

= RSVD33

PADCTL_UFS_CFG2TMC_UFS0_REF_CLK_0

Offset: 0xc

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_UFS0_REF_CLK_0

Reset: 0x00000000 (0b0000,0000,xxx0,0000,0000,xxxx,xxxx,xxxx)

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Bit Reset Description

31:24 0x0

CFG_CAL_DRVUP

20:12 0x0

CFG_CAL_DRVDN

PEX_CTL PAD Control Registers

PADCTL_PEX_CTL_2_PEX_L5_CLKREQ_N_0

Offset: 0x0

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_PEX_L5_CLKREQ_N_0

Reset: 0x00000570 (0bxxxx,xxxx,xxxx,xxxx,xxx0,x1x1,x111,0000)

Bit Reset Description

12 DISABLE

E_SCHMT:

= DISABLE0

= ENABLE1

10 SFIO GPIO_SF_SEL:

= GPIO0

= SFIO1

8 ENABLE E_LPDR:

= DISABLE0

= ENABLE1

6 ENABLE E_INPUT:

= DISABLE0

= ENABLE1

5 ENABLE E_IO_HV:

= DISABLE0

= ENABLE1

4 TRISTATE TRISTATE:

= PASSTHROUGH0

= TRISTATE1

3:2 NONE

PUPD:

= NONE0

= PULL_DOWN1

= PULL_UP2

= RSVD3

1:0

PE5

PM:

= PE50

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Bit Reset Description

= RSVD11

= RSVD22

= RSVD33

PADCTL_PEX_CTL_2_CFG2TMC_PEX_L5_CLKREQ_N_0

Offset: 0x4

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_PEX_L5_CLKREQ_N_0

Reset: 0x00000000 (0bxxxx,xxx0,0000,xxx0,0000,xxxx,xxxx,xxxx)

Bit Reset Description

24:20 0x0

CFG_CAL_DRVUP

16:12 0x0 CFG_CAL_DRVDN

PADCTL_PEX_CTL_2_PEX_L5_RST_N_0

Offset: 0x8

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_PEX_L5_RST_N_0

Reset: 0x00000560 (0bxxxx,xxxx,xxxx,xxxx,xxx0,x1x1,x110,0000)

Bit Reset Description

12 DISABLE E_SCHMT:

= DISABLE0

= ENABLE1

10 SFIO

GPIO_SF_SEL:

= GPIO0

= SFIO1

8 ENABLE

E_LPDR:

= DISABLE0

= ENABLE1

6 ENABLE

E_INPUT:

= DISABLE0

= ENABLE1

5 ENABLE

E_IO_HV:

= DISABLE0

= ENABLE1

PASSTHROUGH

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Bit Reset Description

TRISTATE:

= PASSTHROUGH0

= TRISTATE1

3:2 NONE PUPD:

= NONE0

= PULL_DOWN1

= PULL_UP2

= RSVD3

1:0 PE5 PM:

= PE50

= RSVD11

= RSVD22

= ISTCTRL3

PADCTL_PEX_CTL_2_CFG2TMC_PEX_L5_RST_N_0

Offset: 0xc

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_PEX_L5_RST_N_0

Reset: 0x00000000 (0bxxxx,xxx0,0000,xxx0,0000,xxxx,xxxx,xxxx)

Bit Reset Description

24:20 0x0

CFG_CAL_DRVUP

16:12 0x0

CFG_CAL_DRVDN

EQOS PAD Control Registers

PADCTL_EQOS_EQOS_TD3_0

Offset: 0x0

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_EQOS_TD3_0

Reset: 0x00022410 (0bxxxx,xxxx,0000,xx1x,0010,x10x,x0x1,0000)

Bit Reset Description

23:20 0x0

RFU_IN

17 IORESET

IO_RESET:

= NORMAL0

= IORESET1

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Bit Reset Description

15 DISABLE E_PREEMP:

= DISABLE0

= ENABLE1

14:13 COMP_DRIVE_2X

DRV_TYPE:

DRV_TYPE[0]:

0 = 1X driver;

1 = 2X driver;

DRV_TYPE[1]:

0 = Driving codes from BDSDMEMCOMP;

1 = Default driving codes;

= COMP_DRIVE_1X0

= COMP_DRIVE_2X1

= DEFAULT_DRIVE_1X2

= DEFAULT_DRIVE_2X3

12 DISABLE

E_SCHMT:

= DISABLE0

= ENABLE1

10 SFIO

GPIO_SF_SEL:

= GPIO0

= SFIO1

9 DISABLE

E_HSM:

= DISABLE0

= ENABLE1

6 DISABLE

E_INPUT:

= DISABLE0

= ENABLE1

4 TRISTATE TRISTATE:

= PASSTHROUGH0

= TRISTATE1

3:2 NONE PUPD:

= NONE0

= PULL_DOWN1

= PULL_UP2

= RSVD3

1:0 EQOS

PM:

= EQOS0

= RSVD11

= RSVD22

= RSVD33

PADCTL_EQOS_EQOS_TD2_0

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Offset: 0x8

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_EQOS_TD2_0

Reset: 0x00022410 (0bxxxx,xxxx,0000,xx1x,0010,x10x,x0x1,0000)

Bit Reset Description

23:20 0x0 RFU_IN

17 IORESET IO_RESET:

= NORMAL0

= IORESET1

15 DISABLE E_PREEMP:

= DISABLE0

= ENABLE1

14:13 COMP_DRIVE_2X DRV_TYPE:

DRV_TYPE[0]:

0 = 1X driver;

1 = 2X driver;

DRV_TYPE[1]:

0 = Driving codes from BDSDMEMCOMP;

1 = Default driving codes;

= COMP_DRIVE_1X0

= COMP_DRIVE_2X1

= DEFAULT_DRIVE_1X2

= DEFAULT_DRIVE_2X3

12 DISABLE E_SCHMT:

= DISABLE0

= ENABLE1

10 SFIO GPIO_SF_SEL:

= GPIO0

= SFIO1

9 DISABLE E_HSM:

= DISABLE0

= ENABLE1

6 DISABLE E_INPUT:

= DISABLE0

= ENABLE1

4 TRISTATE TRISTATE:

= PASSTHROUGH0

= TRISTATE1

3:2

NONE

PUPD:

= NONE0

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Bit Reset Description

= PULL_DOWN1

= PULL_UP2

= RSVD3

1:0 EQOS

PM:

= EQOS0

= RSVD11

= RSVD22

= RSVD33

PADCTL_EQOS_EQOS_TD1_0

Offset: 0x10

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_EQOS_TD1_0

Reset: 0x00022410 (0bxxxx,xxxx,0000,xx1x,0010,x10x,x0x1,0000)

Bit Reset Description

23:20 0x0

RFU_IN

17 IORESET

IO_RESET:

= NORMAL0

= IORESET1

15 DISABLE

E_PREEMP:

= DISABLE0

= ENABLE1

14:13 COMP_DRIVE_2X

DRV_TYPE:

DRV_TYPE[0]:

0 = 1X driver;

1 = 2X driver;

DRV_TYPE[1]:

0 = Driving codes from BDSDMEMCOMP;

1 = Default driving codes;

= COMP_DRIVE_1X0

= COMP_DRIVE_2X1

= DEFAULT_DRIVE_1X2

= DEFAULT_DRIVE_2X3

12 DISABLE

E_SCHMT:

= DISABLE0

= ENABLE1

10 SFIO

GPIO_SF_SEL:

= GPIO0

= SFIO1

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Bit Reset Description

9 DISABLE E_HSM:

= DISABLE0

= ENABLE1

6 DISABLE E_INPUT:

= DISABLE0

= ENABLE1

4 TRISTATE TRISTATE:

= PASSTHROUGH0

= TRISTATE1

3:2 NONE PUPD:

= NONE0

= PULL_DOWN1

= PULL_UP2

= RSVD3

1:0 EQOS

PM:

= EQOS0

= RSVD11

= RSVD22

= RSVD33

PADCTL_EQOS_EQOS_TD0_0

Offset: 0x18

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_EQOS_TD0_0

Reset: 0x00022410 (0bxxxx,xxxx,0000,xx1x,0010,x10x,x0x1,0000)

Bit Reset Description

23:20 0x0

RFU_IN

17 IORESET

IO_RESET:

= NORMAL0

= IORESET1

15 DISABLE

E_PREEMP:

= DISABLE0

= ENABLE1

14:13

COMP_DRIVE_2X

DRV_TYPE:

DRV_TYPE[0]:

0 = 1X driver;

1 = 2X driver;

DRV_TYPE[1]:

0 = Driving codes from BDSDMEMCOMP;

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Bit Reset Description

1 = Default driving codes;

= COMP_DRIVE_1X0

= COMP_DRIVE_2X1

= DEFAULT_DRIVE_1X2

= DEFAULT_DRIVE_2X3

12 DISABLE E_SCHMT:

= DISABLE0

= ENABLE1

10 SFIO

GPIO_SF_SEL:

= GPIO0

= SFIO1

9 DISABLE

E_HSM:

= DISABLE0

= ENABLE1

6 DISABLE E_INPUT:

= DISABLE0

= ENABLE1

4 TRISTATE TRISTATE:

= PASSTHROUGH0

= TRISTATE1

3:2 NONE PUPD:

= NONE0

= PULL_DOWN1

= PULL_UP2

= RSVD3

1:0 EQOS PM:

= EQOS0

= RSVD11

= RSVD22

= RSVD33

PADCTL_EQOS_EQOS_RD3_0

Offset: 0x20

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_EQOS_RD3_0

Reset: 0x00022450 (0bxxxx,xxxx,0000,xx1x,0010,x10x,x1x1,0000)

Bit Reset Description

23:20 0x0

RFU_IN

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Bit Reset Description

17 IORESET IO_RESET:

= NORMAL0

= IORESET1

15 DISABLE E_PREEMP:

= DISABLE0

= ENABLE1

14:13 COMP_DRIVE_2X DRV_TYPE:

DRV_TYPE[0]:

0 = 1X driver;

1 = 2X driver;

DRV_TYPE[1]:

0 = Driving codes from BDSDMEMCOMP;

1 = Default driving codes;

= COMP_DRIVE_1X0

= COMP_DRIVE_2X1

= DEFAULT_DRIVE_1X2

= DEFAULT_DRIVE_2X3

12 DISABLE E_SCHMT:

= DISABLE0

= ENABLE1

10 SFIO GPIO_SF_SEL:

= GPIO0

= SFIO1

9 DISABLE E_HSM:

= DISABLE0

= ENABLE1

6 ENABLE

E_INPUT:

= DISABLE0

= ENABLE1

4 TRISTATE

TRISTATE:

= PASSTHROUGH0

= TRISTATE1

3:2 NONE

PUPD:

= NONE0

= PULL_DOWN1

= PULL_UP2

= RSVD3

1:0 EQOS PM:

= EQOS0

= RSVD11

= RSVD22

= RSVD33

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PADCTL_EQOS_EQOS_RD2_0

Offset: 0x28

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_EQOS_RD2_0

Reset: 0x00022450 (0bxxxx,xxxx,0000,xx1x,0010,x10x,x1x1,0000)

Bit Reset Description

23:20 0x0 RFU_IN

17 IORESET IO_RESET:

= NORMAL0

= IORESET1

15 DISABLE E_PREEMP:

= DISABLE0

= ENABLE1

14:13 COMP_DRIVE_2X

DRV_TYPE:

DRV_TYPE[0]:

0 = 1X driver;

1 = 2X driver;

DRV_TYPE[1]:

0 = Driving codes from BDSDMEMCOMP;

1 = Default driving codes;

= COMP_DRIVE_1X0

= COMP_DRIVE_2X1

= DEFAULT_DRIVE_1X2

= DEFAULT_DRIVE_2X3

12 DISABLE E_SCHMT:

= DISABLE0

= ENABLE1

10 SFIO GPIO_SF_SEL:

= GPIO0

= SFIO1

9 DISABLE

E_HSM:

= DISABLE0

= ENABLE1

6 ENABLE

E_INPUT:

= DISABLE0

= ENABLE1

4 TRISTATE TRISTATE:

= PASSTHROUGH0

= TRISTATE1

3:2

NONE

PUPD:

= NONE0

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Bit Reset Description

= PULL_DOWN1

= PULL_UP2

= RSVD3

1:0 EQOS PM:

= EQOS0

= RSVD11

= RSVD22

= RSVD33

PADCTL_EQOS_EQOS_RD1_0

Offset: 0x30

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_EQOS_RD1_0

Reset: 0x00022450 (0bxxxx,xxxx,0000,xx1x,0010,x10x,x1x1,0000)

Bit Reset Description

23:20 0x0 RFU_IN

17 IORESET IO_RESET:

= NORMAL0

= IORESET1

15 DISABLE E_PREEMP:

= DISABLE0

= ENABLE1

14:13 COMP_DRIVE_2X DRV_TYPE:

DRV_TYPE[0]:

0 = 1X driver;

1 = 2X driver;

DRV_TYPE[1]:

0 = Driving codes from BDSDMEMCOMP;

1 = Default driving codes;

= COMP_DRIVE_1X0

= COMP_DRIVE_2X1

= DEFAULT_DRIVE_1X2

= DEFAULT_DRIVE_2X3

12 DISABLE E_SCHMT:

= DISABLE0

= ENABLE1

10 SFIO GPIO_SF_SEL:

= GPIO0

= SFIO1

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Bit Reset Description

9 DISABLE E_HSM:

= DISABLE0

= ENABLE1

6 ENABLE

E_INPUT:

= DISABLE0

= ENABLE1

4 TRISTATE

TRISTATE:

= PASSTHROUGH0

= TRISTATE1

3:2 NONE PUPD:

= NONE0

= PULL_DOWN1

= PULL_UP2

= RSVD3

1:0 EQOS PM:

= EQOS0

= RSVD11

= RSVD22

= RSVD33

PADCTL_EQOS_EQOS_SMA_MDIO_0

Offset: 0x38

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_EQOS_SMA_MDIO_0

Reset: 0x00022458 (0bxxxx,xxxx,0000,xx1x,0010,x10x,x1x1,1000)

Bit Reset Description

23:20 0x0 RFU_IN

17 IORESET IO_RESET:

= NORMAL0

= IORESET1

15 DISABLE E_PREEMP:

= DISABLE0

= ENABLE1

14:13

COMP_DRIVE_2X

DRV_TYPE:

DRV_TYPE[0]:

0 = 1X driver;

1 = 2X driver;

DRV_TYPE[1]:

0 = Driving codes from BDSDMEMCOMP;

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Bit Reset Description

1 = Default driving codes;

= COMP_DRIVE_1X0

= COMP_DRIVE_2X1

= DEFAULT_DRIVE_1X2

= DEFAULT_DRIVE_2X3

12 DISABLE E_SCHMT:

= DISABLE0

= ENABLE1

10 SFIO GPIO_SF_SEL:

= GPIO0

= SFIO1

9 DISABLE E_HSM:

= DISABLE0

= ENABLE1

6 ENABLE E_INPUT:

= DISABLE0

= ENABLE1

4 TRISTATE TRISTATE:

= PASSTHROUGH0

= TRISTATE1

3:2 PULL_UP

PUPD:

= NONE0

= PULL_DOWN1

= PULL_UP2

= RSVD3

1:0 EQOS PM:

= EQOS0

= RSVD11

= RSVD22

= RSVD33

PADCTL_EQOS_EQOS_RD0_0

Offset: 0x40

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_EQOS_RD0_0

Reset: 0x00022450 (0bxxxx,xxxx,0000,xx1x,0010,x10x,x1x1,0000)

Bit Reset Description

23:20 0x0 RFU_IN

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Bit Reset Description

17 IORESET

IO_RESET:

= NORMAL0

= IORESET1

15 DISABLE

E_PREEMP:

= DISABLE0

= ENABLE1

14:13 COMP_DRIVE_2X

DRV_TYPE:

DRV_TYPE[0]:

0 = 1X driver;

1 = 2X driver;

DRV_TYPE[1]:

0 = Driving codes from BDSDMEMCOMP;

1 = Default driving codes;

= COMP_DRIVE_1X0

= COMP_DRIVE_2X1

= DEFAULT_DRIVE_1X2

= DEFAULT_DRIVE_2X3

12 DISABLE

E_SCHMT:

= DISABLE0

= ENABLE1

10 SFIO

GPIO_SF_SEL:

= GPIO0

= SFIO1

9 DISABLE E_HSM:

= DISABLE0

= ENABLE1

6 ENABLE E_INPUT:

= DISABLE0

= ENABLE1

4 TRISTATE TRISTATE:

= PASSTHROUGH0

= TRISTATE1

3:2 NONE PUPD:

= NONE0

= PULL_DOWN1

= PULL_UP2

= RSVD3

1:0 EQOS

PM:

= EQOS0

= RSVD11

= RSVD22

= RSVD33

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PADCTL_EQOS_EQOS_SMA_MDC_0

Offset: 0x48

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_EQOS_SMA_MDC_0

Reset: 0x00022410 (0bxxxx,xxxx,0000,xx1x,0010,x10x,x0x1,0000)

Bit Reset Description

23:20 0x0

RFU_IN

17 IORESET

IO_RESET:

= NORMAL0

= IORESET1

15 DISABLE E_PREEMP:

= DISABLE0

= ENABLE1

14:13 COMP_DRIVE_2X DRV_TYPE:

DRV_TYPE[0]:

0 = 1X driver;

1 = 2X driver;

DRV_TYPE[1]:

0 = Driving codes from BDSDMEMCOMP;

1 = Default driving codes;

= COMP_DRIVE_1X0

= COMP_DRIVE_2X1

= DEFAULT_DRIVE_1X2

= DEFAULT_DRIVE_2X3

12 DISABLE

E_SCHMT:

= DISABLE0

= ENABLE1

10 SFIO GPIO_SF_SEL:

= GPIO0

= SFIO1

9 DISABLE E_HSM:

= DISABLE0

= ENABLE1

6 DISABLE E_INPUT:

= DISABLE0

= ENABLE1

4 TRISTATE TRISTATE:

= PASSTHROUGH0

= TRISTATE1

3:2

NONE

PUPD:

= NONE0

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Bit Reset Description

= PULL_DOWN1

= PULL_UP2

= RSVD3

1:0 EQOS

PM:

= EQOS0

= RSVD11

= RSVD22

= RSVD33

PADCTL_EQOS_EQOS_COMP_0

Offset: 0x50

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_EQOS_COMP_0

Reset: 0x00002000 (0bxxxx,xxxx,0000,xxxx,x01x,xxxx,xxx0,xx00)

Bit Reset Description

23:20 0x0

RFU_IN

14:13 COMP_DRIVE_2X DRV_TYPE:

DRV_TYPE[0]:

0 = 1X driver;

1 = 2X driver;

DRV_TYPE[1]:

0 = Driving codes from BDSDMEMCOMP;

1 = Default driving codes;

= COMP_DRIVE_1X0

= COMP_DRIVE_2X1

= DEFAULT_DRIVE_1X2

= DEFAULT_DRIVE_2X3

4 PASSTHROUGH TRISTATE:

= PASSTHROUGH0

= TRISTATE1

1:0 EQOS

PM:

= EQOS0

= RSVD11

= RSVD22

= RSVD33

PADCTL_EQOS_EQOS_TXC_0

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Offset: 0x58

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_EQOS_TXC_0

Reset: 0x00022410 (0bxxxx,xxxx,0000,xx1x,0010,x10x,x0x1,0000)

Bit Reset Description

23:20 0x0 RFU_IN

17 IORESET IO_RESET:

= NORMAL0

= IORESET1

15 DISABLE E_PREEMP:

= DISABLE0

= ENABLE1

14:13 COMP_DRIVE_2X DRV_TYPE:

DRV_TYPE[0]:

0 = 1X driver;

1 = 2X driver;

DRV_TYPE[1]:

0 = Driving codes from BDSDMEMCOMP;

1 = Default driving codes;

= COMP_DRIVE_1X0

= COMP_DRIVE_2X1

= DEFAULT_DRIVE_1X2

= DEFAULT_DRIVE_2X3

12 DISABLE E_SCHMT:

= DISABLE0

= ENABLE1

10 SFIO GPIO_SF_SEL:

= GPIO0

= SFIO1

9 DISABLE E_HSM:

= DISABLE0

= ENABLE1

6 DISABLE E_INPUT:

= DISABLE0

= ENABLE1

4 TRISTATE TRISTATE:

= PASSTHROUGH0

= TRISTATE1

3:2

NONE

PUPD:

= NONE0

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Bit Reset Description

= PULL_DOWN1

= PULL_UP2

= RSVD3

1:0 EQOS

PM:

= EQOS0

= RSVD11

= RSVD22

= RSVD33

PADCTL_EQOS_EQOS_RXC_0

Offset: 0x60

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_EQOS_RXC_0

Reset: 0x00022450 (0bxxxx,xxxx,0000,xx1x,0010,x10x,x1x1,0000)

Bit Reset Description

23:20 0x0

RFU_IN

17 IORESET

IO_RESET:

= NORMAL0

= IORESET1

15 DISABLE

E_PREEMP:

= DISABLE0

= ENABLE1

14:13 COMP_DRIVE_2X

DRV_TYPE:

DRV_TYPE[0]:

0 = 1X driver;

1 = 2X driver;

DRV_TYPE[1]:

0 = Driving codes from BDSDMEMCOMP;

1 = Default driving codes;

= COMP_DRIVE_1X0

= COMP_DRIVE_2X1

= DEFAULT_DRIVE_1X2

= DEFAULT_DRIVE_2X3

12 DISABLE

E_SCHMT:

= DISABLE0

= ENABLE1

10 SFIO

GPIO_SF_SEL:

= GPIO0

= SFIO1

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Bit Reset Description

9 DISABLE E_HSM:

= DISABLE0

= ENABLE1

6 ENABLE E_INPUT:

= DISABLE0

= ENABLE1

4 TRISTATE TRISTATE:

= PASSTHROUGH0

= TRISTATE1

3:2 NONE PUPD:

= NONE0

= PULL_DOWN1

= PULL_UP2

= RSVD3

1:0 EQOS

PM:

= EQOS0

= RSVD11

= RSVD22

= RSVD33

PADCTL_EQOS_EQOS_TX_CTL_0

Offset: 0x68

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_EQOS_TX_CTL_0

Reset: 0x00022410 (0bxxxx,xxxx,0000,xx1x,0010,x10x,x0x1,0000)

Bit Reset Description

23:20 0x0

RFU_IN

17 IORESET

IO_RESET:

= NORMAL0

= IORESET1

15 DISABLE

E_PREEMP:

= DISABLE0

= ENABLE1

14:13

COMP_DRIVE_2X

DRV_TYPE:

DRV_TYPE[0]:

0 = 1X driver;

1 = 2X driver;

DRV_TYPE[1]:

0 = Driving codes from BDSDMEMCOMP;

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Bit Reset Description

1 = Default driving codes;

= COMP_DRIVE_1X0

= COMP_DRIVE_2X1

= DEFAULT_DRIVE_1X2

= DEFAULT_DRIVE_2X3

12 DISABLE E_SCHMT:

= DISABLE0

= ENABLE1

10 SFIO

GPIO_SF_SEL:

= GPIO0

= SFIO1

9 DISABLE

E_HSM:

= DISABLE0

= ENABLE1

6 DISABLE E_INPUT:

= DISABLE0

= ENABLE1

4 TRISTATE TRISTATE:

= PASSTHROUGH0

= TRISTATE1

3:2 NONE PUPD:

= NONE0

= PULL_DOWN1

= PULL_UP2

= RSVD3

1:0 EQOS PM:

= EQOS0

= RSVD11

= RSVD22

= RSVD33

PADCTL_EQOS_EQOS_RX_CTL_0

Offset: 0x70

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_EQOS_RX_CTL_0

Reset: 0x00022450 (0bxxxx,xxxx,0000,xx1x,0010,x10x,x1x1,0000)

Bit Reset Description

23:20 0x0

RFU_IN

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Bit Reset Description

17 IORESET IO_RESET:

= NORMAL0

= IORESET1

15 DISABLE E_PREEMP:

= DISABLE0

= ENABLE1

14:13 COMP_DRIVE_2X DRV_TYPE:

DRV_TYPE[0]:

0 = 1X driver;

1 = 2X driver;

DRV_TYPE[1]:

0 = Driving codes from BDSDMEMCOMP;

1 = Default driving codes;

= COMP_DRIVE_1X0

= COMP_DRIVE_2X1

= DEFAULT_DRIVE_1X2

= DEFAULT_DRIVE_2X3

12 DISABLE E_SCHMT:

= DISABLE0

= ENABLE1

10 SFIO GPIO_SF_SEL:

= GPIO0

= SFIO1

9 DISABLE E_HSM:

= DISABLE0

= ENABLE1

6 ENABLE

E_INPUT:

= DISABLE0

= ENABLE1

4 TRISTATE

TRISTATE:

= PASSTHROUGH0

= TRISTATE1

3:2 NONE

PUPD:

= NONE0

= PULL_DOWN1

= PULL_UP2

= RSVD3

1:0 EQOS PM:

= EQOS0

= RSVD11

= RSVD22

= RSVD33

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PWR_CTL PAD Control Registers

PADCTL_PWR_CTL_CPU_PWR_REQ_1_0

Offset: 0x0

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_CPU_PWR_REQ_1_0

Reset: 0x00000400 (0bxxxx,xxxx,xxxx,xxxx,xxx0,x1x0,x0x0,0000)

Bit Reset Description

12 DISABLE E_SCHMT:

= DISABLE0

= ENABLE1

10 SFIO GPIO_SF_SEL:

= GPIO0

= SFIO1

8 DISABLE

E_LPDR:

= DISABLE0

= ENABLE1

6 DISABLE

E_INPUT:

= DISABLE0

= ENABLE1

4 PASSTHROUGH TRISTATE:

= PASSTHROUGH0

= TRISTATE1

3:2 NONE PUPD:

= NONE0

= PULL_DOWN1

= PULL_UP2

= RSVD3

1:0 RSVD0 PM:

= RSVD00

= RSVD11

= RSVD22

= RSVD33

PADCTL_PWR_CTL_CFG2TMC_CPU_PWR_REQ_1_0

Offset: 0x4

Read/Write: RW

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Parity Protection: N

SCR Protection: SCR_CPU_PWR_REQ_1_0

Reset: 0x00000000 (0bxxxx,xxx0,0000,xxx0,0000,xxxx,xxxx,xxxx)

Bit Reset Description

24:20 0x0

CFG_CAL_DRVUP

16:12 0x0

CFG_CAL_DRVDN

PADCTL_PWR_CTL_CPU_PWR_REQ_0_0

Offset: 0x8

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_CPU_PWR_REQ_0_0

Reset: 0x00000400 (0bxxxx,xxxx,xxxx,xxxx,xxx0,x1x0,x0x0,0000)

Bit Reset Description

12 DISABLE E_SCHMT:

= DISABLE0

= ENABLE1

10 SFIO

GPIO_SF_SEL:

= GPIO0

= SFIO1

8 DISABLE

E_LPDR:

= DISABLE0

= ENABLE1

6 DISABLE E_INPUT:

= DISABLE0

= ENABLE1

4 PASSTHROUGH TRISTATE:

= PASSTHROUGH0

= TRISTATE1

3:2 NONE PUPD:

= NONE0

= PULL_DOWN1

= PULL_UP2

= RSVD3

1:0 RSVD0 PM:

= RSVD00

= RSVD11

= RSVD22

= RSVD33

PADCTL_PWR_CTL_CFG2TMC_CPU_PWR_REQ_0_0

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Offset: 0xc

Read/Write: RW

Parity Protection: N

SCR Protection: SCR_CPU_PWR_REQ_0_0

Reset: 0x00000000 (0bxxxx,xxx0,0000,xxx0,0000,xxxx,xxxx,xxxx)

Bit Reset Description

24:20 0x0

CFG_CAL_DRVUP

16:12 0x0

CFG_CAL_DRVDN

8.5 Hardware Synchronization Primitives (HSP)

8.5.1 Overview

This chapter describes various modules used to allow multiple processors to share resources and communicate

together. These synchronization elements are reserved for software level interprocessor synchronization and

messaging, especially between different ARM processors. This chapter does not discuss the synchronization

elements used between a processor and a peripheral, or the mechanisms used between software threads in the

same processor cluster.

Rationale

The ARM instructions supporting exclusive access (LDREX/STREX, SWAP, etc.) can only be used inside a

coherency domain and so cannot be used between different processor clusters in the NVIDIA Xavier series

System-on-Chip (SoC). This hardware therefore provides a set of hardware synchronization primitives for

interprocessor synchronization.

There are also times when the cores inside the CCPLEX clusters do not operate in an SMP fashion. This is

required particularly during some power management sequences with caches and/or MMU disabled. Hardware

synchronization may again be required during these periods if exclusive access to a shared resource is

required.

Use Cases

Interprocessor Communication (IPC) protocols use hardware synchronization mechanisms, especially the new

doorbells, when operating between two processors not in an SMP relationship.

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Features

This section provides a quick overview of some important features. A complete specification for these features

is provided later with a high level view.

Shared Mailboxes

The shared mailboxes support a single-writer and single-reader model.

Shared Semaphores

The shared semaphores are formed by three registers, each 32-bits wide:

A read-only register showing the current value of the semaphore

Two write-only registers to set and clear individual semaphore bits

Arbitrated Semaphores

The arbitrated semaphores are true mutex binary semaphores that also include state information to avoid

software use of a busy spin loop if so desired.

Doorbells

The doorbells implement a simple mechanism to support IPC protocols. Each doorbell is one-to-one associated

with a given destination processor, and the assertion of the doorbell signal indicates to the destination

processor that at least one other processor requires attention, typically because the source processor posted a

message in memory.

The doorbell mechanism uses a source-tracking approach to aggregate multiple requests for attention into a

single register, simplifying the software communication model: the target processor identifies the set of pending

requests through a single register read.

8.5.2 Functional Description

Xavier implements an IP block that encapsulates the multiple hardware synchronization primitives, and is

accessed via an APB bus.

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Figure 8.24 Decomposition of the Hardware Synchronization Primitive

The HSP module is instantiated multiple times in Xavier, together with the number of instances of the different

primitives inside each instance.

Note: Only two different configurations are present to limit the design and verification effort (shown as the type

column). In addition, each configuration can have a redundant version.

In the following table:

nSM is the number of Shared Mailboxes

nAS is the number of Arbitrated Semaphores

nSS is the number of Shared Semaphores

nDB is the number of Doorbells

nSI is the number of Shared Interrupts (see below)

Red shows which HSPs are redundant

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Type shows the two possible HSP configurations

Table 8.54 HSP Module Instantiation

Location nSM nAS nSS nDB nSI Red Type Description

Top0 8 2 2 8 8 Yes 0 Each doorbell has an identified

destination. Other resources at

top are unallocated at this time to

cover as yet unidentified needs.

Top1 8 0 4 0 5 Yes 1 Reserved for virtualization.

Allows for a total of eight

bidirectional mailboxes at top,

same as Cortex-R5 HSP for

convenience.

BPMP 8 0 4 0 5 1 All Cortex-R5 clusters, the

Cortex-A9 cluster, and the Top1

instance use a similarly

configured HSP.

AON 8 0 4 0 5 1

SCE 8 0 4 0 5 Yes 1

APE 8 0 4 0 5 1

RCE 8 0 4 0 5 Yes 1

PVA0 8 0 4 0 5 1

PVA1 8 0 4 0 5 1

The Shared Mailboxes, Arbitrated Semaphores, and Shared Semaphores are always replicated per security

level, and each HSP supports two different security levels (TrustZone or non-TrustZone), so that nSM, nAS,

and nSS are always a multiple of two to allow differentiation between two security levels. The doorbell logic is

only duplicated for the CPU where one doorbell can be used to ping the TrustZone secure software without

interference from TrustZone non-secure software or exposing any information to the TrustZone non-secure

software.

Doorbells are system resources, instantiated once into a top level HSP. Doorbell interrupts are sent to specific

targets:

Two doorbells connected to the LIC, and from there to the CCPLEX GIC, are normally mapped to TrustZone secure

and non secure. (The CCPLEX CPU doorbell signals could be made directly visible to the CCPMU, this is not done in

Xavier.)

One doorbell directly connected to the CCPMU inside CCPLEX (the MCE used to communicate with BPMP).

Four doorbells for AON, BPMP, SCE, and RCE Cortex-R5 clusters. Each doorbell connected to VIC inside a Cortex-

R5 cluster.

One doorbell connected to the APE GIC.

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Sub-Unit Descriptions

The HSP module has these main blocks:

APB termination

Common registers and interrupt crossbar

Shared mailboxes

Shared semaphores

Arbitrated semaphores

Doorbells

APB Termination

The APB termination logic is a slave APB that transforms incoming APB transactions into local register read

and write operations. The HSP APB termination implements the new security model.

Common Registers and Interrupt Crossbar

The common registers and interrupt crossbar block contains the interrupt routing logic that takes the set of local

interrupts and generates a set of shared interrupts, connected to an interrupt controller associated with the

instance:

LIC for all HSP instantiated at top

Local VIC for HSP instantiated inside a Cortex-R5 cluster

Cortex-A9 GIC for HSP instantiated inside the APE

The number of shared interrupts, nSI, is a parameter configurable by instance and specified in the HSP Module

Instantiation table.

Shared Mailboxes

The shared mailboxes are word width registers with a very simple interrupt mechanism controlled by the MSB.

Their usual operating model is single writer/single reader.

Each shared mailbox has the following resources:

A 32-bit register

Full and empty interrupts controlled by the value of the MSB. The MSB is interpreted as a Valid bit, so the full

interrupt is the value of the MSB and the empty interrupt is the inverted value of the MSB.

All security aspects are handled by using the new security model for register access.

The number of shared mailboxes is extended to support more than one pair of communicating processors and

virtualization requirements. There are 16 unidirectional mailboxes (eight for TOP0 and eight for TOP1) at

TOP_HSP and eight unidirectional mailboxes local to each Cortex-R5 and Cortex-A9 cluster: APE, BPMP,

AON, RCE, and SCE.

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The expected usage model of shared mailboxes is:

Dedicated to a specific consumer, as it is generally easier to share the input port

Dedicated to a bidirectional IPC method, in which case shared mailboxes are allocated as a pair, one per direction

Preferably, the IPC is between one producer and one consumer to avoid resource conflicts

This is not always possible in multithreaded or multiprocessor use cases, in which either:

A single threaded software agent is used as a resource manager per direction, arbitrating, and dispatching

message. This assumes that all software producers are able to synchronize using software mechanisms, i.e.,

not shared mailboxes, and the same for all software consumers. This is a viable model for the BPMP CCPLEX

IPC.

The input and output semaphores are used for resource sharing

No easy way to operate a mailbox with agents at different levels of security on the same port. If the IPC requires a

mix of security levels and QoS per level, the IPC must use as many mailboxes as required to achieve the required

QoS.

Targeting (very) short messages, not bulk transfer. The base assumption is that the message can identify a descriptor

for a larger structure when needed, possibly via an address offset against some known base or an index in a list or

whatever is convenient for software. Shared mailboxes are not optimized for bandwidth.

Shared Semaphores

The shared semaphores are registers with associated SET/CLR addresses to allow easy manipulation of

individual bits inside them, i.e., without the need for a RMW operation. There is no hardware arbitration, so

software must statically allocate the ownership of individual semaphores for correct operation.

The shared semaphores are formed by three registers, each 32 bits wide:

Read-only register showing the current value of the semaphore

Two write-only registers to set and clear individual semaphore bits

These semaphores can be used for synchronizing processors acting in a producer/consumer relationship, i.e., a

pair of them can be used to implement either a two- or four-way handshake.

Correct operation of the shared semaphores require to statically allocate an owner for each bit, because it is

impossible to implement an atomic test and set (or similar operation) given the register interface. It also means

that calling them "semaphores" is a bit misleading; they are simply atomic set and atomic clear registers.

Arbitrated Semaphores

The arbitrated semaphores are true binary semaphores that also include state information to avoid a busy spin

loop if so wanted. The arbitrated semaphores support two sides, simply denoted 0 and 1, and arbitrates

between requests coming from each side.

In essence, the arbitrated semaphores are built in the following way, all registers being 32 bits wide:

A set of read only flags representing ownership (SMP_GNT_ST), showing ownership of the semaphore, one register

per side (0 and 1).

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A set of write only trigger request flags (SMP_GET), a processor can only acquire a resource (represented by a bit in

the status word) through setting a corresponding request flag. The request is blocked until the resource is not owned

by a different processor. Currently, request flags are only cleared by acquiring the resource. Again, there is one

A set of clear flags (SMP_PUT), a processor relinquishes ownership by writing a one bit corresponding to the shared

resource (write only).

A set of request status flags (SMP_REQ_ST) showing the current pending requests (read only)

One companion set of registers is defined, with one register per side (0 and 1).

Enable register (INT_EN), enabling the generation of an interrupt if the corresponding status bit toggles.

Storing the request information instead of simply using write triggers allows the following implementation to

avoid the typical busy spin lock loop and the corresponding waste of bandwidth and power.

EnableOwnershipInterrupt (i);

RequestResource (i);

WaitForInterrupt();

Doorbell Logic

A doorbell allows a set of source agents in Xavier to request the attention of a specified target agent.

The doorbell logic presents two logically separate interfaces:

The trigger interface can be used by any master in the system; the doorbell logic uses source ID tracking to recognize

the exact source.

The control interface is normally configured for use by the target agent only.

The trigger interface also distinguishes between TrustZone secure and not secure security levels. The doorbell

includes one bit per possible source, per supported security level. Writing to the trigger interface sets a

corresponding bit as shown in the pseudo code below (for one doorbell):

SourceID = f(pUSER) // extract source ID for APB USER field

If TriggerWrite

If pns == TZ_SECURE: Map_0[SourceID] = 1b

If pns == TZ_NOT_SECURE: Map_1[SourceID] = 1b

The control logic uses security aware registers to control whose agent has access to it, with the following set of

registers:

Standard security configuration register to specify the exact security model

Bitmap indicating which sources can raise the doorbell signal and at which security level

Status/control register indicating the set of sources with pending flags (clear on write)

Status/control register indicating the raw bitmap (clear on write)

The control logic then generates one doorbell signal per doorbell. The doorbell signals are:

Exposed as a port with a direct connection to the target processor cluster interrupt controller

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VIC inside a Cortex-R5 cluster

GIC inside the APE cluster

LIC for CCPLEX, and from there directly to the GIC, as the GIC is essentially transparent for the CCPLEX path

CCPLEX power management

Exposed to the interrupt crossbar logic in the HSP, so that it can be mapped as a HSP shared interrupt, allowing the

doorbell to be routed to a different target.

The operation of one doorbell is illustrated in the figure below:

Figure 8.25 Doorbell Logic

Doorbells are identified by numbers, with the following mapping between a doorbell number and its intended

destination.

Table 8.55 Mapping between Doorbell Number and Usage

Doorbell Target

0 CCPLEX power management

1 CCPLEX TrustZone not secure

2 CCPLEX TrustZone secure

3 BPMP

4 AON

5 SCE

6 APE

7 RCE

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Multiple Processors Access to Shared Resources

Xavier does not support full coherency mechanisms, so an IPC protocol must tackle ordering and visibility

issues. The protocol uses a doorbell interrupt to get attention and a standard structure of circular buffers plus

associated read/write pointers in shared memory (internal or external). With this model, the expected software

sequence looks like the following:

Source Processor

Writes a set of messages with known format in shared memory circular buffer structure

If the shared memory is cacheable, flushes its cache to make the messages globally visible

Issues a DMB to ensure that pointer and message are ordered

Writes the value of the write pointer at known location in shared memory

If the shared memory is cacheable, flushes its cache

Issues a DMB to ensure ordering between pointer and interrupt

Writes to a doorbell register in MMIO space to trigger the interrupt to the destination

Destination Processor

Receives doorbell interrupt and enters Interrupt Service Routine

Reads the associated doorbell status register to identify the set of source processors with pending messages

Cache invalidates the address used by the write pointer for the source processor circular buffer

Issues a DMB

Read the write pointer

Cache invalidates the addresses used by the set of messages identified by the write pointer

Issues a DMB

Reads the set of messages

Using Doorbells for Handshake during Boot Sequence

During the boot sequence, the doorbells are used to synchronize the boot sequence across multiple

processors. Each doorbell allows for a full handshake between two processors, denoted as B (normally BPMP)

and D (normally CCPLEX power management). The handshake makes sure that D executes a specific task A

at a time controlled by B and works like this.

B performs all tasks that must be done before task A can be done. When everything is ready, B signals to D that it

can proceed by ringing D doorbell (i.e., writing to the doorbell trigger register). B can continue working on other tasks

not dependent on task A completion. When it reaches a point that requires task A to be complete, B check the

doorbell pending status. If the doorbell is still asserted, B waits for completion by polling on the doorbell status.

D performs all tasks that must be done before task A can be done. When everything is ready D checks if its doorbell

is asserted. If not, it polls on its doorbell until assertion.

D performs task A, then signals completion to B by clearing the doorbell (i.e., by writing to the doorbell pending

status). Clearing the doorbell is acting as an acknowledge by D.

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When B sees the doorbell pending status deasserted, it knows that task A is complete and can now execute tasks

dependent on task A completion.

Shared Interrupts Configuration

Each shared interrupt is the aggregate of the selected bits; in other words, each shared interrupt is driven by the

same structure of AND followed by OR used in LIC. The figure below shows the logic for the Top0 HSP

instance.

Figure 8.26 Shared Interrupt Logic

Assume that software wants to map the shared interrupts as follows:

Shared0 is a (aggregated) mailbox empty, so IE0 = 0xFF

Shared1 is a (aggregated) mailbox full, so IE1 = 0xFF << 8

Shared2 is Arbitrated Semaphore 0, and Arbitrated Semaphore 1 is not used, so IE2 = 0x1 << 24

8.5.3 Programming Model

The programming model is register based.

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8.5.4 HSP Programming Guidelines

Shared Mailboxes

A shared mailbox serves a unidirectional communication between a producer and a consumer. The two masters

agree upon a mailbox to use, and which master is the producer and which master is the consumer. In the

following sequences, it is assumed that shared mailbox {sm} is selected.

Producer Sending a Message

Make sure the selected shared mailbox is empty by checking the TAG field of register HSP_SHRD_MBOX_MBOX_

{sm}_SHRD_MBOX_0.

Write the message in the DATA field of register HSP_SHRD_MBOX_MBOX_{sm}_SHRD_MBOX_0. Set the TAG

field of the register to 1.

Consumer Receiving a Message

Read register HSP_SHRD_MBOX_MBOX_{sm}_SHRD_MBOX_0. If TAG field is 1, then the DATA field carries the

message.

After consuming the message in the mailbox, set the TAG field of the register to 0. The DATA field is don't care and

can be written with any value.

Shared Semaphores

A producer/consumer pair uses shared semaphore to synchronize management of a shared resource. Each bit

in a shared semaphore register represents a shared semaphore. The producer and consumer select a shared

semaphore to use (a particular shared semaphore register and a particular bit) and agree on their roles.

In the following sequences, we assume bit {b} of shared semaphore register {ss} is selected.

Producer

Make sure the shared semaphore is empty by checking that bit {b} in HSP_SHRD_SEM_{ss}_SHRD_SMP_STA_0 is

The Producer writes to the shared resource.

Indicate the data in the shared resource is ready for consumption by writing 1 to bit {b} in HSP_SHRD_SEM_{ss}

_SHRD_SMP_STA_SET_0.

Consumer

The shared resource is ready for consumption when reading HSP_SHRD_SEM_{ss}_SHRD_SMP_STA_0 return

value 1 in bit {b}.

The Consumer consumes the data in the shared resource.

Indicate that the shared resource is available for new data by writing 1 to bit {b} in HSP_SHRD_SEM_{ss}

_SHRD_SMP_STA_CLR_0.

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Arbitrated Semaphores

Each arbitrated semaphore is accessed through two register sets, indexed by 0 and 1; one set for each master

sharing the arbitrated semaphore. Each bit in the arbitrated semaphore register corresponds to an arbitrated

semaphore. The two masters agree on an arbitrated semaphore to use (a particular arbitrated semaphore

set 1.

In the following sequences, we assume bit {b} of the arbitrated semaphore register {as} is selected.

Requesting Semaphore with Interrupt

Enable the ownership interrupt by setting the corresponding bit in HSP_ARB_SEM{0,1}_{as}_INT_EN_0.

Set the corresponding bit in HSP_ARB_SEM{0,1}_{as}_SMP_GET_0 to 1.

Wait for the interrupt. When that happens, the semaphore is acquired.

Requesting Semaphore with Busy Spin Lock

Set bit {b} in HSP_ARB_SEM{0,1}..{as}_SMP_GET_0 to 1.

Poll register HSP_ARB_SEM{0,1}..{as}_SMP_GNT_ST_0. When the bit {b} is 1, the semaphore is acquired.

Relinquishing Semaphore

Set bit {b} in HSP_ARB_SEM{0,1}_{as}_SMP_PUT_0 to 1.

Doorbells

A triggering master can ask for attention from the receiving master by ringing the doorbell of the receiving

master. In the following sequences, we assume {db} is the doorbell index of the receiving master. There is a

dedicated doorbell for each master in TOP0_HSP.

Ringing a Doorbell

Check that the receiving master receives the doorbell by ensuring that the bit corresponds to the triggering master

and its security level of HSP_DBELL_{db}_ENABLE_0 is 1.

Write to HSP_DBELL_{db}_TRIGGER_0. Any value can be written.

Answering a Doorbell

After servicing a doorbell, the receiving master clears the doorbell from a particular master and security level by

writing 1 to the corresponding bit in HSP_DBELL_{db}_PENDING_0.

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8.5.5 HSP Registers

The set of registers is split across the different modules, each set share a common base. Each module has a

number of 64-KiB pages to help in virtualization in Xavier and all of the modules expose their registers via an

APB interface. Each submodule in HSP has its own set of 64-KiB pages plus an extra 64-KiB page for the

common registers. The different windows are placed one after the other in this order:

One 64-KiB page for the common registers

nSM/2 64-KiB pages for the shared mailboxes, grouped in pairs to support bidirectional communication. The number

of mailboxes in a given HSP must be even.

nSS 64-KiB pages for the shared semaphores

nAS 64-KiB pages for the arbitrated semaphores

One 64-KiB page for the doorbells.

All these are referred to a base address shown as HSP_{inst}_BASE in this document, where {inst} identifies

the specific HSP instance.

All transactions sent to a given module must be terminated, if an address is not assigned or if the access

violates some access restrictions, an error response is sent and the access does not affect any state outside of

the APB interface itself.

Common Registers

Common registers are used for two independent reasons:

For truly common functionality

To increase the functionality while keeping the legacy architecture. This is done for security handling. It is

recommended for some modules are treated as one security group, with the security handling performing in a

wrapper that instantiates the legacy code.

The common registers offset is from HSP_{inst}_BASE. The common registers consist of Security Control

Registers (SCRs) and HSP Interrupt registers:

HSP_SCR_SS_{ss}_REG_0

HSP_SCR_AS_{as}_REG_0

HSP_SCR_SM_{sm}_REG_0

HSP_SCR_DBELL_{db}_REG_0

HSP_INT_SCR_SCR_C0_REG_0

HSP_INT_IE{i}_0 (register array)

HSP_INT_IV_0

HSP_INT_IR_0

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HSP Interrupt Registers

The mapping of the HSP internal interrupts is defined as follows:

Bits[00 + [nSM-1:0]] are the empty interrupts of the nSM instantiated shared mailboxes

Bits[08 + [nSM-1:0]] are the full interrupts of the nSM instantiated shared mailboxes

Bits[16 + [nDB-1:0]] are the interrupts of the nDB instantiated doorbells

Bits[24 + [nAS-1:0]] are the grant interrupts of the nAS instantiated arbitrated semaphores

Bits not defined by the mapping above are marked reserved and not physically present. This is true for both IE

{i} and IR registers. Note that this mapping means that nSM, nDB cannot exceed 8 and nAS cannot exceed 4,

for a given HSP instance.

These registers have the same bit mapping, shown in the following table.

Table 8.56 Format of the IE{i} and IR Interrupt Registers

Bit Reset Description

31:28 0x0 smp1_gnt_enable/valid/asserted

27:24 0x0 smp0_gnt_enable/valid/asserted

23:16 0x0 dbell_enable/valid/asserted

15:8 0x0 mbox_full_enable/valid/asserted

7:0 0x0 mbox_empty_enable/valid/asserted

HSP_INT{i}_IE_0

This is an array of eight identical register entries. This array controls the routing of interrupt {i}, a bit mask

indicating which of the internal interrupts is propagated to external interrupt {i}, {i} in [0:nSI-1].

ExternalInterrupts[i] = |(IE{i} & InternalInterrupts}

See the Format of the IE{i} and IR Interrupt Registers table for the organization of the register fields.

Offset: 0x100..0x11f | Read/Write: R/W | SCR Protection: SCR_C0_REG_0 | Reset: 0x00000000

HSP_INT_IV_0

This register contains the currently asserted shared interrupts, ExternalInterrupts.

Each bit of IV is mapped to the corresponding shared interrupt.

Offset: 0x300 | Read/Write: RO | SCR Protection: SCR_C0_REG_0 | Reset: 0x00000000

HSP_INT_IR_0

This register indicates the currently asserted internal interrupts, InternalInterrupts.

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See the Format of the IE{i} and IR Interrupt Registers table for the organization of the register fields.

Offset: 0x304 | Read/Write: RO | SCR Protection: SCR_C0_REG_0 | Reset: 0x000000ff

HSP_INT_SPARE_0

Offset: 0x308 | Read/Write: R/W | Reset: 0x00000000 (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,0000)

Bit Reset Description

3:0 0x0 spare

HSP_INT_HSP_CLK_OVR_0

Offset: 0x30c | Read/Write: R/W | Reset: 0x00000000 (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxx0)

Bit Reset Description

0 0x0 hsp_clk_ovr_on

HSP_INT_DIMENSIONING_0

Offset: 0x380 | Read/Write: RO | Reset: 0x000XXXXX (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx)

Bit Reset Description

19:16 X nSI: Number of shared interrupts in this instance

15:12 X nDB: Number of doorbells in this instance

11:8 X nAS: Number of arbitrated semaphores in this instance

7:4 X nSS: Number of shared semaphores in this instance

3:0 X nSM: Number of shared mailboxes in this instance

Shared Mailbox Registers

Shared mailboxes are placed 32 KiB apart, so that a pair is mapped in a 64 KiB page. The base for a given

mailbox is SM{sm} {inst}_BASE + 64 KiB + {sm} * 32 KiB.

BASE{sm} = HSP

HSP_SHRD_MBOX_MBOX_{sm}_SHRD_MBOX_0

Software-controlled mailbox registers. There are eight shared mailbox registers, where {sm} = 0 through 7.

Offset: 0x0 + (sm * 0x8000) | Read/Write: R/W | SCR Protection: SM_{sm}_REG_0 | Reset: 0x00000000

(0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

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Bit Reset Description

TAG: This bit acts as a Valid bit for the mailbox. The mailbox is deemed full when TAG = 1b and empty when

TAG = 0b, with the status also reflected in corresponding interrupts. The producer writes TAG to 1b to signal

the availability of a message; the consumer writes TAG to 0b to signal that the message has been fully

handled.

30:0 0 DATA: Value exchanged between producer and consumer. No hardware semantic.

HSP_SHRD_MBOX_MBOX_{sm}_SHRD_MBOX_FULL_INT_IE_0

Offset: 0x4 + (sm * 0x8000) | Read/Write: R/W | Parity Protection: N | SCR Protection: SM_{sm}_REG_0 |

Reset: 0x00000001 (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxx1)

Bit Reset Description

0 0x1 ENABLE: Mailbox full interrupt enable

HSP_SHRD_MBOX_MBOX_{sm}_SHRD_MBOX_EMPTY_INT_IE_0

Offset: 0x8 + (sm * 0x8000) | Read/Write: R/W | Parity Protection: N | SCR Protection: SM_{sm}_REG_0 |

Reset: 0x00000001 (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxxx,xxx1)

Bit Reset Description

0 0x1 ENABLE: Mailbox empty interrupt enable

Shared Semaphore Registers

Each shared semaphore instance has an associated page starting at SS{ss} {inst}_BASE + (1 +

BASE = HSP

nSM/2) * 64 KiB + {ss} * 64 KiB.

HSP_SHRD_SEM_{ss}_SHRD_SMP_STA_0

There are eight shared semaphore status registers, where {ss} is 0 through 7. This register gives the current

status for the shared semaphore instance.

Offset: 0x000 + (ss * 0x10000) | Read/Write: RO | SCR Protection: SS_{ss}_REG_0 | Reset: 0x00000000

Bit Reset Description

31:0 0 SMP: Current value. Each bit is an individual semaphore.

HSP_SHRD_SEM_{ss}_SHRD_SMP_STA_SET_0

There are eight shared semaphore set registers, where {ss} is 0 through 7. Set the bits in this register to update

the current value.

Offset: 0x004 + (ss * 0x10000) | Read/Write: WO | SCR Protection: SS_{ss}_REG_0 | Reset: NA

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Bit Reset Description

31:0 NA SMP_SET: Writing bit i to 1b sets semaphore bit i. Undefined for reads.

HSP_SHRD_SEM_{ss}_SHRD_SMP_STA_CLR_0

There are eight shared semaphore clear registers, where {ss} is 0 through 7. Clear the bits in this register to

update the current value.

Offset: 0x008 + (ss * 0x10000) | Read/Write: WO | SCR Protection: SS_{ss}_REG_0 | Reset: NA

Bit Reset Description

31:0 NA SMP_CLR: Writing bit i to 1b clears semaphore bit i. Undefined for reads.

Arbitrated Semaphore Registers

Arbitrated semaphore instance {as} has a register range starting at AS{as} {inst}_BASE + (1 + nSM

BASE = HSP

/2 + nSS) * 64 KiB + {as} * 64 KB. Each arbitrated semaphore instance contains two apertures, identified as {a}

in {0,1}, corresponding to two different owners. The owner associated with an aperture is defined by software

convention. The following table shows the base offset according to arbitrated semaphore instance and aperture.

Table 8.57 Base Offsets of Arbitrated Semaphore Registers

Semaphore Instance {as} Base Offset

Aperture 0 {a} = 0 Aperture 1 {a} = 1

0 0x00 0x20

1 0x10000 0x10020

2 0x20000 0x20020

3 0x30000 0x30020

HSP_ARB_SEM{a}_{as}_SMP_GNT_ST_0

This register indicates current ownership; each bit is an individual semaphore. There are eight Arbitrated

Semaphore Grant Status registers, where {as} = semaphore 0 through 3 and {a} = aperture 0 or 1.

Offset: Base | Read/Write: RO | SCR Protection: AS_{as}_REG_0 | Reset: 0x00000000 (0b0000,

0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0 STATUS: Bit i at 1 indicates aperture{a} is the current owner of resource i

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HSP_ARB_SEM{a}_{as}_SMP_GET_0

There are eight Arbitrated Semaphore Get registers, where {as} = semaphore 0 through 3 and {a} = aperture 0

or 1. Use this register to make a request for ownership.

Offset: Base + 0x4 | Read/Write: WO | SCR Protection: AS_{as}_REG_0 | Reset: 0x00000000 (0b0000,

0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 NA GET: Writing bit i to 1b is a request for ownership of resource i from aperture {a}. All pending requests are

accumulated in an internal register visible as HSP_ARB_SEM{a}_{as}_REQ_ST_0. Requests cannot be

canceled; a request bit gets cleared when ownership is acquired.

HSP_ARB_SEM{a}_{as}_SMP_PUT_0

There are eight Arbitrated Semaphore Put registers, where {as} = semaphore 0 through 3 and {a} = aperture 0

or 1. Use this register to relinquish ownership.

Offset: Base + 0x8 | Read/Write: WO | SCR Protection: AS_{as}_REG_0 | Reset: 0x00000000 (0b0000,

0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 NA PUT: Writing bit i to 1b relinquishes ownership of resource i from aperture {a}.

HSP_ARB_SEM{a}_{as}_SMP_REQ_ST_0

There are eight Arbitrated Semaphore Request registers, where {as} = semaphore 0 through 3 and {a} =

aperture 0 or 1. This register indicates if there are any pending requests.

Offset: Base + 0xc | Read/Write: RO | SCR Protection: AS_{as}_REG_0 | Reset: 0x00000000 (0b0000,

0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:0 0 REQ: Bitmap of pending requests from aperture {a}.

HSP_ARB_SEM{a}_{as}_SMP_INT_EN_0

There are eight Arbitrated Semaphore Interrupt Enable registers, where {as} = semaphore 0 through 3 and {a} =

aperture 0 or 1.

Offset: Base + 0x10 | Read/Write: R/W | SCR Protection: AS_{as}_REG_0 | Reset: 0x00000000 (0b0000,

0000,0000,0000,0000,0000,0000,0000)

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Bit Reset Description

31:0 0 EN: Interrupt enable. The interrupt is active when resource i is granted to aperture {a} and the corresponding

enable bit is 1.

HSP_ARB_SEM_SPARE_SPARE_0

Offset: 0x80 | Read/Write: R/W | SCR Protection: None | Reset: 0x00000000 (0bxxxx,xxxx,xxxx,xxxx,xxxx,xxxx,

xxxx,xxx0)

Bit Reset Description

31:0 0 SPARE

Doorbell Registers

All doorbell registers are in a single page, doorbell {db} has a register range starting at DB{db} {inst}

BASE = HSP

_BASE + (1 + nSM/2 + nSS + nAS) * 64 KiB + {db} * 0x100.

In the Enable, Raw, and Pending registers, each field is defined as a bitmap, where each bit is associated with

a master ID. Only the bits associated with valid Master ID are guaranteed to be present. Two of these are

packed per register to provide fast access; each map is denoted as MAP{sl}. The variable {sl} takes values 0

(TrustZone secure) and 1 (TrustZone non-secure).

The following figure illustrates the bitmap.

Figure 8.27 Format for Doorbell Registers Using Bitmaps

HSP_DBELL_{db}_TRIGGER_0

In this write-only register, set a pending flag based on the source ID and the security level of the transaction.

There are seven doorbell trigger registers, where {db} is a value from 0 to 7.

Offset: 0x0 + (db * 0x100) | Read/Write: WO | SCR Protection: None | Reset: NA

Bit Reset Description

31:0 NA DUMMY: Any write to this register sets bit Raw{db}_{sl}[{src}], where {src} and {sl} are the master ID and

TrustZone attribute of the APB write transaction, respectively.

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HSP_DBELL_{db}_ENABLE_0

This register indicates which pending flags can raise the doorbell signal. There are seven doorbell enable

registers, where {db} is a value from 0 to 7.

Offset: 0x4 + (db * 0x100) | Read/Write: R/W | SCR Protection: DB_{db}_REG_0 | Reset: 0x00000000 (0b0000,

0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:16 0 MAP1: Which bits in Raw{db} {db}_{sl}.

{sl} can raise signal doorbell

This field is valid when {sl} = 1, indicating the master is TrustZone non-secure).

15:0 0 MAP0: Which bits in Raw{db} {db}_{sl}.

{sl} can raise signal doorbell

This field is valid when {sl} = 0, indicating the master is TrustZone secure).

HSP_DBELL_{db}_RAW_0

Which flags have been set as a result of a write to the {db}_TRIGGER register.

Offset: 0x8 + (db * 0x100) | Read/Write: RWC | SCR Protection: DB_{db}_REG_0 | Reset: 0x00000000 (0b0000,

0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:16 0 MAP1: Which flags are currently set; writing 1 to a bit clears it.

This field is valid when {sl} = 1, indicating the master is TrustZone non-secure).

15:0 0 MAP0: Which flags are currently set; writing 1 to a bit clears it.

This field is valid when {sl} = 0, indicating the master is TrustZone secure).

HSP_DBELL_{db}_PENDING_0

This register indicates which flags are set and enabled, equivalently the input to the OR reduce function that

controls the signal doorbell_{db}. The read value for {i} is not guaranteed after execution of an operation on {i}.

Offset: 0xc + (db * 0x100) | Read/Write: RWC | SCR Protection: DB_{db}_REG_0 | Reset: 0x00000000 (0b0000,

0000,0000,0000,0000,0000,0000,0000)

Bit Reset Description

31:16 0 MAP1: Which enabled flags are currently set. Writing 1 to a bit clears the equivalent bit in the HSP_DBELL_

{db}_RAW_0 register, and thus implicitly clears the same bit in this register.

This field is valid when {sl} = 1, indicating the master is TrustZone non-secure).

15:0 0 MAP0: Which enabled flags are currently set. Writing 1 to a bit clears the equivalent bit in the HSP_DBELL_

{db}_RAW_0 register, and thus implicitly clears the same bit in this register.

This field is valid when {sl} = 0, indicating the master is TrustZone secure).

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Invalid Registers

HSP, like other blocks, will normally create an APB slave error when invalid registers are accessed. However,

certain addresses do not do this, as follows:

Read and write accesses to the following invalid register addresses do not result in APB slave error response.

0x03c5_0018, 0x03c5_001c, 0x03c5_0020, 0x03c5_0024, 0x03c5_0028, 0x03c5_002c, 0x03c7_0058, 0x03c7_005c

Read accesses to register address 0x03c8_0080 do not result in APB slave error response.

Writing and reading to the invalid register addresses above has no side effect on HSP functionality, so is

harmless, but this failure to report an error could mask programming errors and so HSP users should be aware

of this.

Avoid Use of 0xDEAD1001 in Certain Registers

The HSP returns read data of 0x00000000 if the expected register read data is 0xDEAD1001.

Therefore a software workaround is required to avoid hitting this issue by ensuring the value 0xDEAD1001 is

not returned on register read. This bug affects shared mailboxes, shared semaphores, and arbitrated

semaphores programming.

Shared Mailboxes

Software should not write the value 0xDEAD1001 to HSP_SHRD_MBOX_MBOX_<N>_SHRD_MBOX_0

registers

Shared Semaphores

The affected bit positions are bit 31, 30, 28, 27, 26, 25, 23, 21, 19, 18, 16, 12, and 0. For every

HSP_SHRD_SEM_<N>_SHRD_SMP_STA_SET_0 register, software shall select a bit position, say bit ‘X,’ out

of the affected bit positions and never write ‘1’ to that bit of the register.

Arbitrated Semaphores

The affected bits are bit 31, 30, 28, 27, 26, 25, 23, 21, 19, 18, 16, 12, and 0. For every Software

HSP_ARB_SEM<0/1>_<N>_SMP_GET_0 pair, software shall select a bit position, say a bit ‘X,’ out of the

affected bits and never write ‘1’ to bit ‘X’ of the register.

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8.6 Design for Debugging (DFD)

8.6.1 Overview

The NVIDIA® Xavier series System-on-Chip (SoC) has multiple Design For Debug (DFD) features for

debugging the SoC. The DFD features allow low-level system debug as well as debug of all the processor

cores: the eight ARMv8 Carmel CCPLEX cores; the embedded Cortex-R5 cores; and the Cortex-A9 APE. DFD

enables the use and development of low-level debugging tools that allow developers of a Xavier-based

implementation to place it into known states and monitor its behavior while running. The benefits of this

enhanced DFD implementation include:

A unified CoreSight TAP for all the CPUs in Xavier

Enhanced security and safety

Availability for debug over standard interfaces

Debug and Trace capabilities over functional interfaces

The DFD capability is based on ARM CoreSight 2.0 Architecture.

This chapter describes the Xavier debug blocks and debugging strategies.